^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * M66592 UDC (USB gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006-2007 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "m66592-udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_DESCRIPTION("M66592 USB gadget driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_AUTHOR("Yoshihiro Shimoda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_ALIAS("platform:m66592_udc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_VERSION "21 July 2009"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const char udc_name[] = "m66592_udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const char *m66592_ep_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void disable_controller(struct m66592 *m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void transfer_complete(struct m66592_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct m66592_request *req, int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline u16 get_usb_speed(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) tmp = m66592_read(m66592, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) m66592_bset(m66592, (1 << pipenum), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) m66592_write(m66592, tmp, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tmp = m66592_read(m66592, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) m66592_bclr(m66592, (1 << pipenum), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) m66592_write(m66592, tmp, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void m66592_usb_connect(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void m66592_usb_disconnect(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __releases(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __acquires(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) m66592->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spin_unlock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) m66592->driver->disconnect(&m66592->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_lock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) disable_controller(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) INIT_LIST_HEAD(&m66592->ep[0].queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else if (pipenum < M66592_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pid = m66592_read(m66592, offset) & M66592_PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_err("unexpect pipe num (%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else if (pipenum < M66592_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) m66592_mdfy(m66592, pid, M66592_PID, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pr_err("unexpect pipe num (%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = m66592_read(m66592, M66592_DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else if (pipenum < M66592_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = m66592_read(m66592, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_err("unexpect pipe num (%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pipe_stop(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else if (pipenum < M66592_MAX_NUM_PIPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) offset = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) m66592_bset(m66592, M66592_SQCLR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_err("unexpect pipe num(%d)\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tmp = m66592_read(m66592, M66592_DCPCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if ((tmp & M66592_CNTMD) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tmp = m66592_read(m66592, M66592_DCPMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) size = tmp & M66592_MAXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) m66592_write(m66592, pipenum, M66592_PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tmp = m66592_read(m66592, M66592_PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if ((tmp & M66592_CNTMD) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tmp = m66592_read(m66592, M66592_PIPEBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) size = ((tmp >> 10) + 1) * 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp = m66592_read(m66592, M66592_PIPEMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) size = tmp & M66592_MXPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned short mbw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ndelay(450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (m66592->pdata->on_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mbw = M66592_MBW_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mbw = M66592_MBW_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) m66592_bset(m66592, mbw, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int pipe_buffer_setting(struct m66592 *m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct m66592_pipe_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 bufnum = 0, buf_bsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 pipecfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (info->pipe == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) m66592_write(m66592, info->pipe, M66592_PIPESEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (info->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pipecfg |= M66592_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pipecfg |= info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pipecfg |= info->epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch (info->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case M66592_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) buf_bsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case M66592_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* isochronous pipes may be used as bulk pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (info->pipe >= M66592_BASE_PIPENUM_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) buf_bsize = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pipecfg |= M66592_DBLB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!info->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pipecfg |= M66592_SHTNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case M66592_ISO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bufnum = M66592_BASE_BUFNUM +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) buf_bsize = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pr_err("m66592 pipe memory is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) m66592_write(m66592, pipecfg, M66592_PIPECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (info->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) info->interval--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) m66592_write(m66592, info->interval, M66592_PIPEPERI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void pipe_buffer_release(struct m66592 *m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct m66592_pipe_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (info->pipe == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (is_bulk_pipe(info->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) m66592->bulk--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (is_interrupt_pipe(info->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) m66592->interrupt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else if (is_isoc_pipe(info->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) m66592->isochronous--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (info->type == M66592_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) m66592->bulk--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pr_err("ep_release: unexpect pipenum (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) info->pipe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void pipe_initialize(struct m66592_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned short mbw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) m66592_write(m66592, M66592_ACLRM, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) m66592_write(m66592, 0, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) m66592_write(m66592, M66592_SQCLR, ep->pipectr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ep->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ndelay(450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (m66592->pdata->on_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mbw = M66592_MBW_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mbw = M66592_MBW_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) m66592_bset(m66592, mbw, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 pipenum, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if ((pipenum != 0) && dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (m66592->num_dma == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) m66592->num_dma++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ep->use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ep->fifoaddr = M66592_D0FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ep->fifosel = M66592_D0FIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ep->fifoctr = M66592_D0FIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ep->fifotrn = M66592_D0FIFOTRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) m66592->num_dma++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ep->use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ep->fifoaddr = M66592_D1FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ep->fifosel = M66592_D1FIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ep->fifoctr = M66592_D1FIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ep->fifotrn = M66592_D1FIFOTRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ep->fifoaddr = M66592_CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ep->fifosel = M66592_CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ep->fifoctr = M66592_CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ep->fifotrn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ep->fifoaddr = M66592_CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ep->fifosel = M66592_CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ep->fifoctr = M66592_CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ep->fifotrn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ep->pipectr = get_pipectr_addr(pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ep->pipenum = pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ep->ep.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) m66592->pipenum2ep[pipenum] = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void m66592_ep_release(struct m66592_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (pipenum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ep->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) m66592->num_dma--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ep->pipenum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ep->use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int alloc_pipe_config(struct m66592_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct m66592_pipe_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int *counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ep->ep.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) BUG_ON(ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (m66592->bulk >= M66592_MAX_NUM_BULK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pr_err("bulk pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) info.pipe = M66592_BASE_PIPENUM_ISOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) + m66592->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) counter = &m66592->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) counter = &m66592->bulk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) info.type = M66592_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (m66592->interrupt >= M66592_MAX_NUM_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pr_err("interrupt pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) info.type = M66592_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) counter = &m66592->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pr_err("isochronous pipe is insufficient\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) info.type = M66592_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) counter = &m66592->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pr_err("unexpect xfer type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ep->type = info.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) info.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) info.interval = desc->bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) info.dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) info.dir_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = pipe_buffer_setting(m66592, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pr_err("pipe_buffer_setting fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (*counter)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) m66592->bulk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pipe_initialize(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int free_pipe_config(struct m66592_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct m66592_pipe_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) info.pipe = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) info.type = ep->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pipe_buffer_release(m66592, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) m66592_ep_release(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) enable_irq_ready(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) enable_irq_nrdy(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) disable_irq_ready(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) disable_irq_nrdy(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* if complete is true, gadget driver complete function is not call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void control_end(struct m66592 *m66592, unsigned ccpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) m66592->ep[0].internal_ccpl = ccpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pipe_start(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pipe_change(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) (M66592_ISEL | M66592_CURPIPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) M66592_CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) m66592_write(m66592, M66592_BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (req->req.length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pipe_start(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) irq_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pipe_change(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) disable_irq_empty(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pipe_start(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tmp = m66592_read(m66592, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (unlikely((tmp & M66592_FRDY) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pipe_irq_enable(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) irq_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ep->pipenum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) m66592_mdfy(m66592, M66592_PIPE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (M66592_ISEL | M66592_CURPIPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) M66592_CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) m66592_write(m66592, M66592_BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pipe_start(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pipe_irq_enable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ep->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pipe_change(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) m66592_bset(m66592, M66592_TRENB, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) m66592_write(m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) (req->req.length + ep->ep.maxpacket - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) / ep->ep.maxpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ep->fifotrn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pipe_start(m66592, pipenum); /* trigger once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pipe_irq_enable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) start_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) start_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u16 ctsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) switch (ctsq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case M66592_CS_RDDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) start_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case M66592_CS_WRDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) start_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case M66592_CS_WRND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) control_end(ep->m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void init_controller(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (m66592->pdata->endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) endian = 0; /* big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) endian = M66592_LITTLE; /* little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* This is a workaound for SH7722 2nd cut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) m66592_bset(m66592, 0x1000, M66592_TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) m66592_write(m66592, 0, M66592_CFBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) m66592_write(m66592, 0, M66592_D0FBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) m66592_bset(m66592, endian, M66592_CFBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) m66592_bset(m66592, endian, M66592_D0FBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int clock, vif, irq_sense;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (m66592->pdata->endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) endian = M66592_BIGEND; /* big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) endian = 0; /* little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (m66592->pdata->vif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) vif = M66592_LDRV; /* 3.3v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) vif = 0; /* 1.5v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) switch (m66592->pdata->xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case M66592_PLATDATA_XTAL_12MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) clock = M66592_XTAL12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case M66592_PLATDATA_XTAL_24MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) clock = M66592_XTAL24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case M66592_PLATDATA_XTAL_48MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) clock = M66592_XTAL48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pr_warn("m66592-udc: xtal configuration error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (m66592->irq_trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case IRQF_TRIGGER_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) irq_sense = M66592_INTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case IRQF_TRIGGER_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) irq_sense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pr_warn("m66592-udc: irq trigger config error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) irq_sense = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) m66592_bset(m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (vif & M66592_LDRV) | (endian & M66592_BIGEND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) M66592_PINCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) msleep(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) M66592_DMA0CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void disable_controller(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void m66592_start_xclock(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tmp = m66592_read(m66592, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!(tmp & M66592_XCKE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void transfer_complete(struct m66592_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct m66592_request *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __releases(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __acquires(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (unlikely(ep->pipenum == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (ep->internal_ccpl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ep->internal_ccpl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) list_del_init(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) req->req.status = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) req->req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) restart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_unlock(&ep->m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) usb_gadget_giveback_request(&ep->ep, &req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_lock(&ep->m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) req = list_entry(ep->queue.next, struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ep->ep.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pipe_change(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) m66592_bset(m66592, M66592_ISEL, ep->fifosel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tmp = m66592_read(m66592, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (i++ > 100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pr_err("pipe0 is busy. maybe cpu i/o bus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "conflict. please power off this controller.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ndelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } while ((tmp & M66592_FRDY) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) bufsize = get_buffer_size(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) size = min(bufsize, req->req.length - req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* write fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (size > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) m66592_write_fifo(m66592, ep, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) disable_irq_ready(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) disable_irq_empty(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) disable_irq_ready(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) enable_irq_empty(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pipe_start(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) unsigned bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pipe_change(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) tmp = m66592_read(m66592, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (unlikely((tmp & M66592_FRDY) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pipe_stop(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pipe_irq_disable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pr_err("write fifo not ready. pipnum=%d\n", pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) bufsize = get_buffer_size(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) size = min(bufsize, req->req.length - req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* write fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) m66592_write_fifo(m66592, ep, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if ((size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) || ((size % ep->ep.maxpacket) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) || ((bufsize != ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) && (bufsize > size)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) disable_irq_ready(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) enable_irq_empty(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) disable_irq_empty(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pipe_irq_enable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int rcv_len, bufsize, req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u16 pipenum = ep->pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct m66592 *m66592 = ep->m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int finish = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pipe_change(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) tmp = m66592_read(m66592, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (unlikely((tmp & M66592_FRDY) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) req->req.status = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pipe_stop(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pipe_irq_disable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pr_err("read fifo not ready");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* prepare parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) rcv_len = tmp & M66592_DTLN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) bufsize = get_buffer_size(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) buf = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) req_len = req->req.length - req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (rcv_len < bufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) size = min(rcv_len, req_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) size = min(bufsize, req_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* update parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) req->req.actual += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* check transfer finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if ((!req->req.zero && (req->req.actual == req->req.length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) || (size % ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) || (size == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pipe_stop(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pipe_irq_disable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) finish = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* read fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) m66592_write(m66592, M66592_BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if ((ep->pipenum != 0) && finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u16 check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) M66592_CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ep = &m66592->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) req = list_entry(ep->queue.next, struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) irq_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) check = 1 << pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if ((status & check) && (enb & check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) m66592_write(m66592, ~check, M66592_BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ep = m66592->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) irq_packet_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) irq_packet_read(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u16 check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u16 pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ep = &m66592->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) req = list_entry(ep->queue.next, struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) irq_ep0_write(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) check = 1 << pipenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if ((status & check) && (enb & check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) m66592_write(m66592, ~check, M66592_BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) tmp = control_reg_get(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if ((tmp & M66592_INBUFM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) disable_irq_empty(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pipe_irq_disable(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pipe_stop(m66592, pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ep = m66592->pipenum2ep[pipenum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct m66592_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __releases(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) __acquires(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u16 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) status = 1 << USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pid = control_reg_get_pid(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (pid == M66592_PID_STALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) status = 1 << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pipe_stall(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return; /* exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) m66592->ep0_data = cpu_to_le16(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) m66592->ep0_req->buf = &m66592->ep0_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) m66592->ep0_req->length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* AV: what happens if we get called again before that gets through? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) spin_unlock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) spin_lock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pipe_stop(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) control_reg_sqclr(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ep->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } else if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) pipe_start(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) pipe_stall(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int timeout = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) switch (le16_to_cpu(ctrl->wValue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Wait for the completion of status stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) tmp = m66592_read(m66592, M66592_INTSTS0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) M66592_CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) } while (tmp != M66592_CS_IDST && timeout-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (tmp == M66592_CS_IDST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) m66592_bset(m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) le16_to_cpu(ctrl->wIndex >> 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) M66592_TESTMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) pipe_stall(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u16 w_index = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pipe_stall(m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) control_end(m66592, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pipe_stall(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* if return value is true, call class driver's setup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u16 *p = (u16 *)ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) unsigned long offset = M66592_USBREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* read fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) p[i] = m66592_read(m66592, offset + i*2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* check request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) get_status(m66592, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) clear_feature(m66592, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) set_feature(m66592, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static void m66592_update_usb_speed(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u16 speed = get_usb_speed(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case M66592_HSMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) m66592->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case M66592_FSMODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) m66592->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) m66592->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pr_err("USB speed unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static void irq_device_state(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u16 dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (dvsq == M66592_DS_DFLT) { /* bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) usb_gadget_udc_reset(&m66592->gadget, m66592->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) m66592_update_usb_speed(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) m66592_update_usb_speed(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) && m66592->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) m66592_update_usb_speed(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) m66592->old_dvsq = dvsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static void irq_control_stage(struct m66592 *m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) __releases(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) __acquires(m66592->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct usb_ctrlrequest ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u16 ctsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) switch (ctsq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case M66592_CS_IDST: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ep = &m66592->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) req = list_entry(ep->queue.next, struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) transfer_complete(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) case M66592_CS_RDDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case M66592_CS_WRDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case M66592_CS_WRND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (setup_packet(m66592, &ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) spin_unlock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pipe_stall(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) spin_lock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case M66592_CS_RDSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) case M66592_CS_WRSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) control_end(m66592, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static irqreturn_t m66592_irq(int irq, void *_m66592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct m66592 *m66592 = _m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u16 intsts0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) u16 intenb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u16 savepipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) u16 mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) spin_lock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) intsts0 = m66592_read(m66592, M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) intenb0 = m66592_read(m66592, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * When USB clock stops, it cannot read register. Even if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * clock stops, the interrupt occurs. So this driver turn on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * a clock by this timing and do re-reading of register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) m66592_start_xclock(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) intsts0 = m66592_read(m66592, M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) intenb0 = m66592_read(m66592, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) savepipe = m66592_read(m66592, M66592_CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mask0 = intsts0 & intenb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (mask0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u16 brdysts = m66592_read(m66592, M66592_BRDYSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u16 bempsts = m66592_read(m66592, M66592_BEMPSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) u16 brdyenb = m66592_read(m66592, M66592_BRDYENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) u16 bempenb = m66592_read(m66592, M66592_BEMPENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (mask0 & M66592_VBINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) m66592_write(m66592, 0xffff & ~M66592_VBINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) M66592_INTSTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) m66592_start_xclock(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* start vbus sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) & M66592_VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) m66592->scount = M66592_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mod_timer(&m66592->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (intsts0 & M66592_DVSQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) irq_device_state(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) && (brdysts & brdyenb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) irq_pipe_ready(m66592, brdysts, brdyenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) && (bempsts & bempenb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) irq_pipe_empty(m66592, bempsts, bempenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (intsts0 & M66592_CTRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) irq_control_stage(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) m66592_write(m66592, savepipe, M66592_CFIFOSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spin_unlock(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void m66592_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct m66592 *m66592 = from_timer(m66592, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) spin_lock_irqsave(&m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) tmp = m66592_read(m66592, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!(tmp & M66592_RCKE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (m66592->scount > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (tmp == m66592->old_vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) m66592->scount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (m66592->scount == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (tmp == M66592_VBSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) m66592_usb_connect(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) m66592_usb_disconnect(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mod_timer(&m66592->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) m66592->scount = M66592_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) m66592->old_vbus = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mod_timer(&m66592->timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) spin_unlock_irqrestore(&m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int m66592_enable(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return alloc_pipe_config(ep, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static int m66592_disable(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) BUG_ON(!ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) req = list_entry(ep->queue.next, struct m66592_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) spin_lock_irqsave(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) transfer_complete(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) spin_unlock_irqrestore(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pipe_irq_disable(ep->m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return free_pipe_config(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) req = kzalloc(sizeof(struct m66592_request), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) INIT_LIST_HEAD(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return &req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) req = container_of(_req, struct m66592_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int request = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) req = container_of(_req, struct m66592_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) spin_lock_irqsave(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) request = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) list_add_tail(&req->queue, &ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) req->req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (ep->ep.desc == NULL) /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) start_ep0(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (request && !ep->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) start_packet(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) spin_unlock_irqrestore(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct m66592_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) req = container_of(_req, struct m66592_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) spin_lock_irqsave(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) transfer_complete(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) spin_unlock_irqrestore(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int m66592_set_halt(struct usb_ep *_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct m66592_ep *ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) spin_lock_irqsave(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) } else if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ep->busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pipe_stall(ep->m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ep->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) pipe_stop(ep->m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) spin_unlock_irqrestore(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static void m66592_fifo_flush(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct m66592_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ep = container_of(_ep, struct m66592_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) spin_lock_irqsave(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (list_empty(&ep->queue) && !ep->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pipe_stop(ep->m66592, ep->pipenum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) spin_unlock_irqrestore(&ep->m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const struct usb_ep_ops m66592_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .enable = m66592_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .disable = m66592_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .alloc_request = m66592_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .free_request = m66592_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .queue = m66592_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .dequeue = m66592_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .set_halt = m66592_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .fifo_flush = m66592_fifo_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static int m66592_udc_start(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct m66592 *m66592 = to_m66592(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* hook up the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) driver->driver.bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) m66592->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) m66592_start_xclock(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* start vbus sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) m66592->old_vbus = m66592_read(m66592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) M66592_INTSTS0) & M66592_VBSTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) m66592->scount = M66592_MAX_SAMPLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int m66592_udc_stop(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct m66592 *m66592 = to_m66592(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) init_controller(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) disable_controller(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) m66592->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static int m66592_get_frame(struct usb_gadget *_gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct m66592 *m66592 = gadget_to_m66592(_gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int m66592_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct m66592 *m66592 = gadget_to_m66592(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) spin_lock_irqsave(&m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) spin_unlock_irqrestore(&m66592->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static const struct usb_gadget_ops m66592_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .get_frame = m66592_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .udc_start = m66592_udc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .udc_stop = m66592_udc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .pullup = m66592_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static int m66592_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct m66592 *m66592 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) usb_del_gadget_udc(&m66592->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) del_timer_sync(&m66592->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) iounmap(m66592->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) free_irq(platform_get_irq(pdev, 0), m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) clk_disable(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) clk_put(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) kfree(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static void nop_completion(struct usb_ep *ep, struct usb_request *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static int m66592_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct resource *res, *ires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) void __iomem *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct m66592 *m66592 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) char clk_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pr_err("platform_get_resource error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (!ires) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) "platform_get_resource IORESOURCE_IRQ error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) reg = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (reg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) pr_err("ioremap error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (dev_get_platdata(&pdev->dev) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* initialize ucd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (m66592 == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) m66592->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) spin_lock_init(&m66592->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) platform_set_drvdata(pdev, m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) m66592->gadget.ops = &m66592_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) m66592->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) m66592->gadget.name = udc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) timer_setup(&m66592->timer, m66592_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) m66592->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ret = request_irq(ires->start, m66592_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) udc_name, m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) pr_err("request_irq error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) goto clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) m66592->clk = clk_get(&pdev->dev, clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (IS_ERR(m66592->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ret = PTR_ERR(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) goto clean_up2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) clk_enable(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) INIT_LIST_HEAD(&m66592->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) m66592->gadget.ep0 = &m66592->ep[0].ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct m66592_ep *ep = &m66592->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (i != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) list_add_tail(&m66592->ep[i].ep.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) &m66592->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ep->m66592 = m66592;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ep->ep.name = m66592_ep_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ep->ep.ops = &m66592_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) usb_ep_set_maxpacket_limit(&ep->ep, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) usb_ep_set_maxpacket_limit(&m66592->ep[0].ep, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) m66592->ep[0].pipenum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) m66592->ep[0].fifoaddr = M66592_CFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) m66592->ep[0].fifosel = M66592_CFIFOSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) m66592->ep[0].fifoctr = M66592_CFIFOCTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) m66592->ep[0].fifotrn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) m66592->ep[0].pipectr = get_pipectr_addr(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) m66592->pipenum2ep[0] = &m66592->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) m66592->epaddr2ep[0] = &m66592->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (m66592->ep0_req == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto clean_up3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) m66592->ep0_req->complete = nop_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) init_controller(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) goto err_add_udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) err_add_udc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) m66592->ep0_req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) clean_up3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (m66592->pdata->on_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) clk_disable(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) clk_put(m66592->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) clean_up2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) free_irq(ires->start, m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) clean_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (m66592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (m66592->ep0_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) kfree(m66592);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static struct platform_driver m66592_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .remove = m66592_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .name = udc_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) module_platform_driver_probe(m66592_driver, m66592_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags