^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Faraday FOTG210 USB OTG controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Faraday Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FOTG210_GMIR 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GMIR_INT_POLARITY 0x8 /*Active High*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GMIR_MHC_INT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GMIR_MOTG_INT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GMIR_MDEV_INT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Device Main Control Register(0x100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FOTG210_DMCR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMCR_HS_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMCR_CHIP_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMCR_SFRST (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMCR_GOSUSP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMCR_GLINT_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMCR_HALF_SPEED (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMCR_CAP_RMWAKUP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Device Address Register(0x104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FOTG210_DAR 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DAR_AFT_CONF (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Device Test Register(0x108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FOTG210_DTR 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DTR_TST_CLRFF (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* PHY Test Mode Selector register(0x114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FOTG210_PHYTMSR 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHYTMSR_TST_PKT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHYTMSR_TST_SE0NAK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHYTMSR_TST_KSTA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHYTMSR_TST_JSTA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHYTMSR_UNPLUG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Cx configuration and FIFO Empty Status register(0x120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FOTG210_DCFESR 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DCFESR_CX_EMP (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DCFESR_CX_CLR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DCFESR_CX_STL (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DCFESR_TST_PKDONE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DCFESR_CX_DONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Device IDLE Counter Register(0x124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FOTG210_DICR 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Device Mask of Interrupt Group Register (0x130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FOTG210_DMIGR 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMIGR_MINT_G0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Device Mask of Interrupt Source Group 0(0x134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FOTG210_DMISGR0 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMISGR0_MCX_COMEND (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMISGR0_MCX_OUT_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMISGR0_MCX_IN_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMISGR0_MCX_SETUP_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Device Mask of Interrupt Source Group 1 Register(0x138)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FOTG210_DMISGR1 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMISGR1_MF3_IN_INT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMISGR1_MF2_IN_INT (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DMISGR1_MF1_IN_INT (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMISGR1_MF0_IN_INT (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DMISGR1_MF3_SPK_INT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DMISGR1_MF3_OUT_INT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DMISGR1_MF2_SPK_INT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DMISGR1_MF2_OUT_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMISGR1_MF1_SPK_INT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMISGR1_MF1_OUT_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMISGR1_MF0_SPK_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DMISGR1_MF0_OUT_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Device Mask of Interrupt Source Group 2 Register (0x13C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FOTG210_DMISGR2 0x13C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DMISGR2_MDMA_ERROR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DMISGR2_MDMA_CMPLT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Device Interrupt group Register (0x140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FOTG210_DIGR 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DIGR_INT_G2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DIGR_INT_G1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DIGR_INT_G0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Device Interrupt Source Group 0 Register (0x144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FOTG210_DISGR0 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DISGR0_CX_COMABT_INT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DISGR0_CX_COMFAIL_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DISGR0_CX_COMEND_INT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DISGR0_CX_OUT_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DISGR0_CX_IN_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DISGR0_CX_SETUP_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Device Interrupt Source Group 1 Register (0x148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FOTG210_DISGR1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DISGR1_IN_INT(fifo) (1 << 16 << (fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Device Interrupt Source Group 2 Register (0x14C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FOTG210_DISGR2 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DISGR2_DMA_ERROR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DISGR2_DMA_CMPLT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DISGR2_RX0BYTE_INT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DISGR2_TX0BYTE_INT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DISGR2_ISO_SEQ_ABORT_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DISGR2_ISO_SEQ_ERR_INT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DISGR2_RESM_INT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DISGR2_SUSP_INT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DISGR2_USBRST_INT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Device Receive Zero-Length Data Packet Register (0x150)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FOTG210_RX0BYTE 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RX0BYTE_EP8 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RX0BYTE_EP7 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RX0BYTE_EP6 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RX0BYTE_EP5 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RX0BYTE_EP4 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RX0BYTE_EP3 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RX0BYTE_EP2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RX0BYTE_EP1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Device Transfer Zero-Length Data Packet Register (0x154)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define FOTG210_TX0BYTE 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TX0BYTE_EP8 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TX0BYTE_EP7 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TX0BYTE_EP6 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TX0BYTE_EP5 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TX0BYTE_EP4 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TX0BYTE_EP3 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TX0BYTE_EP2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TX0BYTE_EP1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define INOUTEPMPSR_STL_EP (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define INOUTEPMPSR_RESET_TSEQ (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Device Endpoint 1~4 Map Register (0x1A0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FOTG210_EPMAP 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EPMAP_FIFONO(ep, dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EPMAP_FIFONOMSK(ep, dir) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Device FIFO Map Register (0x1A8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FOTG210_FIFOMAP 0x1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Device FIFO Confuguration Register (0x1AC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FOTG210_FIFOCF 0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FIBCR_BCFX 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FIBCR_FFRST (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Device DMA Target FIFO Number Register (0x1C0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define FOTG210_DMATFNR 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DMATFNR_ACC_CXF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DMATFNR_ACC_F3 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DMATFNR_ACC_F2 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DMATFNR_ACC_F1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DMATFNR_ACC_F0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DMATFNR_ACC_FN(fifo) (1 << (fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DMATFNR_DISDMA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Device DMA Controller Parameter setting 1 Register (0x1C8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FOTG210_DMACPSR1 0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DMACPSR1_DMA_ABORT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DMACPSR1_DMA_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Device DMA Controller Parameter setting 2 Register (0x1CC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FOTG210_DMACPSR2 0x1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Device DMA Controller Parameter setting 3 Register (0x1CC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define FOTG210_CXPORT 0x1D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct fotg210_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct usb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct fotg210_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct fotg210_udc *fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned stall:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned wedged:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned use_dma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned char epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned char type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned char dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct usb_endpoint_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct fotg210_udc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spinlock_t lock; /* protect the struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long irq_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct fotg210_ep *ep[FOTG210_MAX_NUM_EP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct usb_request *ep0_req; /* for internal request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __le16 ep0_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 ep0_dir; /* 0/0x80 out/in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 reenum; /* if re-enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags