^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FOTG210 UDC Driver supports Bulk transfer so far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Faraday Technology Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "fotg210.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRIVER_DESC "FOTG210 USB Device Controller Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRIVER_VERSION "30-April-2013"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const char udc_name[] = "fotg210_udc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char * const fotg210_ep_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "ep0", "ep1", "ep2", "ep3", "ep4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) value |= DCFESR_CX_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) iowrite32(value, fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) list_del_init(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* don't modify queue heads during completion callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) req->req.status = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) req->req.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spin_unlock(&ep->fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) usb_gadget_giveback_request(&ep->ep, &req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) spin_lock(&ep->fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ep->epnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) fotg210_disable_fifo_int(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) fotg210_set_cxdone(ep->fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Driver should map an ep to a fifo and then map the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * to the ep. What a brain-damaged design!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* map a fifo to an ep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = ioread32(fotg210->reg + FOTG210_EPMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val |= EPMAP_FIFONO(epnum, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite32(val, fotg210->reg + FOTG210_EPMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* map the ep to the fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val &= ~FIFOMAP_EPNOMSK(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val |= FIFOMAP_EPNO(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* enable fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = ioread32(fotg210->reg + FOTG210_FIFOCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val |= FIFOCF_FIFO_EN(epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val = ioread32(fotg210->reg + FOTG210_FIFOCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val |= FIFOCF_TYPE(type, epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FOTG210_OUTEPMPSR(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val = ioread32(fotg210->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val |= INOUTEPMPSR_MPS(mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) iowrite32(val, fotg210->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int fotg210_config_ep(struct fotg210_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) fotg210_set_tfrtype(ep, ep->epnum, ep->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fotg210->ep[ep->epnum] = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int fotg210_ep_enable(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct fotg210_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ep = container_of(_ep, struct fotg210_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ep->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ep->epnum = usb_endpoint_num(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ep->type = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ep->dir_in = usb_endpoint_dir_in(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ep->ep.maxpacket = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return fotg210_config_ep(ep, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct fotg210_ep *ep = fotg210->ep[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = (ep->dir_in) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) fotg210->reg + FOTG210_INEPMPSR(epnum) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fotg210->reg + FOTG210_OUTEPMPSR(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * bit. Controller wouldn't clear this bit. WTF!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) value |= INOUTEPMPSR_RESET_TSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) value &= ~INOUTEPMPSR_RESET_TSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int fotg210_ep_release(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!ep->epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ep->epnum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ep->stall = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ep->wedged = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fotg210_reset_tseq(ep->fotg210, ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int fotg210_ep_disable(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct fotg210_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BUG_ON(!_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ep = container_of(_ep, struct fotg210_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct fotg210_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) spin_lock_irqsave(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) fotg210_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) spin_unlock_irqrestore(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return fotg210_ep_release(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) INIT_LIST_HEAD(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return &req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void fotg210_ep_free_request(struct usb_ep *_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) req = container_of(_req, struct fotg210_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void fotg210_enable_dma(struct fotg210_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dma_addr_t d, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* set transfer length and direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* set device DMA target FIFO number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) value = ioread32(fotg210->reg + FOTG210_DMATFNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ep->epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) value |= DMATFNR_ACC_FN(ep->epnum - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) value |= DMATFNR_ACC_CXF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* set DMA memory address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* enable MDMA_EROR and MDMA_CMPLT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) value = ioread32(fotg210->reg + FOTG210_DMISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) value |= DMACPSR1_DMA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void fotg210_disable_dma(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void fotg210_wait_dma_done(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if ((value & DISGR2_USBRST_INT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (value & DISGR2_DMA_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto dma_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } while (!(value & DISGR2_DMA_CMPLT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) value &= ~DISGR2_DMA_CMPLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dma_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) value |= DMACPSR1_DMA_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* reset fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ep->epnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) value = ioread32(ep->fotg210->reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FOTG210_FIBCR(ep->epnum - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) value |= FIBCR_FFRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iowrite32(value, ep->fotg210->reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FOTG210_FIBCR(ep->epnum - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) value |= DCFESR_CX_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void fotg210_start_dma(struct fotg210_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct fotg210_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct device *dev = &ep->fotg210->gadget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dma_addr_t d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ep->epnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) buffer = req->req.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) length = req->req.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) buffer = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) length = ioread32(ep->fotg210->reg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (length > req->req.length - req->req.actual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) length = req->req.length - req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) buffer = req->req.buf + req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (req->req.length - req->req.actual > ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) length = ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) length = req->req.length - req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) d = dma_map_single(dev, buffer, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (dma_mapping_error(dev, d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("dma_mapping_error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) fotg210_enable_dma(ep, d, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* check if dma is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) fotg210_wait_dma_done(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) fotg210_disable_dma(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* update actual transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) req->req.actual += length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dma_unmap_single(dev, d, length, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void fotg210_ep0_queue(struct fotg210_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct fotg210_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!req->req.length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ep->dir_in) { /* if IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fotg210_start_dma(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (req->req.length == req->req.actual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } else { /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) value &= ~DMISGR0_MCX_OUT_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct fotg210_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int request = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ep = container_of(_ep, struct fotg210_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) req = container_of(_req, struct fotg210_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spin_lock_irqsave(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) request = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) list_add_tail(&req->queue, &ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) req->req.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!ep->epnum) /* ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) fotg210_ep0_queue(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else if (request && !ep->stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fotg210_enable_fifo_int(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct fotg210_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ep = container_of(_ep, struct fotg210_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) req = container_of(_req, struct fotg210_request, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spin_lock_irqsave(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fotg210_done(ep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) spin_unlock_irqrestore(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void fotg210_set_epnstall(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* check if IN FIFO is empty before stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) value = ioread32(fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg = (ep->dir_in) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) value |= INOUTEPMPSR_STL_EP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void fotg210_clear_epnstall(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reg = (ep->dir_in) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) value &= ~INOUTEPMPSR_STL_EP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct fotg210_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct fotg210_udc *fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ep = container_of(_ep, struct fotg210_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spin_lock_irqsave(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fotg210_set_epnstall(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ep->stall = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (wedge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ep->wedged = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fotg210_reset_tseq(fotg210, ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fotg210_clear_epnstall(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ep->stall = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ep->wedged = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!list_empty(&ep->queue))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) fotg210_enable_fifo_int(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_unlock_irqrestore(&ep->fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return fotg210_set_halt_and_wedge(_ep, value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int fotg210_ep_set_wedge(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return fotg210_set_halt_and_wedge(_ep, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct usb_ep_ops fotg210_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .enable = fotg210_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .disable = fotg210_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .alloc_request = fotg210_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .free_request = fotg210_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .queue = fotg210_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .dequeue = fotg210_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .set_halt = fotg210_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .fifo_flush = fotg210_ep_fifo_flush,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .set_wedge = fotg210_ep_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) | TX0BYTE_EP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) | RX0BYTE_EP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* read 8-byte setup packet only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 *tmp = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = (length >> 2); i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) data = ioread32(fotg210->reg + FOTG210_CXPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *tmp = data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *(tmp + 1) = (data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *(tmp + 2) = (data >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *(tmp + 3) = (data >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tmp = tmp + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) switch (length % 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) data = ioread32(fotg210->reg + FOTG210_CXPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *tmp = data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) data = ioread32(fotg210->reg + FOTG210_CXPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *tmp = data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *(tmp + 1) = (data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) data = ioread32(fotg210->reg + FOTG210_CXPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *tmp = data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *(tmp + 1) = (data >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *(tmp + 2) = (data >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void fotg210_set_configuration(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 value = ioread32(fotg210->reg + FOTG210_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) value |= DAR_AFT_CONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) iowrite32(value, fotg210->reg + FOTG210_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 value = ioread32(fotg210->reg + FOTG210_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) value |= (addr & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) iowrite32(value, fotg210->reg + FOTG210_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) value |= DCFESR_CX_STL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) iowrite32(value, fotg210->reg + FOTG210_DCFESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void fotg210_request_error(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fotg210_set_cxstall(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pr_err("request error!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static void fotg210_set_address(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ctrl->wValue >= 0x0100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) fotg210_request_error(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fotg210_set_dev_addr(fotg210, ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static void fotg210_set_feature(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case USB_RECIP_ENDPOINT: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fotg210_set_epnstall(fotg210->ep[epnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fotg210_set_cxstall(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fotg210_request_error(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void fotg210_clear_feature(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct fotg210_ep *ep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ep->wedged) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ep->stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) fotg210_request_error(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int fotg210_is_epnstall(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct fotg210_udc *fotg210 = ep->fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) reg = (ep->dir_in) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return value & INOUTEPMPSR_STL_EP ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void fotg210_get_status(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fotg210->ep0_data = 1 << USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) fotg210->ep0_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fotg210->ep0_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) fotg210_is_epnstall(fotg210->ep[epnum])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) fotg210_request_error(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) fotg210_request_error(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return; /* exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) fotg210->ep0_req->buf = &fotg210->ep0_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) fotg210->ep0_req->length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) spin_unlock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) spin_lock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int fotg210_setup_packet(struct fotg210_udc *fotg210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) u8 *p = (u8 *)ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u8 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fotg210_rdsetupp(fotg210, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) fotg210->gadget.speed = value & DMCR_HS_EN ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) USB_SPEED_HIGH : USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* check request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) fotg210_get_status(fotg210, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fotg210_clear_feature(fotg210, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) fotg210_set_feature(fotg210, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fotg210_set_address(fotg210, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case USB_REQ_SET_CONFIGURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fotg210_set_configuration(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void fotg210_ep0out(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct fotg210_ep *ep = fotg210->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!list_empty(&ep->queue) && !ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) req = list_first_entry(&ep->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct fotg210_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (req->req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) fotg210_start_dma(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pr_err("%s : empty queue\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void fotg210_ep0in(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct fotg210_ep *ep = fotg210->ep[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct fotg210_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct fotg210_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (req->req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) fotg210_start_dma(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (req->req.actual == req->req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) fotg210_set_cxdone(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) value &= ~DISGR0_CX_COMABT_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) iowrite32(value, fotg210->reg + FOTG210_DISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct fotg210_request *req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct fotg210_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (req->req.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) fotg210_start_dma(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct fotg210_request *req = list_entry(ep->queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct fotg210_request, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) fotg210_start_dma(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Complete the request when it's full or a short packet arrived.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * Like other drivers, short_not_ok isn't handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (req->req.length == req->req.actual ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) fotg210_done(ep, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static irqreturn_t fotg210_irq(int irq, void *_fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct fotg210_udc *fotg210 = _fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int_grp &= ~int_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_lock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (int_grp & DIGR_INT_G2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 int_grp2 = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) int_grp2 &= ~int_msk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (int_grp2 & DISGR2_USBRST_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) value &= ~DISGR2_USBRST_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pr_info("fotg210 udc reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (int_grp2 & DISGR2_SUSP_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) value &= ~DISGR2_SUSP_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pr_info("fotg210 udc suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (int_grp2 & DISGR2_RESM_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) value &= ~DISGR2_RESM_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pr_info("fotg210 udc resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) value &= ~DISGR2_ISO_SEQ_ERR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pr_info("fotg210 iso sequence error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) value &= ~DISGR2_ISO_SEQ_ABORT_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pr_info("fotg210 iso sequence abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (int_grp2 & DISGR2_TX0BYTE_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) fotg210_clear_tx0byte(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) value &= ~DISGR2_TX0BYTE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pr_info("fotg210 transferred 0 byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (int_grp2 & DISGR2_RX0BYTE_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fotg210_clear_rx0byte(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) value &= ~DISGR2_RX0BYTE_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pr_info("fotg210 received 0 byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (int_grp2 & DISGR2_DMA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) value = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) value &= ~DISGR2_DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) iowrite32(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (int_grp & DIGR_INT_G0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 int_grp0 = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct usb_ctrlrequest ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int_grp0 &= ~int_msk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* the highest priority in this source register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (int_grp0 & DISGR0_CX_COMABT_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) fotg210_clear_comabt_int(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pr_info("fotg210 CX command abort\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (int_grp0 & DISGR0_CX_SETUP_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (fotg210_setup_packet(fotg210, &ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) spin_unlock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (fotg210->driver->setup(&fotg210->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) &ctrl) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) fotg210_set_cxstall(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) spin_lock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (int_grp0 & DISGR0_CX_COMEND_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) pr_info("fotg210 cmd end\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (int_grp0 & DISGR0_CX_IN_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fotg210_ep0in(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (int_grp0 & DISGR0_CX_OUT_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fotg210_ep0out(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) fotg210_set_cxstall(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pr_info("fotg210 ep0 fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (int_grp & DIGR_INT_G1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 int_grp1 = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int_grp1 &= ~int_msk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (int_grp1 & DISGR1_IN_INT(fifo))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) (int_grp1 & DISGR1_SPK_INT(fifo)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) spin_unlock(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) reg &= ~PHYTMSR_UNPLUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int fotg210_udc_start(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* hook up the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) driver->driver.bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) fotg210->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* enable device global interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) value = ioread32(fotg210->reg + FOTG210_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) value |= DMCR_GLINT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) iowrite32(value, fotg210->reg + FOTG210_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void fotg210_init(struct fotg210_udc *fotg210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* disable global interrupt and set int polarity to active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) fotg210->reg + FOTG210_GMIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* disable device global interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) value = ioread32(fotg210->reg + FOTG210_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) value &= ~DMCR_GLINT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) iowrite32(value, fotg210->reg + FOTG210_DMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* enable only grp2 irqs we handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) fotg210->reg + FOTG210_DMISGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* disable all fifo interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* disable cmd end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) value = ioread32(fotg210->reg + FOTG210_DMISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) value |= DMISGR0_MCX_COMEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int fotg210_udc_stop(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) spin_lock_irqsave(&fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) fotg210_init(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fotg210->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) spin_unlock_irqrestore(&fotg210->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct usb_gadget_ops fotg210_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .udc_start = fotg210_udc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .udc_stop = fotg210_udc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int fotg210_udc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) usb_del_gadget_udc(&fotg210->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) iounmap(fotg210->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) free_irq(platform_get_irq(pdev, 0), fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) kfree(fotg210->ep[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) kfree(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int fotg210_udc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct resource *res, *ires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct fotg210_udc *fotg210 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pr_err("platform_get_resource error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!ires) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* initialize udc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (fotg210 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (_ep[i] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) fotg210->ep[i] = _ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fotg210->reg = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (fotg210->reg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) pr_err("ioremap error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) spin_lock_init(&fotg210->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) platform_set_drvdata(pdev, fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) fotg210->gadget.ops = &fotg210_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) fotg210->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) fotg210->gadget.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) fotg210->gadget.name = udc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) INIT_LIST_HEAD(&fotg210->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct fotg210_ep *ep = fotg210->ep[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) list_add_tail(&fotg210->ep[i]->ep.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) &fotg210->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ep->fotg210 = fotg210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) INIT_LIST_HEAD(&ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ep->ep.name = fotg210_ep_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ep->ep.ops = &fotg210_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (fotg210->ep0_req == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) goto err_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) fotg210_init(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) fotg210_disable_unplug(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) udc_name, fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pr_err("request_irq error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) goto err_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto err_add_udc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) err_add_udc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) free_irq(ires->start, fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) err_req:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) err_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) iounmap(fotg210->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) kfree(fotg210->ep[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) kfree(fotg210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static struct platform_driver fotg210_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .name = udc_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .probe = fotg210_udc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .remove = fotg210_udc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) module_platform_driver(fotg210_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) MODULE_DESCRIPTION(DRIVER_DESC);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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