Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * xhci-dbc.h - xHCI debug capability early driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2016 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Lu Baolu <baolu.lu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __LINUX_XHCI_DBC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __LINUX_XHCI_DBC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * xHCI Debug Capability Register interfaces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct xdbc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	__le32	capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	__le32	doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	__le32	ersts;		/* Event Ring Segment Table Size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	__le32	__reserved_0;	/* 0c~0f reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	__le64	erstba;		/* Event Ring Segment Table Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	__le64	erdp;		/* Event Ring Dequeue Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	__le32	control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	__le32	status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	__le32	portsc;		/* Port status and control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	__le32	__reserved_1;	/* 2b~28 reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	__le64	dccp;		/* Debug Capability Context Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	__le32	devinfo1;	/* Device Descriptor Info Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	__le32	devinfo2;	/* Device Descriptor Info Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DEBUG_MAX_BURST(p)	(((p) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CTRL_DBC_RUN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CTRL_PORT_ENABLE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CTRL_HALT_OUT_TR	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CTRL_HALT_IN_TR		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CTRL_DBC_RUN_CHANGE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CTRL_DBC_ENABLE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DCST_DEBUG_PORT(p)	(((p) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PORTSC_CONN_STATUS	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PORTSC_CONN_CHANGE	BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PORTSC_RESET_CHANGE	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PORTSC_LINK_CHANGE	BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PORTSC_CONFIG_CHANGE	BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * xHCI Debug Capability data structures:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct xdbc_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	__le32 field[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct xdbc_erst_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	__le64	seg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	__le32	seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__le32	__reserved_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) struct xdbc_info_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__le64	string0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__le64	manufacturer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__le64	product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__le64	serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__le32	length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__le32	__reserved_0[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct xdbc_ep_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__le32	ep_info1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__le32	ep_info2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__le64	deq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	__le32	tx_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__le32	__reserved_0[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) struct xdbc_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct xdbc_info_context	info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct xdbc_ep_context		out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct xdbc_ep_context		in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define XDBC_INFO_CONTEXT_SIZE		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define XDBC_MAX_STRING_LENGTH		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define XDBC_STRING_MANUFACTURER	"Linux Foundation"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define XDBC_STRING_PRODUCT		"Linux USB GDB Target"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define XDBC_STRING_SERIAL		"0001"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct xdbc_strings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	char	string0[XDBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	char	manufacturer[XDBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	char	product[XDBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	char	serial[XDBC_MAX_STRING_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XDBC_PROTOCOL		1	/* GNU Remote Debug Command Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XDBC_VENDOR_ID		0x1d6b	/* Linux Foundation 0x1d6b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XDBC_PRODUCT_ID		0x0011	/* __le16 idProduct; device 0011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XDBC_DEVICE_REV		0x0010	/* 0.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * xHCI Debug Capability software state structures:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct xdbc_segment {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct xdbc_trb		*trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	dma_addr_t		dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XDBC_TRBS_PER_SEGMENT	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct xdbc_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct xdbc_segment	*segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct xdbc_trb		*enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct xdbc_trb		*dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32			cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * These are the "Endpoint ID" (also known as "Context Index") values for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * OUT Transfer Ring and the IN Transfer Ring of a Debug Capability Context data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * According to the "eXtensible Host Controller Interface for Universal Serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * Bus (xHCI)" specification, section "7.6.3.2 Endpoint Contexts and Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * Rings", these should be 0 and 1, and those are the values AMD machines give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * you; but Intel machines seem to use the formula from section "4.5.1 Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * Context Index", which is supposed to be used for the Device Context only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * Luckily the values from Intel don't overlap with those from AMD, so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * just test for both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define XDBC_EPID_OUT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XDBC_EPID_IN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define XDBC_EPID_OUT_INTEL	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XDBC_EPID_IN_INTEL	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct xdbc_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u16			vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u16			device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u32			bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32			dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32			func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	void __iomem		*xhci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u64			xhci_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	size_t			xhci_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int			port_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* DbC register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct xdbc_regs __iomem *xdbc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* DbC table page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	dma_addr_t		table_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	void			*table_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* event ring segment table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dma_addr_t		erst_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	size_t			erst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	void			*erst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* event ring segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct xdbc_ring	evt_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct xdbc_segment	evt_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* debug capability contexts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	dma_addr_t		dbcc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	size_t			dbcc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	void			*dbcc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* descriptor strings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	dma_addr_t		string_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	size_t			string_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	void			*string_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* bulk OUT endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct xdbc_ring	out_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct xdbc_segment	out_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	void			*out_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	dma_addr_t		out_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* bulk IN endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct xdbc_ring	in_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct xdbc_segment	in_seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	void			*in_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	dma_addr_t		in_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* spinlock for early_xdbc_write() reentrancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	raw_spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define XDBC_PCI_MAX_BUSES	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define XDBC_PCI_MAX_DEVICES	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XDBC_PCI_MAX_FUNCTION	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define XDBC_TABLE_ENTRY_SIZE	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define XDBC_ERST_ENTRY_NUM	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define XDBC_DBCC_ENTRY_NUM	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define XDBC_STRING_ENTRY_NUM	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Bits definitions for xdbc_state.flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define XDBC_FLAGS_INITIALIZED	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define XDBC_FLAGS_IN_STALL	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define XDBC_FLAGS_OUT_STALL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define XDBC_FLAGS_IN_PROCESS	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define XDBC_FLAGS_OUT_PROCESS	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define XDBC_FLAGS_CONFIGURED	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define XDBC_MAX_PACKET		1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Door bell target: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OUT_EP_DOORBELL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IN_EP_DOORBELL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DOOR_BELL_TARGET(p)	(((p) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define xdbc_read64(regs)	xhci_read_64(NULL, (regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define xdbc_write64(val, regs)	xhci_write_64(NULL, (val), (regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif /* __LINUX_XHCI_DBC_H */