^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * xhci-dbc.c - xHCI debug capability early driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Lu Baolu <baolu.lu@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/usb/xhci-dbgp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../host/xhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "xhci-dbc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct xdbc_state xdbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static bool early_console_keep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef XDBC_TRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define xdbc_trace trace_printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void xdbc_trace(const char *fmt, ...) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif /* XDBC_TRACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void __iomem * __init xdbc_map_pci_mmio(u32 bus, u32 dev, u32 func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u64 val64, sz64, mask64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 val, sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (val == 0xffffffff || sz == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) pr_notice("invalid mmio bar\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val64 = val & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mask64 = PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val64 |= (u64)val << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) sz64 |= (u64)sz << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mask64 |= ~0ULL << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) sz64 &= mask64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!sz64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_notice("invalid mmio address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sz64 = 1ULL << __ffs64(sz64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Check if the mem space is enabled: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) byte = read_pci_config_byte(bus, dev, func, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!(byte & PCI_COMMAND_MEMORY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) byte |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) write_pci_config_byte(bus, dev, func, PCI_COMMAND, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) xdbc.xhci_start = val64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) xdbc.xhci_length = sz64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) base = early_ioremap(val64, sz64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void * __init xdbc_get_page(dma_addr_t *dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) virt = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *dma_addr = (dma_addr_t)__pa(virt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static u32 __init xdbc_find_dbgp(int xdbc_num, u32 *b, u32 *d, u32 *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 bus, dev, func, class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) for (bus = 0; bus < XDBC_PCI_MAX_BUSES; bus++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (dev = 0; dev < XDBC_PCI_MAX_DEVICES; dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (func = 0; func < XDBC_PCI_MAX_FUNCTION; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) class = read_pci_config(bus, dev, func, PCI_CLASS_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if ((class >> 8) != PCI_CLASS_SERIAL_USB_XHCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (xdbc_num-- != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *b = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *d = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *f = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int handshake(void __iomem *ptr, u32 mask, u32 done, int wait, int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Can not use readl_poll_timeout_atomic() for early boot things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) result = readl(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) result &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (result == done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) udelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wait -= delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } while (wait > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init xdbc_bios_handoff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int offset, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_LEGACY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = readl(xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (val & XHCI_HC_BIOS_OWNED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(val | XHCI_HC_OS_OWNED, xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) timeout = handshake(xdbc.xhci_base + offset, XHCI_HC_BIOS_OWNED, 0, 5000, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pr_notice("failed to hand over xHCI control from BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(val & ~XHCI_HC_BIOS_OWNED, xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Disable BIOS SMIs and clear all SMI events: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = readl(xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val &= XHCI_LEGACY_DISABLE_SMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val |= XHCI_LEGACY_SMI_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(val, xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xdbc_alloc_ring(struct xdbc_segment *seg, struct xdbc_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) seg->trbs = xdbc_get_page(&seg->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!seg->trbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ring->segment = seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void __init xdbc_free_ring(struct xdbc_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct xdbc_segment *seg = ring->segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) memblock_free(seg->dma, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ring->segment = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void xdbc_reset_ring(struct xdbc_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct xdbc_segment *seg = ring->segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct xdbc_trb *link_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) memset(seg->trbs, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ring->enqueue = seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ring->dequeue = seg->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ring->cycle_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ring != &xdbc.evt_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) link_trb = &seg->trbs[XDBC_TRBS_PER_SEGMENT - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) link_trb->field[0] = cpu_to_le32(lower_32_bits(seg->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) link_trb->field[1] = cpu_to_le32(upper_32_bits(seg->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) link_trb->field[3] = cpu_to_le32(TRB_TYPE(TRB_LINK)) | cpu_to_le32(LINK_TOGGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline void xdbc_put_utf16(u16 *s, const char *c, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) s[i] = cpu_to_le16(c[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void xdbc_mem_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct xdbc_ep_context *ep_in, *ep_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct usb_string_descriptor *s_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct xdbc_erst_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct xdbc_strings *strings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct xdbc_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 string_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 dev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) xdbc_reset_ring(&xdbc.evt_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) xdbc_reset_ring(&xdbc.in_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) xdbc_reset_ring(&xdbc.out_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) memset(xdbc.table_base, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) memset(xdbc.out_buf, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Initialize event ring segment table: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) xdbc.erst_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) xdbc.erst_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xdbc.erst_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) index += XDBC_ERST_ENTRY_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) entry = (struct xdbc_erst_entry *)xdbc.erst_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) entry->seg_addr = cpu_to_le64(xdbc.evt_seg.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) entry->seg_size = cpu_to_le32(XDBC_TRBS_PER_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) entry->__reserved_0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Initialize ERST registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(1, &xdbc.xdbc_reg->ersts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) xdbc_write64(xdbc.erst_dma, &xdbc.xdbc_reg->erstba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) xdbc_write64(xdbc.evt_seg.dma, &xdbc.xdbc_reg->erdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Debug capability contexts: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) xdbc.dbcc_size = 64 * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) xdbc.dbcc_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) xdbc.dbcc_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) index += XDBC_DBCC_ENTRY_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Popluate the strings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) xdbc.string_size = sizeof(struct xdbc_strings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) xdbc.string_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) xdbc.string_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) strings = (struct xdbc_strings *)xdbc.string_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) index += XDBC_STRING_ENTRY_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Serial string: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) s_desc = (struct usb_string_descriptor *)strings->serial;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) s_desc->bLength = (strlen(XDBC_STRING_SERIAL) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) s_desc->bDescriptorType = USB_DT_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) xdbc_put_utf16(s_desc->wData, XDBC_STRING_SERIAL, strlen(XDBC_STRING_SERIAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) string_length = s_desc->bLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) string_length <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Product string: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) s_desc = (struct usb_string_descriptor *)strings->product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) s_desc->bLength = (strlen(XDBC_STRING_PRODUCT) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) s_desc->bDescriptorType = USB_DT_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) xdbc_put_utf16(s_desc->wData, XDBC_STRING_PRODUCT, strlen(XDBC_STRING_PRODUCT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) string_length += s_desc->bLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) string_length <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Manufacture string: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) s_desc = (struct usb_string_descriptor *)strings->manufacturer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) s_desc->bLength = (strlen(XDBC_STRING_MANUFACTURER) + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s_desc->bDescriptorType = USB_DT_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) xdbc_put_utf16(s_desc->wData, XDBC_STRING_MANUFACTURER, strlen(XDBC_STRING_MANUFACTURER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) string_length += s_desc->bLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) string_length <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* String0: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) strings->string0[0] = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) strings->string0[1] = USB_DT_STRING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) strings->string0[2] = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) strings->string0[3] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) string_length += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Populate info Context: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ctx = (struct xdbc_context *)xdbc.dbcc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ctx->info.string0 = cpu_to_le64(xdbc.string_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctx->info.manufacturer = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctx->info.product = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctx->info.serial = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctx->info.length = cpu_to_le32(string_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Populate bulk out endpoint context: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) max_burst = DEBUG_MAX_BURST(readl(&xdbc.xdbc_reg->control));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ep_out = (struct xdbc_ep_context *)&ctx->out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ep_out->ep_info1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ep_out->ep_info2 = cpu_to_le32(EP_TYPE(BULK_OUT_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ep_out->deq = cpu_to_le64(xdbc.out_seg.dma | xdbc.out_ring.cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Populate bulk in endpoint context: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ep_in = (struct xdbc_ep_context *)&ctx->in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ep_in->ep_info1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ep_in->ep_info2 = cpu_to_le32(EP_TYPE(BULK_IN_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ep_in->deq = cpu_to_le64(xdbc.in_seg.dma | xdbc.in_ring.cycle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Set DbC context and info registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xdbc_write64(xdbc.dbcc_dma, &xdbc.xdbc_reg->dccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_info = cpu_to_le32((XDBC_VENDOR_ID << 16) | XDBC_PROTOCOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(dev_info, &xdbc.xdbc_reg->devinfo1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_info = cpu_to_le32((XDBC_DEVICE_REV << 16) | XDBC_PRODUCT_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(dev_info, &xdbc.xdbc_reg->devinfo2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) xdbc.in_buf = xdbc.out_buf + XDBC_MAX_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) xdbc.in_dma = xdbc.out_dma + XDBC_MAX_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void xdbc_do_reset_debug_port(u32 id, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __iomem *ops_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __iomem *portsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 val, cap_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cap_length = readl(xdbc.xhci_base) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ops_reg = xdbc.xhci_base + cap_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) id--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = id; i < (id + count); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) portsc = ops_reg + 0x400 + i * 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val = readl(portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!(val & PORT_CONNECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(val | PORT_RESET, portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void xdbc_reset_debug_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 val, port_offset, port_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) offset = xhci_find_next_ext_cap(xdbc.xhci_base, offset, XHCI_EXT_CAPS_PROTOCOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = readl(xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (XHCI_EXT_PORT_MAJOR(val) != 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val = readl(xdbc.xhci_base + offset + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) port_offset = XHCI_EXT_PORT_OFF(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) port_count = XHCI_EXT_PORT_COUNT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) xdbc_do_reset_debug_port(port_offset, port_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) xdbc_queue_trb(struct xdbc_ring *ring, u32 field1, u32 field2, u32 field3, u32 field4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct xdbc_trb *trb, *link_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) trb = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) trb->field[0] = cpu_to_le32(field1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) trb->field[1] = cpu_to_le32(field2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) trb->field[2] = cpu_to_le32(field3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) trb->field[3] = cpu_to_le32(field4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ++(ring->enqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ring->enqueue >= &ring->segment->trbs[TRBS_PER_SEGMENT - 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) link_trb = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ring->cycle_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) link_trb->field[3] |= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) link_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ring->enqueue = ring->segment->trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ring->cycle_state ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static void xdbc_ring_doorbell(int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel(DOOR_BELL_TARGET(target), &xdbc.xdbc_reg->doorbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int xdbc_start(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 ctrl, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ctrl = readl(&xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel(ctrl | CTRL_DBC_ENABLE | CTRL_PORT_ENABLE, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, CTRL_DBC_ENABLE, 100000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) xdbc_trace("failed to initialize hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Reset port to avoid bus hang: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (xdbc.vendor == PCI_VENDOR_ID_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) xdbc_reset_debug_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Wait for port connection: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = handshake(&xdbc.xdbc_reg->portsc, PORTSC_CONN_STATUS, PORTSC_CONN_STATUS, 5000000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) xdbc_trace("waiting for connection timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Wait for debug device to be configured: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_RUN, CTRL_DBC_RUN, 5000000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) xdbc_trace("waiting for device configuration timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Check port number: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) status = readl(&xdbc.xdbc_reg->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!DCST_DEBUG_PORT(status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) xdbc_trace("invalid root hub port number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) xdbc.port_number = DCST_DEBUG_PORT(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) xdbc_trace("DbC is running now, control 0x%08x port ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) readl(&xdbc.xdbc_reg->control), xdbc.port_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int xdbc_bulk_transfer(void *data, int size, bool read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct xdbc_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct xdbc_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 length, control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (size > XDBC_MAX_PACKET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) xdbc_trace("bad parameter, size %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) !(xdbc.flags & XDBC_FLAGS_CONFIGURED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) (!read && (xdbc.flags & XDBC_FLAGS_OUT_STALL)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (read && (xdbc.flags & XDBC_FLAGS_IN_STALL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) xdbc_trace("connection not ready, flags %08x\n", xdbc.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ring = (read ? &xdbc.in_ring : &xdbc.out_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) trb = ring->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cycle = ring->cycle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) length = TRB_LEN(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) control &= cpu_to_le32(~TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) control |= cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) memset(xdbc.in_buf, 0, XDBC_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) addr = xdbc.in_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) xdbc.flags |= XDBC_FLAGS_IN_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) memset(xdbc.out_buf, 0, XDBC_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) memcpy(xdbc.out_buf, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) addr = xdbc.out_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) xdbc.flags |= XDBC_FLAGS_OUT_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) xdbc_queue_trb(ring, lower_32_bits(addr), upper_32_bits(addr), length, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Add a barrier between writes of trb fields and flipping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * the cycle bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) trb->field[3] |= cpu_to_le32(cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) xdbc_ring_doorbell(read ? IN_EP_DOORBELL : OUT_EP_DOORBELL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int xdbc_handle_external_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) xdbc.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(0, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) xdbc_mem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = xdbc_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) xdbc_trace("dbc recovered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) reset_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) xdbc_trace("failed to recover from external reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int __init xdbc_early_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writel(0, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Allocate the table page: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) xdbc.table_base = xdbc_get_page(&xdbc.table_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!xdbc.table_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Get and store the transfer buffer: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) xdbc.out_buf = xdbc_get_page(&xdbc.out_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!xdbc.out_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Allocate the event ring: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = xdbc_alloc_ring(&xdbc.evt_seg, &xdbc.evt_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Allocate IN/OUT endpoint transfer rings: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = xdbc_alloc_ring(&xdbc.in_seg, &xdbc.in_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = xdbc_alloc_ring(&xdbc.out_seg, &xdbc.out_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) xdbc_mem_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = xdbc_start();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writel(0, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int __init early_xdbc_parse_parameter(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned long dbgp_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 bus, dev, func, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (strstr(s, "keep"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) early_console_keep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (xdbc.xdbc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (*s && kstrtoul(s, 0, &dbgp_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dbgp_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pr_notice("dbgp_num: %lu\n", dbgp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Locate the host controller: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = xdbc_find_dbgp(dbgp_num, &bus, &dev, &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pr_notice("failed to locate xhci host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) xdbc.vendor = read_pci_config_16(bus, dev, func, PCI_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) xdbc.device = read_pci_config_16(bus, dev, func, PCI_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) xdbc.bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) xdbc.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) xdbc.func = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Map the IO memory: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) xdbc.xhci_base = xdbc_map_pci_mmio(bus, dev, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (!xdbc.xhci_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Locate DbC registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_notice("xhci host doesn't support debug capability\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) xdbc.xhci_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) xdbc.xhci_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int __init early_xdbc_setup_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!xdbc.xdbc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) xdbc_bios_handoff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) raw_spin_lock_init(&xdbc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = xdbc_early_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pr_notice("failed to setup the connection to host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) xdbc_free_ring(&xdbc.evt_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) xdbc_free_ring(&xdbc.out_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) xdbc_free_ring(&xdbc.in_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (xdbc.table_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) memblock_free(xdbc.table_dma, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (xdbc.out_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) memblock_free(xdbc.out_dma, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) xdbc.table_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) xdbc.out_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void xdbc_handle_port_status(struct xdbc_trb *evt_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 port_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) port_reg = readl(&xdbc.xdbc_reg->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (port_reg & PORTSC_CONN_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) xdbc_trace("connect status change event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Check whether cable unplugged: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!(port_reg & PORTSC_CONN_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) xdbc.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) xdbc_trace("cable unplugged\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (port_reg & PORTSC_RESET_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) xdbc_trace("port reset change event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (port_reg & PORTSC_LINK_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) xdbc_trace("port link status change event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (port_reg & PORTSC_CONFIG_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) xdbc_trace("config error change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Write back the value to clear RW1C bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(port_reg, &xdbc.xdbc_reg->portsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static void xdbc_handle_tx_event(struct xdbc_trb *evt_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 comp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ep_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) comp_code = GET_COMP_CODE(le32_to_cpu(evt_trb->field[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ep_id = TRB_TO_EP_ID(le32_to_cpu(evt_trb->field[3]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) switch (comp_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case COMP_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case COMP_SHORT_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case COMP_TRB_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case COMP_BABBLE_DETECTED_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case COMP_USB_TRANSACTION_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case COMP_STALL_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) xdbc.flags |= XDBC_FLAGS_OUT_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) xdbc.flags |= XDBC_FLAGS_IN_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) xdbc_trace("endpoint %d stalled\n", ep_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ep_id == XDBC_EPID_IN || ep_id == XDBC_EPID_IN_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) xdbc.flags &= ~XDBC_FLAGS_IN_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else if (ep_id == XDBC_EPID_OUT || ep_id == XDBC_EPID_OUT_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) xdbc.flags &= ~XDBC_FLAGS_OUT_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) xdbc_trace("invalid endpoint id %d\n", ep_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void xdbc_handle_events(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct xdbc_trb *evt_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bool update_erdp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) cmd = read_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!(cmd & PCI_COMMAND_MASTER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) write_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Handle external reset events: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) reg = readl(&xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!(reg & CTRL_DBC_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (xdbc_handle_external_reset()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) xdbc_trace("failed to recover connection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Handle configure-exit event: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) reg = readl(&xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (reg & CTRL_DBC_RUN_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) writel(reg, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (reg & CTRL_DBC_RUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) xdbc.flags |= XDBC_FLAGS_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) xdbc.flags &= ~XDBC_FLAGS_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Handle endpoint stall event: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) reg = readl(&xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (reg & CTRL_HALT_IN_TR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) xdbc.flags |= XDBC_FLAGS_IN_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) xdbc.flags &= ~XDBC_FLAGS_IN_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!(xdbc.flags & XDBC_FLAGS_IN_PROCESS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (reg & CTRL_HALT_OUT_TR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) xdbc.flags |= XDBC_FLAGS_OUT_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) xdbc.flags &= ~XDBC_FLAGS_OUT_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Handle the events in the event ring: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) evt_trb = xdbc.evt_ring.dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) while ((le32_to_cpu(evt_trb->field[3]) & TRB_CYCLE) == xdbc.evt_ring.cycle_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Add a barrier between reading the cycle flag and any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * reads of the event's flags/data below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) switch ((le32_to_cpu(evt_trb->field[3]) & TRB_TYPE_BITMASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case TRB_TYPE(TRB_PORT_STATUS):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) xdbc_handle_port_status(evt_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case TRB_TYPE(TRB_TRANSFER):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) xdbc_handle_tx_event(evt_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ++(xdbc.evt_ring.dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (xdbc.evt_ring.dequeue == &xdbc.evt_seg.trbs[TRBS_PER_SEGMENT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) xdbc.evt_ring.dequeue = xdbc.evt_seg.trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) xdbc.evt_ring.cycle_state ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) evt_trb = xdbc.evt_ring.dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) update_erdp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Update event ring dequeue pointer: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (update_erdp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) xdbc_write64(__pa(xdbc.evt_ring.dequeue), &xdbc.xdbc_reg->erdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int xdbc_bulk_write(const char *bytes, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) int ret, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (in_nmi()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!raw_spin_trylock_irqsave(&xdbc.lock, flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) raw_spin_lock_irqsave(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) xdbc_handle_events();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Check completion of the previous request: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if ((xdbc.flags & XDBC_FLAGS_OUT_PROCESS) && (timeout < 2000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) timeout += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (xdbc.flags & XDBC_FLAGS_OUT_PROCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) xdbc_trace("previous transfer not completed yet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = xdbc_bulk_transfer((void *)bytes, size, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void early_xdbc_write(struct console *con, const char *str, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static char buf[XDBC_MAX_PACKET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int chunk, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int use_cr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (!xdbc.xdbc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) memset(buf, 0, XDBC_MAX_PACKET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) while (n > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) for (chunk = 0; chunk < XDBC_MAX_PACKET && n > 0; str++, chunk++, n--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!use_cr && *str == '\n') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) use_cr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) buf[chunk] = '\r';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) str--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (use_cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) use_cr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) buf[chunk] = *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (chunk > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = xdbc_bulk_write(buf, chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) xdbc_trace("missed message {%s}\n", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static struct console early_xdbc_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .name = "earlyxdbc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .write = early_xdbc_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) void __init early_xdbc_register_console(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (early_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) early_console = &early_xdbc_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (early_console_keep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) early_console->flags &= ~CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) early_console->flags |= CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) register_console(early_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static void xdbc_unregister_console(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (early_xdbc_console.flags & CON_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unregister_console(&early_xdbc_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int xdbc_scrub_function(void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) raw_spin_lock_irqsave(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) xdbc_handle_events();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) schedule_timeout_interruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) xdbc_unregister_console();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) writel(0, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) xdbc_trace("dbc scrub function exits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int __init xdbc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * It's time to shut down the DbC, so that the debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * port can be reused by the host controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (early_xdbc_console.index == -1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) (early_xdbc_console.flags & CON_BOOT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) xdbc_trace("hardware not used anymore\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) goto free_and_quit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) base = ioremap(xdbc.xhci_start, xdbc.xhci_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) xdbc_trace("failed to remap the io address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto free_and_quit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) raw_spin_lock_irqsave(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) xdbc.xhci_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) raw_spin_unlock_irqrestore(&xdbc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) kthread_run(xdbc_scrub_function, NULL, "%s", "xdbc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) free_and_quit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) xdbc_free_ring(&xdbc.evt_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) xdbc_free_ring(&xdbc.out_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) xdbc_free_ring(&xdbc.in_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) memblock_free(xdbc.table_dma, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) memblock_free(xdbc.out_dma, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) writel(0, &xdbc.xdbc_reg->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) early_iounmap(xdbc.xhci_base, xdbc.xhci_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) subsys_initcall(xdbc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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