^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/time64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ulpi/regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DWC3_ULPI_ADDR(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DWC3_ULPI_BASE_DELAY DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int count = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ns += DWC3_ULPI_BASE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ns += DWC3_ULPI_BASE_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (reg & DWC3_GUSB2PHYCFG_SUSPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ndelay(ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (reg & DWC3_GUSB2PHYACC_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int dwc3_ulpi_read(struct device *dev, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dwc3 *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = dwc3_ulpi_busyloop(dwc, addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return DWC3_GUSB2PHYACC_DATA(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct dwc3 *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg |= DWC3_GUSB2PHYACC_WRITE | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return dwc3_ulpi_busyloop(dwc, addr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct ulpi_ops dwc3_ulpi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .read = dwc3_ulpi_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .write = dwc3_ulpi_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int dwc3_ulpi_init(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Register the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (IS_ERR(dwc->ulpi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(dwc->dev, "failed to register ULPI interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return PTR_ERR(dwc->ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void dwc3_ulpi_exit(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (dwc->ulpi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ulpi_unregister_interface(dwc->ulpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dwc->ulpi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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