^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Felipe Balbi <balbi@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "gadget.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) & ~((d)->interval - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * dwc3_gadget_set_test_mode - enables usb2 test modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @dwc: pointer to our context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @mode: the mode to set (J, K SE0 NAK, Force Enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Caller should take care of locking. This function will return 0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * success or -EINVAL if wrong Test Selector is passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg &= ~DWC3_DCTL_TSTCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case USB_TEST_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case USB_TEST_K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case USB_TEST_SE0_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case USB_TEST_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) case USB_TEST_FORCE_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reg |= mode << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * dwc3_gadget_get_link_state - gets current state of usb link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @dwc: pointer to our context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Caller should take care of locking. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * return the link state on success (>= 0) or -ETIMEDOUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int dwc3_gadget_get_link_state(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return DWC3_DSTS_USBLNKST(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * dwc3_gadget_set_link_state - sets usb link to a particular state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @dwc: pointer to our context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @state: the state to put link into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Caller should take care of locking. This function will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * return 0 on success or -ETIMEDOUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int retries = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Wait until device controller is ready. Only applies to 1.94a and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * later RTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) while (--retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (reg & DWC3_DSTS_DCNRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (retries <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* set no action before sending new link state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* set requested state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg |= DWC3_DCTL_ULSTCHNGREQ(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The following code is racy when called from dwc3_gadget_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * and is not needed, at least on newer versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* wait for a change in DSTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) retries = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) while (--retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (DWC3_DSTS_USBLNKST(reg) == state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * dwc3_ep_inc_trb - increment a trb index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @index: Pointer to the TRB index to increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * The index should never point to the link TRB. After incrementing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * if it is point to the link TRB, wrap around to the beginning. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * link TRB is always at the last TRB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void dwc3_ep_inc_trb(u8 *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (*index)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (*index == (DWC3_TRB_NUM - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @dep: The endpoint whose enqueue pointer we're incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dwc3_ep_inc_trb(&dep->trb_enqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @dep: The endpoint whose enqueue pointer we're incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dwc3_ep_inc_trb(&dep->trb_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dwc3_request *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) list_del(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) req->remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) req->needs_extra_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (req->request.status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) req->request.status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (req->trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) usb_gadget_unmap_request_by_dev(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &req->request, req->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) req->trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) trace_dwc3_gadget_giveback(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (dep->number > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pm_runtime_put(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * dwc3_gadget_giveback - call struct usb_request's ->complete callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @dep: The endpoint to whom the request belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @req: The request we're giving back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @status: completion code for the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Must be called with controller's lock held and interrupts disabled. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * function will unmap @req and call its ->complete() callback to notify upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * layers that it has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dwc3_gadget_del_and_unmap_request(dep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) req->status = DWC3_REQUEST_STATUS_COMPLETED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) usb_gadget_giveback_request(&dep->endpoint, &req->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * dwc3_send_gadget_generic_command - issue a generic command for the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @dwc: pointer to the controller context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @cmd: the command to be issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @param: command parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Caller should take care of locking. Issue @cmd with a given @param to @dwc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * and wait for its completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 timeout = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!(reg & DWC3_DGCMD_CMDACT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) status = DWC3_DGCMD_STATUS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) trace_dwc3_gadget_generic_cmd(cmd, param, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * dwc3_send_gadget_ep_cmd - issue an endpoint command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @dep: the endpoint to which the command is going to be issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @cmd: the command to be issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @params: parameters to the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Caller should handle locking. This function will issue @cmd with given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @params to @dep and wait for its completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct dwc3_gadget_ep_cmd_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 timeout = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 saved_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int cmd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * endpoint command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * settings. Restore them after the command is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (dwc->gadget->speed <= USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (saved_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Initiate remote wakeup if the link state is in U3 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * link state is in U1/U2, no remote wakeup is needed. The Start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Transfer command will initiate the link recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) link_state = dwc3_gadget_get_link_state(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) switch (link_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case DWC3_LINK_STATE_U2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (dwc->gadget->speed >= USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case DWC3_LINK_STATE_U3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = __dwc3_gadget_wakeup(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * not relying on XferNotReady, we can make use of a special "No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Response Update Transfer" command where we should clear both CmdAct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * and CmdIOC bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * With this, we don't need to wait for command completion and can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * straight away issue further commands to the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * NOTICE: We're making an assumption that control endpoints will never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * make use of Update Transfer command. This is a safe assumption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * because we can never have more than one request at a time with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Control Endpoints. If anybody changes that assumption, this chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * needs to be updated accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) !usb_endpoint_xfer_isoc(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cmd |= DWC3_DEPCMD_CMDACT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!(cmd & DWC3_DEPCMD_CMDACT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) !(cmd & DWC3_DEPCMD_CMDIOC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto skip_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!(reg & DWC3_DEPCMD_CMDACT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cmd_status = DWC3_DEPCMD_STATUS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) switch (cmd_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case DEPEVT_TRANSFER_NO_RESOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_WARN(dwc->dev, "No resource for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case DEPEVT_TRANSFER_BUS_EXPIRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * SW issues START TRANSFER command to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * isochronous ep with future frame interval. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * future interval time has already passed when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * core receives the command, it will respond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * with an error status of 'Bus Expiry'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Instead of always returning -EINVAL, let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * give a hint to the gadget driver that this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * the case by returning -EAGAIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cmd_status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) skip_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dep->flags |= DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret != -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dwc3_gadget_ep_get_transfer_index(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (saved_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) reg |= saved_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) EXPORT_SYMBOL_GPL(dwc3_send_gadget_ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 cmd = DWC3_DEPCMD_CLEARSTALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * As of core revision 2.60a the recommended programming model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * is to set the ClearPendIN bit when issuing a Clear Stall EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * command for IN endpoints. This is to prevent an issue where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * some (non-compliant) hosts may not send ACK TPs for pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * IN transfers due to a mishandled error condition. Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * STAR 9000614252.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (dep->direction &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (dwc->gadget->speed >= USB_SPEED_SUPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cmd |= DWC3_DEPCMD_CLEARPENDIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct dwc3_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 offset = (char *) trb - (char *) dep->trb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return dep->trb_pool_dma + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dep->trb_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &dep->trb_pool_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!dep->trb_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void dwc3_free_trb_pool(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dep->trb_pool, dep->trb_pool_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dep->trb_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dep->trb_pool_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) memset(¶ms, 0x00, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * dwc3_gadget_start_config - configure ep resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @dep: endpoint that is being enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * completion, it will set Transfer Resource for all available endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * The assignment of transfer resources cannot perfectly follow the data book
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * due to the fact that the controller driver does not have all knowledge of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * configuration in advance. It is given this information piecemeal by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * composite gadget framework after every SET_CONFIGURATION and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * SET_INTERFACE. Trying to follow the databook programming model in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * scenario can cause errors. For two reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * incorrect in the scenario of multiple interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * endpoint on alt setting (8.1.6).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * The following simplified method is used instead:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * All hardware endpoints can be assigned a transfer resource and this setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * will stay persistent until either a core reset or hibernation. So whenever we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * guaranteed that there are as many transfer resources as endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * This function is called for each endpoint when it is being enabled but is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * triggered only when called for EP0-out, which always happens first, and which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * should only happen in one of the above conditions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int dwc3_gadget_start_config(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct dwc3 *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (dep->number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) memset(¶ms, 0x00, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cmd = DWC3_DEPCMD_DEPSTARTCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct dwc3_ep *dep = dwc->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = dwc3_gadget_set_xfer_resource(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct usb_ss_ep_comp_descriptor *comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct usb_endpoint_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) comp_desc = dep->endpoint.comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) desc = dep->endpoint.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) memset(¶ms, 0x00, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Burst size is only needed in SuperSpeed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (dwc->gadget->speed >= USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 burst = dep->endpoint.maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) params.param0 |= action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (action == DWC3_DEPCFG_ACTION_RESTORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) params.param2 |= dep->saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) | DWC3_DEPCFG_XFER_COMPLETE_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) | DWC3_DEPCFG_STREAM_EVENT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dep->stream_capable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * We are doing 1:1 mapping for endpoints, meaning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Physical Endpoints 2 maps to Logical Endpoint 2 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * so on. We consider the direction bit as part of the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * endpoint number. So USB endpoint 0x81 is 0x03.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * We must use the lower 16 TX FIFOs even though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * HW might have more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (dep->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (desc->bInterval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u8 bInterval_m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * NOTE: The programming guide incorrectly stated bInterval_m1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * must be set to 0 when operating in fullspeed. Internally the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * controller does not have this limitation. See DWC_usb3x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * programming guide section 3.2.2.1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dwc->gadget->speed == USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dep->interval = desc->bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dep->interval = 1 << (desc->bInterval - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * dwc3_gadget_get_tx_fifos_size - Get the txfifos total size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @dwc: pointer to the DWC3 context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * 3-RAM configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * RAM0 depth = Descriptor Cache depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * RAM1 depth = TxFIFOs depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * RAM2 depth = RxFIFOs depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * 2-RAM configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * RAM0 depth = Descriptor Cache depth + RxFIFOs depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * RAM1 depth = TxFIFOs depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * 1-RAM configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * RAM0 depth = Descriptor Cache depth + RxFIFOs depth + TxFIFOs depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int dwc3_gadget_get_tx_fifos_size(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int txfifo_depth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int ram0_depth, rxfifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Get the depth of the TxFIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (DWC3_NUM_RAMS(dwc->hwparams.hwparams1) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* For 2 or 3-RAM, RAM1 contains TxFIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) txfifo_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* For 1-RAM, RAM0 contains Descriptor Cache, RxFIFOs, and TxFIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ram0_depth = DWC3_GHWPARAMS6_RAM0_DEPTH(dwc->hwparams.hwparams6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* All OUT endpoints share a single RxFIFO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rxfifo_size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) txfifo_depth = ram0_depth - DWC3_GRXFIFOSIZ_RXFDEP(rxfifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) txfifo_depth = ram0_depth - DWC31_GRXFIFOSIZ_RXFDEP(rxfifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* The value of GRxFIFOSIZ0[31:16] is the depth of Descriptor Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) txfifo_depth -= DWC3_GRXFIFOSIZ_RXFSTADDR(rxfifo_size) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return txfifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @dwc: pointer to the DWC3 context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @nfifos: number of fifos to calculate for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Calculates the size value based on the equation below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * DWC3 revision 280A and prior:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * fifo_size = mult * (max_packet / mdwidth) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * DWC3 revision 290A and onwards:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * The max packet size is set to 1024, as the txfifo requirements mainly apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * to super speed USB use cases. However, it is safe to overestimate the fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * allocations for other scenarios, i.e. high speed USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int max_packet = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mdwidth = dwc3_mdwidth(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* MDWIDTH is represented in bits, we need it in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mdwidth >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (DWC3_VER_IS_PRIOR(DWC3, 290A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) fifo_size = mult * (max_packet / mdwidth) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * @dwc: pointer to the DWC3 context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Iterates through all the endpoint registers and clears the previous txfifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (!dwc->do_fifo_resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Read ep0IN related TXFIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dep = dwc->eps[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dwc->last_fifo_depth = fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Clear existing TXFIFO for all IN eps except ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) num += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dep = dwc->eps[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Don't change TXFRAMNUM on usb31 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) size = DWC3_IP_IS(DWC3) ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) DWC31_GTXFIFOSIZ_TXFRAMNUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dwc->num_ep_resized = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * __dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for Rockchip platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * @dep: pointer to dwc3_ep structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * According to the different USB transfer type and Speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * this function will a best effort FIFO allocation in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * to improve FIFO usage and throughput, while still allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * us to enable as many endpoints as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int __dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) u32 fifo_0_start, last_fifo_depth, ram1_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) u32 fifo_size, maxpacket, mdwidth, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Set enough tx fifos for Isochronous endpoints to get better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * performance and more compliance with bus latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) maxpacket = dep->endpoint.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (gadget_is_superspeed(dwc->gadget))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mult = dep->endpoint.mult * dep->endpoint.maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mult = dep->endpoint.mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mult = mult > 0 ? mult * 2 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (mult > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mult = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } else if (usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Set enough tx fifos for Bulk endpoints to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * better transmission performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mult = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (gadget_is_superspeed(dwc->gadget)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (dep->endpoint.maxburst > mult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mult = dep->endpoint.maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (mult > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mult = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) maxpacket = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) maxpacket = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } else if (usb_endpoint_xfer_int(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * REVIST: we assume that the maxpacket of interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * endpoint is 64 Bytes for MTP and the other functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) maxpacket = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mdwidth = dwc3_mdwidth(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mdwidth >>= 3; /* bits convert to bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ram1_depth = dwc3_gadget_get_tx_fifos_size(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) last_fifo_depth = dwc->last_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Calculate the fifo size for this EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) tmp = mult * (maxpacket + mdwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) tmp += mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) fifo_size = DIV_ROUND_UP(tmp, mdwidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Check if TXFIFOs start at non-zero addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) fifo_size |= (fifo_0_start + (last_fifo_depth << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Check fifo size allocation doesn't exceed available RAM size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (last_fifo_depth >= ram1_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(dwc->dev, "Fifosize(0x%x) > RAM size(0x%x) %s depth(0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) last_fifo_depth, ram1_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dep->endpoint.name, fifo_size & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dep->flags |= DWC3_EP_TXFIFO_RESIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dwc->last_fifo_depth = last_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dwc->num_ep_resized++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @dwc: pointer to our context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * This function will a best effort FIFO allocation in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * to improve FIFO usage and throughput, while still allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * us to enable as many endpoints as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Keep in mind that this operation will be highly dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * on the configured size for RAM1 - which contains TxFifo -,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * the amount of endpoints enabled on coreConsultant tool, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * the width of the Master Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * In general, FIFO depths are represented with the following equation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * In conjunction with dwc3_gadget_check_config(), this resizing logic will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * ensure that all endpoints will have enough internal memory for one max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * packet per endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int fifo_0_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int ram1_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int min_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int num_in_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int num_fifos = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!dwc->do_fifo_resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* resize IN endpoints except ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* bail if already resized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (IS_REACHABLE(CONFIG_ARCH_ROCKCHIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return __dwc3_gadget_resize_tx_fifos(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ram1_depth = dwc3_gadget_get_tx_fifos_size(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if ((dep->endpoint.maxburst > 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) usb_endpoint_xfer_isoc(dep->endpoint.desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) num_fifos = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (dep->endpoint.maxburst > 6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) num_fifos = dwc->tx_fifo_resize_max_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* FIFO size for a single buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Calculate the number of remaining EPs w/o any FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) num_in_ep = dwc->max_cfg_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) num_in_ep -= dwc->num_ep_resized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Reserve at least one FIFO for the number of IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) min_depth = num_in_ep * (fifo + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) remaining = max_t(int, 0, remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * We've already reserved 1 FIFO per EP, so check what we can fit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * addition to it. If there is not enough remaining space, allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * all the remaining space to the EP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) fifo_size = (num_fifos - 1) * fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (remaining < fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) fifo_size = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fifo_size += fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Last increment according to the TX FIFO size equation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) fifo_size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Check if TXFIFOs start at non-zero addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Check fifo size allocation doesn't exceed available RAM size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (dwc->last_fifo_depth >= ram1_depth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dwc->last_fifo_depth, ram1_depth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dep->endpoint.name, fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dwc->last_fifo_depth -= fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dep->flags |= DWC3_EP_TXFIFO_RESIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dwc->num_ep_resized++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * __dwc3_gadget_ep_enable - initializes a hw endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * @dep: endpoint to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * @action: one of INIT, MODIFY or RESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * Caller should take care of locking. Execute all necessary commands to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * initialize a HW endpoint so it can be used by a gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!(dep->flags & DWC3_EP_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = dwc3_gadget_resize_tx_fifos(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = dwc3_gadget_start_config(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = dwc3_gadget_set_ep_config(dep, action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!(dep->flags & DWC3_EP_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct dwc3_trb *trb_st_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct dwc3_trb *trb_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dep->type = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dep->flags |= DWC3_EP_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) reg |= DWC3_DALEPENA_EP(dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dep->trb_dequeue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dep->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (usb_endpoint_xfer_control(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Initialize the TRB ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) memset(dep->trb_pool, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Link TRB. The HWO bit is never reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) trb_st_hw = &dep->trb_pool[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Issue StartTransfer here with no-op TRB so we can always rely on No
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * Response Update Transfer command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (usb_endpoint_xfer_bulk(desc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) usb_endpoint_xfer_int(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dma_addr_t trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) trb = &dep->trb_pool[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) trb_dma = dwc3_trb_dma_offset(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) params.param0 = upper_32_bits(trb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) params.param1 = lower_32_bits(trb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cmd = DWC3_DEPCMD_STARTTRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (dep->stream_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * For streams, at start, there maybe a race where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * host primes the endpoint before the function driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * queues a request to initiate a stream. In that case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * the controller will not see the prime to generate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * ERDY and start stream. To workaround this, issue a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * no-op TRB as normal, but end it immediately. As a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * result, when the function driver queues the request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * the next START_TRANSFER command will cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * controller to generate an ERDY to initiate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * All stream eps will reinitiate stream on NoStream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * rejection until we can determine that the host can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * prime after the first transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * However, if the controller is capable of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * TXF_FLUSH_BYPASS, then IN direction endpoints will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * automatically restart the stream without the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * initiation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!dep->direction ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) !(dwc->hwparams.hwparams9 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) trace_dwc3_gadget_ep_enable(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dwc3_stop_active_transfer(dep, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* If endxfer is delayed, avoid unmapping requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (dep->flags & DWC3_EP_DELAY_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* - giveback all requests to gadget driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) while (!list_empty(&dep->started_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) req = next_request(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dwc3_gadget_giveback(dep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) while (!list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) req = next_request(&dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dwc3_gadget_giveback(dep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) while (!list_empty(&dep->cancelled_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) req = next_request(&dep->cancelled_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dwc3_gadget_giveback(dep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * __dwc3_gadget_ep_disable - disables a hw endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * @dep: the endpoint to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * This function undoes what __dwc3_gadget_ep_enable did and also removes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * requests which are currently being processed by the hardware and those which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * are not yet scheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * Caller should take care of locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) trace_dwc3_gadget_ep_disable(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* make sure HW endpoint isn't stalled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (dep->flags & DWC3_EP_STALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) __dwc3_gadget_ep_set_halt(dep, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) reg &= ~DWC3_DALEPENA_EP(dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Clear out the ep descriptors for non-ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (dep->number > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dep->endpoint.comp_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dep->endpoint.desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dwc3_remove_requests(dwc, dep, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dep->stream_capable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dep->type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mask = DWC3_EP_TXFIFO_RESIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * set. Do not clear DEP flags, so that the end transfer command will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * be reattempted during the next SETUP stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (dep->flags & DWC3_EP_DELAY_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dep->flags &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int dwc3_gadget_ep_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct dwc3 *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) pr_debug("dwc3: invalid parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!desc->wMaxPacketSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pr_debug("dwc3: missing wMaxPacketSize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) "%s is already enabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dep->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int dwc3_gadget_ep_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct dwc3 *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) pr_debug("dwc3: invalid parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "%s is already disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dep->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) ret = __dwc3_gadget_ep_disable(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) req = kzalloc(sizeof(*req), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) req->direction = dep->direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) req->epnum = dep->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) req->dep = dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) req->status = DWC3_REQUEST_STATUS_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) trace_dwc3_alloc_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return &req->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct dwc3_request *req = to_dwc3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) trace_dwc3_free_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) kfree(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * dwc3_ep_prev_trb - returns the previous TRB in the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * @dep: The endpoint with the TRB ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * @index: The index of the current TRB in the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * Returns the TRB prior to the one pointed to by the index. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * index is 0, we will wrap backwards, skip the link TRB, and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * the one just before that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u8 tmp = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) tmp = DWC3_TRB_NUM - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return &dep->trb_pool[tmp - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) u8 trbs_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * If the enqueue & dequeue are equal then the TRB ring is either full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * pending to be processed by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (dep->trb_enqueue == dep->trb_dequeue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * If there is any request remained in the started_list at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * this point, that means there is no TRB available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!list_empty(&dep->started_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return DWC3_TRB_NUM - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) trbs_left = dep->trb_dequeue - dep->trb_enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) trbs_left &= (DWC3_TRB_NUM - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (dep->trb_dequeue < dep->trb_enqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) trbs_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return trbs_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dma_addr_t dma, unsigned int length, unsigned int chain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) unsigned int node, unsigned int stream_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) unsigned int short_not_ok, unsigned int no_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) unsigned int is_last, bool must_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct usb_gadget *gadget = dwc->gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) enum usb_device_speed speed = gadget->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) trb->size = DWC3_TRB_SIZE_LENGTH(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) trb->bpl = lower_32_bits(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) trb->bph = upper_32_bits(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) switch (usb_endpoint_type(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * USB Specification 2.0 Section 5.9.2 states that: "If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * there is only a single transaction in the microframe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * only a DATA0 data packet PID is used. If there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * two transactions per microframe, DATA1 is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * the first transaction data packet and DATA0 is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * for the second transaction data packet. If there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * three transactions per microframe, DATA2 is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * the first transaction data packet, DATA1 is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * the second, and DATA0 is used for the third."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * IOW, we should satisfy the following cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * 1) length <= maxpacket
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * - DATA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * 2) maxpacket < length <= (2 * maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * - DATA1, DATA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * 3) (2 * maxpacket) < length <= (3 * maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * - DATA2, DATA1, DATA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct usb_ep *ep = &dep->endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) unsigned int mult = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) unsigned int maxp = usb_endpoint_maxp(ep->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (length <= (2 * maxp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mult--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (length <= maxp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mult--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) trb->size |= DWC3_TRB_SIZE_PCM1(mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* always enable Interrupt on Missed ISOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) trb->ctrl = DWC3_TRBCTL_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * This is only possible with faulty memory because we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * checked it already :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) usb_endpoint_type(dep->endpoint.desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * Enable Continue on Short Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * when endpoint is not a stream capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (usb_endpoint_dir_out(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (!dep->stream_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) trb->ctrl |= DWC3_TRB_CTRL_CSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (short_not_ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if ((!no_interrupt && !chain) || must_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) trb->ctrl |= DWC3_TRB_CTRL_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) trb->ctrl |= DWC3_TRB_CTRL_CHN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) else if (dep->stream_capable && is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) trb->ctrl |= DWC3_TRB_CTRL_LST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * As per data book 4.2.3.2TRB Control Bit Rules section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * The controller autonomously checks the HWO field of a TRB to determine if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * is valid before setting the HWO field to '1'. In most systems, this means that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * software must update the fourth DWORD of a TRB last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * However there is a possibility of CPU re-ordering here which can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * controller to observe the HWO bit set prematurely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * Add a write memory barrier to prevent CPU re-ordering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) trb->ctrl |= DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dwc3_ep_inc_enq(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) trace_dwc3_prepare_trb(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * dwc3_prepare_one_trb - setup one TRB from one request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * @dep: endpoint for which this request is prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * @req: dwc3_request pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * @trb_length: buffer size of the TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * @chain: should this TRB be chained to the next?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * @node: only for isochronous endpoints. First TRB needs different type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * @use_bounce_buffer: set to use bounce buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * @must_interrupt: set to interrupt on TRB completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct dwc3_request *req, unsigned int trb_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) unsigned int chain, unsigned int node, bool use_bounce_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) bool must_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) unsigned int stream_id = req->request.stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) unsigned int short_not_ok = req->request.short_not_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned int no_interrupt = req->request.no_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) unsigned int is_last = req->request.is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (use_bounce_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dma = dep->dwc->bounce_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) else if (req->request.num_sgs > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dma = sg_dma_address(req->start_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dma = req->request.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) trb = &dep->trb_pool[dep->trb_enqueue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (!req->trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dwc3_gadget_move_started_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) req->trb = trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) req->trb_dma = dwc3_trb_dma_offset(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) req->num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) stream_id, short_not_ok, no_interrupt, is_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) must_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) unsigned int rem = req->request.length % maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if ((req->request.length && req->request.zero && !rem &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) (!req->direction && rem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * @dep: The endpoint that the request belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * @req: The request to prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * @entry_length: The last SG entry size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * @node: Indicates whether this is not the first entry (for isoc only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * Return the number of TRBs prepared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct dwc3_request *req, unsigned int entry_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) unsigned int node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unsigned int rem = req->request.length % maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) unsigned int num_trbs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (dwc3_needs_extra_trb(dep, req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) num_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (dwc3_calc_trbs_left(dep) < num_trbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) req->needs_extra_trb = num_trbs > 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Prepare a normal TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (req->direction || req->request.length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dwc3_prepare_one_trb(dep, req, entry_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) req->needs_extra_trb, node, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if ((!req->direction && !req->request.length) || req->needs_extra_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dwc3_prepare_one_trb(dep, req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) req->direction ? 0 : maxp - rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) false, 1, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct scatterlist *sg = req->start_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct scatterlist *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) unsigned int length = req->request.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) unsigned int remaining = req->request.num_mapped_sgs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) - req->num_queued_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) unsigned int num_trbs = req->num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * If we resume preparing the request, then get the remaining length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * the request and resume where we left off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) length -= sg_dma_len(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) for_each_sg(sg, s, remaining, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) unsigned int trb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) bool must_interrupt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) bool last_sg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) trb_length = min_t(unsigned int, length, sg_dma_len(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) length -= trb_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * IOMMU driver is coalescing the list of sgs which shares a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * page boundary into one and giving it to USB driver. With
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * this the number of sgs mapped is not equal to the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * sgs passed. So mark the chain bit to false if it isthe last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * mapped sg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if ((i == remaining - 1) || !length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) last_sg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (!num_trbs_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (last_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) * Look ahead to check if we have enough TRBs for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * next SG entry. If not, set interrupt on this TRB to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * resume preparing the next SG entry when more TRBs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * free.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (num_trbs_left == 1 || (needs_extra_trb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) num_trbs_left <= 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) sg_dma_len(sg_next(s)) >= length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) must_interrupt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) must_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * There can be a situation where all sgs in sglist are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * queued because of insufficient trb number. To handle this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * case, update start_sg to next sg to be queued, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * we have free trbs we can continue queuing from where we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * previously stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!last_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) req->start_sg = sg_next(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) req->num_queued_sgs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) req->num_pending_sgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * The number of pending SG entries may not correspond to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * number of mapped SG entries. If all the data are queued, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * don't include unused SG entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) req->num_pending_sgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (must_interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return req->num_trbs - num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * dwc3_prepare_trbs - setup TRBs from requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) * @dep: endpoint for which requests are being prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * The function goes through the requests list and sets up TRBs for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * transfers. The function returns once there are no more TRBs available or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * it runs out of requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * Returns the number of TRBs prepared or negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static int dwc3_prepare_trbs(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct dwc3_request *req, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * We can get in a situation where there's a request in the started list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * but there weren't enough TRBs to fully kick it in the first time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * around, so it has been waiting for more TRBs to be freed up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * In that case, we should check if we have a request with pending_sgs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * in the started list and prepare TRBs for that request first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * otherwise we will prepare TRBs completely out of order and that will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * break things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) list_for_each_entry(req, &dep->started_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (req->num_pending_sgs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ret = dwc3_prepare_trbs_sg(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (!ret || req->num_pending_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (!dwc3_calc_trbs_left(dep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * Don't prepare beyond a transfer. In DWC_usb32, its transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * burst capability may try to read and use TRBs beyond the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * active transfer instead of stopping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (dep->stream_capable && req->request.is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) list_for_each_entry_safe(req, n, &dep->pending_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) dep->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) req->sg = req->request.sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) req->start_sg = req->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) req->num_queued_sgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) req->num_pending_sgs = req->request.num_mapped_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (req->num_pending_sgs > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = dwc3_prepare_trbs_sg(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (req->num_pending_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ret = dwc3_prepare_trbs_linear(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (!ret || !dwc3_calc_trbs_left(dep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * Don't prepare beyond a transfer. In DWC_usb32, its transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * burst capability may try to read and use TRBs beyond the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * active transfer instead of stopping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (dep->stream_capable && req->request.is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) int starting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * This happens when we need to stop and restart a transfer such as in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * the case of reinitiating a stream or retrying an isoc transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ret = dwc3_prepare_trbs(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * If there's no new TRB prepared and we don't need to restart a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * transfer, there's no need to update the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (!ret && !starting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) req = next_request(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (!req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dep->flags |= DWC3_EP_PENDING_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (starting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) params.param0 = upper_32_bits(req->trb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) params.param1 = lower_32_bits(req->trb_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) cmd = DWC3_DEPCMD_STARTTRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (dep->stream_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) cmd = DWC3_DEPCMD_UPDATETRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) DWC3_DEPCMD_PARAM(dep->resource_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct dwc3_request *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (ret == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) list_for_each_entry_safe(req, tmp, &dep->started_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* If ep isn't started, then there's no end transfer pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dwc3_gadget_ep_cleanup_cancelled_requests(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (dep->stream_capable && req->request.is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return DWC3_DSTS_SOFFN(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * __dwc3_stop_active_transfer - stop the current active transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) * @dep: isoc endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) * @force: set forcerm bit in the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * @interrupt: command complete interrupt after End Transfer command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * When setting force, the ForceRM bit will be set. In that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * the controller won't update the TRB progress on command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * completion. It also won't clear the HWO bit in the TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * The command will also not complete immediately in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) cmd = DWC3_DEPCMD_ENDTRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * If the End Transfer command was timed out while the device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * not in SETUP phase, it's possible that an incoming Setup packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * may prevent the command's completion. Let's retry when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * ep0state returns to EP0_SETUP_PHASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) dep->flags |= DWC3_EP_DELAY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) WARN_ON_ONCE(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) dep->resource_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (!interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * @dep: isoc endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * This function tests for the correct combination of BIT[15:14] from the 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * microframe number reported by the XferNotReady event for the future frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * number to start the isoc transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * XferNotReady event are invalid. The driver uses this number to schedule the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * isochronous transfer and passes it to the START TRANSFER command. Because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * this number is invalid, the command may fail. If BIT[15:14] matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * internal 16-bit microframe, the START TRANSFER command will pass and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * transfer will start at the scheduled time, if it is off by 1, the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * will still pass, but the transfer will start 2 seconds in the future. For all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * other conditions, the START TRANSFER command will fail with bus-expiry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) * In order to workaround this issue, we can test for the correct combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * BIT[15:14] by sending START TRANSFER commands with different values of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * As the result, within the 4 possible combinations for BIT[15:14], there will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * command status will result in a 2-second delay start. The smaller BIT[15:14]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * value is the correct combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * Since there are only 4 outcomes and the results are ordered, we can simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * deduce the smaller successful combination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * of BIT[15:14]. The correct combination is as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) * if test0 fails and test1 passes, BIT[15:14] is 'b01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * if test0 fails and test1 fails, BIT[15:14] is 'b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * if test0 passes and test1 fails, BIT[15:14] is 'b11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * if test0 passes and test1 passes, BIT[15:14] is 'b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) int cmd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) bool test0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) bool test1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) while (dep->combo_num < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) u32 test_frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * Check if we can start isoc transfer on the next interval or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * 4 uframes in the future with BIT[15:14] as dep->combo_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) test_frame_number |= dep->combo_num << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) test_frame_number += max_t(u32, 4, dep->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) params.param0 = upper_32_bits(dep->dwc->bounce_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) params.param1 = lower_32_bits(dep->dwc->bounce_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) cmd = DWC3_DEPCMD_STARTTRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* Redo if some other failure beside bus-expiry is received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (cmd_status && cmd_status != -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dep->start_cmd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) dep->combo_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* Store the first test status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (dep->combo_num == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) dep->start_cmd_status = cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dep->combo_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * End the transfer if the START_TRANSFER command is successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * to wait for the next XferNotReady to test the command again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (cmd_status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* test0 and test1 are both completed at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) test0 = (dep->start_cmd_status == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) test1 = (cmd_status == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (!test0 && test1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) dep->combo_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) else if (!test0 && !test1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dep->combo_num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) else if (test0 && !test1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) dep->combo_num = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) else if (test0 && test1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) dep->combo_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dep->frame_number &= DWC3_FRNUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dep->frame_number |= dep->combo_num << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dep->frame_number += max_t(u32, 4, dep->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* Reinitialize test variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) dep->start_cmd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dep->combo_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return __dwc3_gadget_kick_transfer(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (list_empty(&dep->pending_list) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) list_empty(&dep->started_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dep->flags |= DWC3_EP_PENDING_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!dwc->dis_start_transfer_quirk &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return dwc3_gadget_start_isoc_quirk(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (desc->bInterval <= 14 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dwc->gadget->speed >= USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) u32 frame = __dwc3_gadget_get_frame(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) bool rollover = frame <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) (dep->frame_number & DWC3_FRNUMBER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * frame_number is set from XferNotReady and may be already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * out of date. DSTS only provides the lower 14 bit of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * current frame number. So add the upper two bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * frame_number and handle a possible rollover.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * This will provide the correct frame_number unless more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * rollover has happened since XferNotReady.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (rollover)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) dep->frame_number += BIT(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) int future_interval = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* Give the controller at least 500us to schedule transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (desc->bInterval < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) future_interval += 3 - desc->bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ret = __dwc3_gadget_kick_transfer(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (ret != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * After a number of unsuccessful start attempts due to bus-expiry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * status, issue END_TRANSFER command and retry on the next XferNotReady
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) if (ret == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ret = __dwc3_stop_active_transfer(dep, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) &req->request, req->dep->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) "%s: request %pK already in flight\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) dep->name, &req->request))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) pm_runtime_get(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) req->request.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) req->request.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) trace_dwc3_ep_queue(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) list_add_tail(&req->list, &dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) req->status = DWC3_REQUEST_STATUS_QUEUED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * Start the transfer only after the END_TRANSFER is completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * and endpoint STALL is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) (dep->flags & DWC3_EP_WEDGE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) (dep->flags & DWC3_EP_DELAY_STOP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) (dep->flags & DWC3_EP_STALL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) dep->flags |= DWC3_EP_DELAY_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * wait for a XferNotReady event so we will know what's the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * (micro-)frame number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * Without this trick, we are very, very likely gonna get Bus Expiry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * errors which will force us issue EndTransfer command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) !(dep->flags & DWC3_EP_TRANSFER_STARTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return __dwc3_gadget_start_isoc(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) __dwc3_gadget_kick_transfer(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct dwc3_request *req = to_dwc3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ret = __dwc3_gadget_ep_queue(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* If req->trb is not set, then the request has not started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (!req->trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * If request was already started, this means we had to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * stop the transfer. With that we also need to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) * all TRBs used by the request, however TRBs can only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * be modified after completion of END_TRANSFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * command. So what we do here is that we wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * END_TRANSFER completion and only after that, we jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * over TRBs by clearing HWO and incrementing dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) for (i = 0; i < req->num_trbs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) trb = &dep->trb_pool[dep->trb_dequeue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dwc3_ep_inc_deq(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) req->num_trbs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) while (!list_empty(&dep->cancelled_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) req = next_request(&dep->cancelled_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) dwc3_gadget_ep_skip_trbs(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) switch (req->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) case DWC3_REQUEST_STATUS_DISCONNECTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) case DWC3_REQUEST_STATUS_DEQUEUED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) dwc3_gadget_giveback(dep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) case DWC3_REQUEST_STATUS_STALLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) dwc3_gadget_giveback(dep, req, -EPIPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) dwc3_gadget_giveback(dep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) * The endpoint is disabled, let the dwc3_remove_requests()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * handle the cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (!dep->endpoint.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) struct dwc3_request *req = to_dwc3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct dwc3_request *r = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) trace_dwc3_ep_dequeue(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) list_for_each_entry(r, &dep->cancelled_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (r == req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) list_for_each_entry(r, &dep->pending_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (r == req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) dwc3_gadget_ep_skip_trbs(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) dwc3_gadget_giveback(dep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) list_for_each_entry(r, &dep->started_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (r == req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) /* wait until it is processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) * Remove any started request if the transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * cancelled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dwc3_gadget_move_cancelled_request(r, DWC3_REQUEST_STATUS_DEQUEUED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) dwc3_gadget_ep_skip_trbs(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) dwc3_gadget_giveback(dep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) dev_err(dwc->dev, "request %pK was not queued to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) request, ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) memset(¶ms, 0x00, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) unsigned int transfer_in_flight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) unsigned int started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (dep->number > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) trb = &dwc->ep0_trb[dep->trb_enqueue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) started = !list_empty(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (!protocol && ((dep->direction && transfer_in_flight) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) (!dep->direction && started))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) dev_err(dwc->dev, "failed to set STALL on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) dep->flags |= DWC3_EP_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * Don't issue CLEAR_STALL command to control endpoints. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * controller automatically clears the STALL when it receives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * the SETUP token.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (dep->number <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) if (!list_empty(&dep->started_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) dep->flags |= DWC3_EP_DELAY_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) (dep->flags & DWC3_EP_DELAY_STOP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) vdwc->clear_stall_protocol = dep->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ret = dwc3_send_clear_stall_ep_cmd(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) dev_err(dwc->dev, "failed to clear STALL on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if ((dep->flags & DWC3_EP_DELAY_START) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) !usb_endpoint_xfer_isoc(dep->endpoint.desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) __dwc3_gadget_kick_transfer(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) dep->flags &= ~DWC3_EP_DELAY_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ret = __dwc3_gadget_ep_set_halt(dep, value, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) dep->flags |= DWC3_EP_WEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) if (dep->number == 0 || dep->number == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ret = __dwc3_gadget_ep0_set_halt(ep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .bLength = USB_DT_ENDPOINT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .bDescriptorType = USB_DT_ENDPOINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .enable = dwc3_gadget_ep0_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .disable = dwc3_gadget_ep0_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .alloc_request = dwc3_gadget_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .free_request = dwc3_gadget_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .queue = dwc3_gadget_ep0_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .dequeue = dwc3_gadget_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .set_halt = dwc3_gadget_ep0_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .set_wedge = dwc3_gadget_ep_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static const struct usb_ep_ops dwc3_gadget_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .enable = dwc3_gadget_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .disable = dwc3_gadget_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .alloc_request = dwc3_gadget_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .free_request = dwc3_gadget_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .queue = dwc3_gadget_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .dequeue = dwc3_gadget_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .set_halt = dwc3_gadget_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .set_wedge = dwc3_gadget_ep_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static int dwc3_gadget_get_frame(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) return __dwc3_gadget_get_frame(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) u8 link_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) * According to the Databook Remote wakeup request should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) * be issued only when the device is in early suspend state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) * We can check that via USB Link State bits in DSTS register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) link_state = DWC3_DSTS_USBLNKST(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) switch (link_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) case DWC3_LINK_STATE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) case DWC3_LINK_STATE_U1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) case DWC3_LINK_STATE_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) dev_err(dwc->dev, "failed to put link in Recovery\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /* Recent versions do this automatically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /* write zeroes to Link Change Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /* poll until Link State changes to ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) retries = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) /* in HS, means ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) dev_err(dwc->dev, "failed to send remote wakeup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static int dwc3_gadget_wakeup(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ret = __dwc3_gadget_wakeup(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) int is_selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) g->is_selfpowered = !!is_selfpowered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static void dwc3_stop_active_transfers(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) u32 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) for (epnum = 2; epnum < dwc->num_eps; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) dep = dwc->eps[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) if (ssp_rate == USB_SSP_GEN_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ssp_rate = dwc->max_ssp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) reg &= ~DWC3_DCFG_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) reg &= ~DWC3_DCFG_NUMLANES(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (ssp_rate == USB_SSP_GEN_1x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) reg |= DWC3_DCFG_SUPERSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) reg |= DWC3_DCFG_SUPERSPEED_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (ssp_rate != USB_SSP_GEN_2x1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) dwc->max_ssp_rate != USB_SSP_GEN_2x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) reg |= DWC3_DCFG_NUMLANES(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) enum usb_device_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) speed = dwc->gadget_max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) speed = dwc->maximum_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (speed == USB_SPEED_SUPER_PLUS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) DWC3_IP_IS(DWC32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) __dwc3_gadget_set_ssp_rate(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) reg &= ~(DWC3_DCFG_SPEED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) * WORKAROUND: DWC3 revision < 2.20a have an issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) * which would cause metastability state on Run/Stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) * bit if we try to force the IP to USB2-only mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) * Because of that, we cannot configure the IP to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) * speed other than the SuperSpeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) * STAR#9000525659: Clock Domain Crossing on DCTL in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) * USB 2.0 Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) !dwc->dis_metastability_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) reg |= DWC3_DCFG_SUPERSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) reg |= DWC3_DCFG_LOWSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) reg |= DWC3_DCFG_FULLSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) reg |= DWC3_DCFG_HIGHSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) reg |= DWC3_DCFG_SUPERSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) case USB_SPEED_SUPER_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) reg |= DWC3_DCFG_SUPERSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) reg |= DWC3_DCFG_SUPERSPEED_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) dev_err(dwc->dev, "invalid speed (%d)\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) reg |= DWC3_DCFG_SUPERSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) reg |= DWC3_DCFG_SUPERSPEED_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (DWC3_IP_IS(DWC32) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) speed > USB_SPEED_UNKNOWN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) speed < USB_SPEED_SUPER_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) reg &= ~DWC3_DCFG_NUMLANES(~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) u32 timeout = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) if (pm_runtime_suspended(dwc->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) reg &= ~DWC3_DCTL_TRGTULST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) reg |= DWC3_DCTL_TRGTULST_RX_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) reg &= ~DWC3_DCTL_KEEP_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) reg |= DWC3_DCTL_RUN_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) if (dwc->has_hibernation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) reg |= DWC3_DCTL_KEEP_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) __dwc3_gadget_set_speed(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) dwc->pullups_connected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) reg &= ~DWC3_DCTL_RUN_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) if (dwc->has_hibernation && !suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) reg &= ~DWC3_DCTL_KEEP_CONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) dwc->pullups_connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) reg &= DWC3_DSTS_DEVCTRLHLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) } while (--timeout && !(!is_on ^ !reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) static void __dwc3_gadget_stop(struct dwc3 *dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static int __dwc3_gadget_start(struct dwc3 *dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) dwc->connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) * Per databook, when we want to stop the gadget, if a control transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) * is still in process, complete it and get the core into setup phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (dwc->ep0state != EP0_SETUP_PHASE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) dwc->ep0state != EP0_UNCONNECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) if (dwc->delayed_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) dwc3_ep0_send_delayed_status(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) reinit_completion(&dwc->ep0_in_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) * Section 4.1.8 Table 4-7, it states that for a device-initiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) * command for any active transfers" before clearing the RunStop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) * bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) dwc3_stop_active_transfers(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) __dwc3_gadget_stop(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) * Note: if the GEVNTCOUNT indicates events in the event buffer, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) * driver needs to acknowledge them before the controller can halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * Simply let the interrupt handler acknowledges and handle the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * remaining event generated by the controller while polling for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * DSTS.DEVCTLHLT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) return dwc3_gadget_run_stop(dwc, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) is_on = !!is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) vdwc->softconnect = is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) * Avoid issuing a runtime resume if the device is already in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * suspended state during gadget disconnect. DWC3 gadget was already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) * halted/stopped during runtime suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) if (!is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) pm_runtime_barrier(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (pm_runtime_suspended(dwc->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) * Check the return value for successful resume, or error. For a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * successful resume, the DWC3 runtime PM resume routine will handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) * the run stop sequence, so avoid duplicate operations here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) ret = pm_runtime_get_sync(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) if (!ret || ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) pm_runtime_put(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (dwc->pullups_connected == is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) pm_runtime_put(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) synchronize_irq(dwc->irq_gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if (!is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) ret = dwc3_gadget_soft_disconnect(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) * In the Synopsys DWC_usb31 1.90a programming guide section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) * 4.1.9, it specifies that for a reconnect after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) * device-initiated disconnect requires a core soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) * (DCTL.CSftRst) before enabling the run/stop bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) dwc3_core_soft_reset(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) dwc3_event_buffers_setup(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) __dwc3_gadget_start(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) ret = dwc3_gadget_run_stop(dwc, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) pm_runtime_put(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* Enable all but Start and End of Frame IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) DWC3_DEVTEN_CMDCMPLTEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) DWC3_DEVTEN_ERRTICERREN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) DWC3_DEVTEN_WKUPEVTEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) DWC3_DEVTEN_CONNECTDONEEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) DWC3_DEVTEN_USBRSTEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) DWC3_DEVTEN_DISCONNEVTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (DWC3_VER_IS_PRIOR(DWC3, 250A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) reg |= DWC3_DEVTEN_ULSTCNGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) /* mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) * @dwc: pointer to our context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) * The following looks like complex but it's actually very simple. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) * calculate the number of packets we can burst at once on OUT transfers, we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) * gonna use RxFIFO size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) * To calculate RxFIFO size we need two numbers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) * MDWIDTH = size, in bits, of the internal memory bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) * Given these two numbers, the formula is simple:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) * 24 bytes is for 3x SETUP packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * 16 bytes is a clock domain crossing tolerance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) u32 ram2_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) u32 mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) u32 nump;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) mdwidth = dwc3_mdwidth(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) nump = min_t(u32, nump, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) /* update NumP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) reg &= ~DWC3_DCFG_NUMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) reg |= nump << DWC3_DCFG_NUMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static int __dwc3_gadget_start(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) * If the DWC3 is in runtime suspend, the clocks maybe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) * disabled, so avoid enable the DWC3 endpoints here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) * The DWC3 runtime PM resume routine will handle the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) * gadget start sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) if (pm_runtime_suspended(dwc->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) * the core supports IMOD, disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) if (dwc->imod_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) } else if (dwc3_has_imod(dwc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) * field instead of letting dwc3 itself calculate that automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) * This way, we maximize the chances that we'll be able to get several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) * bursts of data without going through any sort of endpoint throttling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) dwc3_gadget_setup_nump(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) * Currently the controller handles single stream only. So, Ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) * Packet Pending bit for stream selection and don't search for another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) * stream if the host sends Data Packet with PP=0 (for OUT direction) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) * the stream performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) reg |= DWC3_DCFG_IGNSTRMPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) /* Start with SuperSpeed Default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) dep->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) dev_err(dwc->dev, "failed to enable %s\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) dep = dwc->eps[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) dep->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) dev_err(dwc->dev, "failed to enable %s\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) /* begin to receive SETUP packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) dwc->ep0state = EP0_SETUP_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) dwc->ep0_bounced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) dwc->link_state = DWC3_LINK_STATE_SS_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) dwc->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) dwc3_ep0_out_start(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) dwc3_gadget_enable_irq(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) __dwc3_gadget_ep_disable(dwc->eps[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static int dwc3_gadget_start(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) irq = dwc->irq_gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) IRQF_SHARED, "dwc3", dwc->ev_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) if (dwc->gadget_driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) dev_err(dwc->dev, "%s is already bound to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) dwc->gadget->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) dwc->gadget_driver->driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) dwc->gadget_driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) free_irq(irq, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static void __dwc3_gadget_stop(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) dwc3_gadget_disable_irq(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) __dwc3_gadget_ep_disable(dwc->eps[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) __dwc3_gadget_ep_disable(dwc->eps[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) static int dwc3_gadget_stop(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) if (!dwc->gadget_driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) dev_warn(dwc->dev, "%s is already stopped\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) dwc->gadget->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) dwc->gadget_driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) dwc->max_cfg_eps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) free_irq(dwc->irq_gadget, dwc->ev_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) static void dwc3_gadget_config_params(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) struct usb_dcd_config_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /* Recommended BESL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) if (!dwc->dis_enblslpm_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * If the recommended BESL baseline is 0 or if the BESL deep is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) * less than 2, Microsoft's Windows 10 host usb stack will issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * a usb reset immediately after it receives the extended BOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) * descriptor and the enumeration will fail. To maintain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) * compatibility with the Windows' usb stack, let's set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) * recommended BESL baseline to 1 and clamp the BESL deep to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) * within 2 to 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) params->besl_baseline = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (dwc->is_utmi_l1_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) params->besl_deep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) clamp_t(u8, dwc->hird_threshold, 2, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) /* U1 Device exit Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) if (dwc->dis_u1_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) params->bU1devExitLat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* U2 Device exit Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) if (dwc->dis_u2_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) params->bU2DevExitLat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) params->bU2DevExitLat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) static void dwc3_gadget_set_speed(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) enum usb_device_speed speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) dwc->gadget_max_speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) enum usb_ssp_rate rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) dwc->gadget_ssp_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) union power_supply_propval val = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) if (dwc->usb2_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) return usb_phy_set_power(dwc->usb2_phy, mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (!dwc->usb_psy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) val.intval = 1000 * mA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) * @g: pointer to the USB gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) * Used to record the maximum number of endpoints being used in a USB composite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) * device. (across all configurations) This is to be used in the calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) * of the TXFIFO sizes when resizing internal memory for individual endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) * It will help ensured that the resizing logic reserves enough space for at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) * least one max packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) static int dwc3_gadget_check_config(struct usb_gadget *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) struct usb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) int fifo_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) int ram1_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) int ep_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) if (!dwc->do_fifo_resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) list_for_each_entry(ep, &g->ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) /* Only interested in the IN endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) if (ep->claimed && (ep->address & USB_DIR_IN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) ep_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) if (ep_num <= dwc->max_cfg_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /* Update the max number of eps in the composition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) dwc->max_cfg_eps = ep_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* Based on the equation, increment by one for every ep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) fifo_size += dwc->max_cfg_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) /* Check if we can fit a single fifo per endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) ram1_depth = dwc3_gadget_get_tx_fifos_size(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (fifo_size > ram1_depth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) struct dwc3 *dwc = gadget_to_dwc(g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) dwc->async_callbacks = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static const struct usb_gadget_ops dwc3_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) .get_frame = dwc3_gadget_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) .wakeup = dwc3_gadget_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) .set_selfpowered = dwc3_gadget_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) .pullup = dwc3_gadget_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) .udc_start = dwc3_gadget_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .udc_stop = dwc3_gadget_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .udc_set_speed = dwc3_gadget_set_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) .get_config_params = dwc3_gadget_config_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .vbus_draw = dwc3_gadget_vbus_draw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .check_config = dwc3_gadget_check_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .udc_async_callbacks = dwc3_gadget_async_callbacks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) dep->endpoint.maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) dep->endpoint.ops = &dwc3_gadget_ep0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (!dep->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) dwc->gadget->ep0 = &dep->endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) dep->endpoint.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) u32 mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) mdwidth = dwc3_mdwidth(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* MDWIDTH is represented in bits, we need it in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) mdwidth /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) size = DWC3_GTXFIFOSIZ_TXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) size = DWC31_GTXFIFOSIZ_TXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) /* FIFO Depth is in MDWDITH bytes. Multiply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) size *= mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) * To meet performance requirement, a minimum TxFIFO size of 3x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) * MaxPacketSize is recommended for endpoints that support burst and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) * support burst. Use those numbers and we can calculate the max packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) * limit as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (dwc->maximum_speed >= USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) size /= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) size /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) * If enable tx fifos resize, set each in ep maxpacket
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) * to 1024, it can avoid being dependent on the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) * fifo size, and more flexible use of endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) if (dwc->do_fifo_resize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) usb_ep_set_maxpacket_limit(&dep->endpoint, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) dep->endpoint.max_streams = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) dep->endpoint.ops = &dwc3_gadget_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) list_add_tail(&dep->endpoint.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) &dwc->gadget->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) dep->endpoint.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dep->endpoint.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) dep->endpoint.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) return dwc3_alloc_trb_pool(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) u32 mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) mdwidth = dwc3_mdwidth(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) /* MDWIDTH is represented in bits, convert to bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) mdwidth /= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* All OUT endpoints share a single RxFIFO space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) if (DWC3_IP_IS(DWC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) size = DWC3_GRXFIFOSIZ_RXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) size = DWC31_GRXFIFOSIZ_RXFDEP(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) /* FIFO depth is in MDWDITH bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) size *= mdwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) * To meet performance requirement, a minimum recommended RxFIFO size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) * is defined as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) * RxFIFO size >= (3 x MaxPacketSize) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) * Then calculate the max packet limit as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) size -= (3 * 8) + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) if (size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) size /= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) usb_ep_set_maxpacket_limit(&dep->endpoint, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) dep->endpoint.max_streams = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) dep->endpoint.ops = &dwc3_gadget_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) list_add_tail(&dep->endpoint.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) &dwc->gadget->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) dep->endpoint.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) dep->endpoint.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) dep->endpoint.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) return dwc3_alloc_trb_pool(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) bool direction = epnum & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) u8 num = epnum >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) u8 num_in_eps, num_out_eps, min_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) dep = kzalloc(sizeof(*dep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) num_in_eps = DWC3_NUM_IN_EPS(&dwc->hwparams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) num_out_eps = dwc->num_eps - num_in_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) min_eps = min_t(u8, num_in_eps, num_out_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) /* reconfig direction and num if num_out_eps != num_in_eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) if (num + 1 > min_eps && num_in_eps != num_out_eps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) num = epnum - min_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) direction = num + 1 > num_out_eps ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) dep->dwc = dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) dep->number = num << 1 | direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) dep->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) dwc->eps[epnum] = dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) dep->combo_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) dep->start_cmd_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) direction ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) dep->endpoint.name = dep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) if (!(dep->number > 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) dep->endpoint.desc = &dwc3_gadget_ep0_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) dep->endpoint.comp_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if (num == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) ret = dwc3_gadget_init_control_endpoint(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) else if (direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) ret = dwc3_gadget_init_in_endpoint(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) ret = dwc3_gadget_init_out_endpoint(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) dep->endpoint.caps.dir_in = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) dep->endpoint.caps.dir_out = !direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) INIT_LIST_HEAD(&dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) INIT_LIST_HEAD(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) INIT_LIST_HEAD(&dep->cancelled_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) dwc3_debugfs_create_endpoint_dir(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) INIT_LIST_HEAD(&dwc->gadget->ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) for (epnum = 0; epnum < total; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) ret = dwc3_gadget_init_endpoint(dwc, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) dep = dwc->eps[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) * Physical endpoints 0 and 1 are special; they form the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) * bi-directional USB endpoint 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) * For those two physical endpoints, we don't allocate a TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) * pool nor do we add them the endpoints list. Due to that, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * shouldn't do these two operations otherwise we would end up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * with all sorts of bugs when removing dwc3.ko.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) if (epnum != 0 && epnum != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) dwc3_free_trb_pool(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) list_del(&dep->endpoint.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) debugfs_remove_recursive(debugfs_lookup(dep->name, dwc->root));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) kfree(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) struct dwc3_request *req, struct dwc3_trb *trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) const struct dwc3_event_depevt *event, int status, int chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) dwc3_ep_inc_deq(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) trace_dwc3_complete_trb(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) req->num_trbs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) * If we're in the middle of series of chained TRBs and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) * receive a short transfer along the way, DWC3 will skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) * through all TRBs including the last TRB in the chain (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) * where CHN bit is zero. DWC3 will also avoid clearing HWO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) * bit and SW has to do it manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) * We're going to do that here to avoid problems of HW trying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) * to use bogus TRBs for transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) * For isochronous transfers, the first TRB in a service interval must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) * have the Isoc-First type. Track and report its interval frame number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) unsigned int frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) frame_number &= ~(dep->interval - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) req->request.frame_number = frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) * this TRB points to the bounce buffer address, it's a MPS alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) * TRB. Don't add it to req->remaining calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) count = trb->size & DWC3_TRB_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) req->remaining += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) if (event->status & DEPEVT_STATUS_SHORT && !chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) (trb->ctrl & DWC3_TRB_CTRL_LST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) struct dwc3_request *req, const struct dwc3_event_depevt *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) struct scatterlist *sg = req->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) struct scatterlist *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) unsigned int num_queued = req->num_queued_sgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) for_each_sg(sg, s, num_queued, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) trb = &dep->trb_pool[dep->trb_dequeue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) req->sg = sg_next(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) req->num_queued_sgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) trb, event, status, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) struct dwc3_request *req, const struct dwc3_event_depevt *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) event, status, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) const struct dwc3_event_depevt *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) struct dwc3_request *req, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) if (req->request.num_mapped_sgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) req->request.actual = req->request.length - req->remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) if (!dwc3_gadget_ep_request_completed(req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) if (req->needs_extra_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) req->needs_extra_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) * If MISS ISOC happens, we need to move the req from started_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) * to cancelled_list, then unmap the req and clear the HWO of trb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) * Later in the dwc3_gadget_endpoint_trbs_complete(), it will move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) * the req from the cancelled_list to the pending_list, and restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) * the req for isoc transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) if (status == -EXDEV && usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) req->remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) req->needs_extra_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) if (req->trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) usb_gadget_unmap_request_by_dev(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) &req->request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) req->direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) req->trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) req->trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) dwc3_gadget_giveback(dep, req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) const struct dwc3_event_depevt *event, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) while (!list_empty(&dep->started_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) req = next_request(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) req, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) * The endpoint is disabled, let the dwc3_remove_requests()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) * handle the cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) if (!dep->endpoint.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (!dep->endpoint.desc || !dwc->pullups_connected ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) !dwc->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) if (!list_empty(&dep->pending_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) * We only need to check the first entry of the started list. We can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) * assume the completed requests are removed from the started list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) req = next_request(&dep->started_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) return !dwc3_gadget_ep_request_completed(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) dep->frame_number = event->parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) const struct dwc3_event_depevt *event, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) struct dwc3_request *req, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) bool no_started_trb = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) if (!dep->endpoint.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) return no_started_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) * If MISS ISOC happens, we need to do the following three steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) * to restart the reqs in the cancelled_list and pending_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) * in order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) * Step1. Move all the reqs from pending_list to the tail of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) * cancelled_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) * Step2. Move all the reqs from cancelled_list to the tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) * of pending_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) * Step3. Stop and restart an isoc transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && status == -EXDEV &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) !list_empty(&dep->cancelled_list) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) !list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) list_for_each_entry_safe(req, tmp, &dep->pending_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && status == -EXDEV &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) !list_empty(&dep->cancelled_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) dwc3_gadget_move_queued_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) list_empty(&dep->started_list) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) (list_empty(&dep->pending_list) || status == -EXDEV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) else if (dwc3_gadget_ep_should_continue(dep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) if (__dwc3_gadget_kick_transfer(dep) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) no_started_trb = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) * See dwc3_gadget_linksts_change_interrupt() for 1st half.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) dep = dwc->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) if (!(dep->flags & DWC3_EP_ENABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) if (!list_empty(&dep->started_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) return no_started_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) reg |= dwc->u1u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) dwc->u1u2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) return no_started_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) if (!dep->endpoint.desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) dwc3_gadget_endpoint_frame_from_event(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) if (event->status & DEPEVT_STATUS_BUSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) status = -ECONNRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) if (event->status & DEPEVT_STATUS_MISSED_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) status = -EXDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) dwc3_gadget_endpoint_trbs_complete(dep, event, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) if (event->status & DEPEVT_STATUS_BUSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) status = -ECONNRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) dwc3_gadget_endpoint_frame_from_event(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) * The XferNotReady event is generated only once before the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) * starts. It will be generated again when END_TRANSFER command is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) * issued. For some controller versions, the XferNotReady event may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) * generated while the END_TRANSFER command is still in process. Ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) * it and wait for the next XferNotReady event after the command is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) * completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) (void) __dwc3_gadget_start_isoc(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) if (cmd != DWC3_DEPCMD_ENDTRANSFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) * The END_TRANSFER command will cause the controller to generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) * NoStream Event, and it's not due to the host DP NoStream rejection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) * Ignore the next NoStream event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) if (dep->stream_capable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) dwc3_gadget_ep_cleanup_cancelled_requests(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) if (dwc3_send_clear_stall_ep_cmd(dep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) if (dwc->delayed_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) __dwc3_gadget_ep0_set_halt(ep0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) if (vdwc->clear_stall_protocol == dep->number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) dwc3_ep0_send_delayed_status(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) if ((dep->flags & DWC3_EP_DELAY_START) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) !usb_endpoint_xfer_isoc(dep->endpoint.desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) __dwc3_gadget_kick_transfer(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) dep->flags &= ~DWC3_EP_DELAY_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) if (event->status == DEPEVT_STREAMEVT_FOUND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) switch (event->parameters) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) case DEPEVT_STREAM_PRIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) * If the host can properly transition the endpoint state from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) * idle to prime after a NoStream rejection, there's no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) * force restarting the endpoint to reinitiate the stream. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) * simplify the check, assume the host follows the USB spec if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) * it primed the endpoint more than once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) case DEPEVT_STREAM_NOSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) * If the host rejects a stream due to no active stream, by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) * USB and xHCI spec, the endpoint will be put back to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) * state. When the host is ready (buffer added/updated), it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) * prime the endpoint to inform the usb device controller. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) * triggers the device controller to issue ERDY to restart the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) * stream. However, some hosts don't follow this and keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) * endpoint in the idle state. No prime will come despite host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) * streams are updated, and the device controller will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) * triggered to generate ERDY to move the next stream data. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) * workaround this and maintain compatibility with various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) * hosts, force to reinitate the stream until the host is ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) * instead of waiting for the host to prime the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) dep->flags |= DWC3_EP_DELAY_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) dwc3_stop_active_transfer(dep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) u8 epnum = event->endpoint_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) dep = dwc->eps[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (!(dep->flags & DWC3_EP_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) /* Handle only EPCMDCMPLT when EP disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) if (epnum == 0 || epnum == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) dwc3_ep0_interrupt(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) switch (event->endpoint_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) case DWC3_DEPEVT_XFERINPROGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) dwc3_gadget_endpoint_transfer_in_progress(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) case DWC3_DEPEVT_XFERNOTREADY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) dwc3_gadget_endpoint_transfer_not_ready(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) case DWC3_DEPEVT_EPCMDCMPLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) dwc3_gadget_endpoint_command_complete(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) case DWC3_DEPEVT_XFERCOMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) dwc3_gadget_endpoint_transfer_complete(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) case DWC3_DEPEVT_STREAMEVT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) dwc3_gadget_endpoint_stream_event(dep, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) case DWC3_DEPEVT_RXTXFIFOEVT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) static void dwc3_disconnect_gadget(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) dwc->gadget_driver->disconnect(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) static void dwc3_suspend_gadget(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) dwc->gadget_driver->suspend(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) static void dwc3_resume_gadget(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) if (dwc->async_callbacks && dwc->gadget_driver->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) dwc->gadget_driver->resume(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) static void dwc3_reset_gadget(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) if (!dwc->gadget_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) bool interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) * Only issue End Transfer command to the control endpoint of a started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) * Data Phase. Typically we should only do so in error cases such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) * invalid/unexpected direction as described in the control transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) * flow of the programming guide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) (dep->flags & DWC3_EP_DELAY_STOP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) * If a Setup packet is received but yet to DMA out, the controller will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) * not process the End Transfer command of any endpoint. Polling of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) * timeout. Delay issuing the End Transfer command until the Setup TRB is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) * prepared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) dep->flags |= DWC3_EP_DELAY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) * NOTICE: We are violating what the Databook says about the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) * EndTransfer command. Ideally we would _always_ wait for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) * EndTransfer Command Completion IRQ, but that's causing too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) * much trouble synchronizing between us and gadget driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) * We have discussed this with the IP Provider and it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) * suggested to giveback all requests here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) * Note also that a similar handling was tested by Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) * (thanks a lot Paul) and nothing bad has come out of it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) * In short, what we're doing is issuing EndTransfer with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) * CMDIOC bit set and delay kicking transfer until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) * EndTransfer command had completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) * As of IP version 3.10a of the DWC_usb3 IP, the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) * supports a mode to work around the above limitation. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) * software can poll the CMDACT bit in the DEPCMD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) * after issuing a EndTransfer command. This mode is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) * by writing GUCTL2[14]. This polling is already done in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) * dwc3_send_gadget_ep_cmd() function so if the mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) * enabled, the EndTransfer command will have completed upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) * returning from this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) * This mode is NOT available on the DWC_usb31 IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) __dwc3_stop_active_transfer(dep, force, interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) EXPORT_SYMBOL_GPL(dwc3_stop_active_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) u32 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) dep = dwc->eps[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) if (!(dep->flags & DWC3_EP_STALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) dep->flags &= ~DWC3_EP_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) ret = dwc3_send_clear_stall_ep_cmd(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) WARN_ON_ONCE(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) reg &= ~DWC3_DCTL_INITU1ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) reg &= ~DWC3_DCTL_INITU2ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) dwc->connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) dwc3_disconnect_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) dwc->gadget->speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) dwc->setup_packet_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) if (dwc->ep0state != EP0_SETUP_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) unsigned int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) dir = !!dwc->ep0_expect_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (dwc->ep0state == EP0_DATA_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) * Ideally, dwc3_reset_gadget() would trigger the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) * drivers to stop any active transfers through ep disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) * However, for functions which defer ep disable, such as mass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) * storage, we will need to rely on the call to stop active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) * transfers here, and avoid allowing of request queuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) dwc->connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) * WORKAROUND: DWC3 revisions <1.88a have an issue which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) * would cause a missing Disconnect Event if there's a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) * pending Setup Packet in the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) * There's no suggested workaround on the official Bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) * report, which states that "unless the driver/application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) * is doing any special handling of a disconnect event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) * there is no functional issue".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) * Unfortunately, it turns out that we _do_ some special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) * handling of a disconnect event, namely complete all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) * pending transfers, notify gadget driver of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) * disconnection, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) * Our suggested workaround is to follow the Disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) * Event steps here, instead, based on a setup_packet_pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) * flag. Such flag gets set whenever we have a SETUP_PENDING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) * status for EP0 TRBs and gets cleared on XferComplete for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) * same endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) * STAR#9000466709: RTL: Device : Disconnect event not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) * generated if setup packet pending in FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) if (dwc->setup_packet_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) dwc3_gadget_disconnect_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) dwc3_reset_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) * From SNPS databook section 8.1.2, the EP0 should be in setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) * phase. So ensure that EP0 is in setup phase by issuing a stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) * and restart if EP0 is not in setup phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) if (dwc->ep0state != EP0_SETUP_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) unsigned int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) dir = !!dwc->ep0_expect_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) if (dwc->ep0state == EP0_DATA_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) dwc->eps[0]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) dwc->eps[1]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) * needs to ensure that it sends "a DEPENDXFER command for any active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) * transfers."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) dwc3_stop_active_transfers(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) dwc->connected = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) reg &= ~DWC3_DCTL_TSTCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) dwc->test_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) dwc3_clear_stall_all_ep(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) /* Reset device address to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) reg &= ~(DWC3_DCFG_DEVADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) u8 lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) u8 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) if (!vdwc->softconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) reg = dwc3_readl(dwc->regs, DWC3_DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) speed = reg & DWC3_DSTS_CONNECTSPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) dwc->speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) if (DWC3_IP_IS(DWC32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) lanes = DWC3_DSTS_CONNLANES(reg) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) * each time on Connect Done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) * Currently we always use the reset value. If any platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) * wants to set this to a different value, we need to add a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) * setting and update GCTL.RAMCLKSEL here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) case DWC3_DSTS_SUPERSPEED_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) dwc->gadget->ep0->maxpacket = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) if (lanes > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) case DWC3_DSTS_SUPERSPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) * WORKAROUND: DWC3 revisions <1.90a have an issue which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) * would cause a missing USB3 Reset event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) * In such situations, we should force a USB3 Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) * event by calling our dwc3_gadget_reset_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) * routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) * STAR#9000483510: RTL: SS : USB3 reset event may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) * not be generated always when the link enters poll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) if (DWC3_VER_IS_PRIOR(DWC3, 190A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) dwc3_gadget_reset_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) dwc->gadget->ep0->maxpacket = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) dwc->gadget->speed = USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) if (lanes > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) case DWC3_DSTS_HIGHSPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) dwc->gadget->ep0->maxpacket = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) dwc->gadget->speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) case DWC3_DSTS_FULLSPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) dwc->gadget->ep0->maxpacket = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) dwc->gadget->speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) case DWC3_DSTS_LOWSPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) dwc->gadget->ep0->maxpacket = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) dwc->gadget->speed = USB_SPEED_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) /* Enable USB2 LPM Capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) !dwc->usb2_gadget_lpm_disable &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) (speed != DWC3_DSTS_SUPERSPEED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) reg |= DWC3_DCFG_LPM_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) (dwc->is_utmi_l1_suspend << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) * DCFG.LPMCap is set, core responses with an ACK and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) * BESL value in the LPM token is less than or equal to LPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) * NYET threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) "LPM Erratum not available on dwc3 revisions < 2.40a\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) if (dwc->usb2_gadget_lpm_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) reg &= ~DWC3_DCFG_LPM_CAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) dev_err(dwc->dev, "failed to enable %s\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) dep = dwc->eps[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) dev_err(dwc->dev, "failed to enable %s\n", dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) * Configure PHY via GUSB3PIPECTLn if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) * Update GTXFIFOSIZn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) * In both cases reset values should be sufficient.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) * TODO take core out of low power mode when that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) * implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) if (dwc->async_callbacks && dwc->gadget_driver->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) dwc->gadget_driver->resume(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) unsigned int evtinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) unsigned int pwropt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) * WORKAROUND: DWC3 < 2.50a have an issue when configured without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) * Hibernation mode enabled which would show up when device detects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) * host-initiated U3 exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) * In that case, device will generate a Link State Change Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) * from U3 to RESUME which is only necessary if Hibernation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) * configured in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) * There are no functional changes due to such spurious event and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) * just need to ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) * operational mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) (next == DWC3_LINK_STATE_RESUME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) * on the link partner, the USB session might do multiple entry/exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) * of low power states before a transfer takes place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) * Due to this problem, we might experience lower throughput. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) * suggested workaround is to disable DCTL[12:9] bits if we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) * transitioning from U1/U2 to U0 and enable those bits again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) * after a transfer completes and there are no pending transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) * on any of the enabled endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * This is the first half of that workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * core send LGO_Ux entering U0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) if (next == DWC3_LINK_STATE_U0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) u32 u1u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) switch (dwc->link_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) case DWC3_LINK_STATE_U1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) case DWC3_LINK_STATE_U2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) u1u2 = reg & (DWC3_DCTL_INITU2ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) | DWC3_DCTL_ACCEPTU2ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) | DWC3_DCTL_INITU1ENA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) | DWC3_DCTL_ACCEPTU1ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) if (!dwc->u1u2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) dwc->u1u2 = reg & u1u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) reg &= ~u1u2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) dwc3_gadget_dctl_write_safe(dwc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) switch (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) case DWC3_LINK_STATE_U1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) if (dwc->speed == USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) dwc3_suspend_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) case DWC3_LINK_STATE_U2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) case DWC3_LINK_STATE_U3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) dwc3_suspend_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) case DWC3_LINK_STATE_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) dwc3_resume_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) /* do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) dwc->link_state = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) unsigned int evtinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) dwc3_suspend_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) dwc->link_state = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) unsigned int evtinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) unsigned int is_ss = evtinfo & BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) * WORKAROUND: DWC3 revison 2.20a with hibernation support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) * have a known issue which can cause USB CV TD.9.23 to fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) * randomly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) * Because of this issue, core could generate bogus hibernation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) * events which SW needs to ignore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) * Refers to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) * Device Fallback from SuperSpeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) /* enter hibernation here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) static void dwc3_gadget_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) const struct dwc3_event_devt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) switch (event->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) case DWC3_DEVICE_EVENT_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) dev_info(dwc->dev, "device disconnect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) dwc3_gadget_disconnect_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) case DWC3_DEVICE_EVENT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) dev_info(dwc->dev, "device reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) dwc3_gadget_reset_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) case DWC3_DEVICE_EVENT_CONNECT_DONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) dwc3_gadget_conndone_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) case DWC3_DEVICE_EVENT_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) dwc3_gadget_wakeup_interrupt(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) case DWC3_DEVICE_EVENT_HIBER_REQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) "unexpected hibernation event\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) case DWC3_DEVICE_EVENT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) /* It changed to be suspend event for version 2.30a and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) * Ignore suspend event until the gadget enters into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) * USB_STATE_CONFIGURED state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) if (dwc->gadget->state >= USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) dwc3_gadget_suspend_interrupt(dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) event->event_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) case DWC3_DEVICE_EVENT_SOF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) case DWC3_DEVICE_EVENT_CMD_CMPL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) case DWC3_DEVICE_EVENT_OVERFLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) static void dwc3_process_event_entry(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) const union dwc3_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) trace_dwc3_event(event->raw, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (!event->type.is_devspec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) dwc3_endpoint_interrupt(dwc, &event->depevt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) else if (event->type.type == DWC3_EVENT_TYPE_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) dwc3_gadget_interrupt(dwc, &event->devt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) struct dwc3 *dwc = evt->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) int left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) left = evt->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) if (!(evt->flags & DWC3_EVENT_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) while (left > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) union dwc3_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) event.raw = *(u32 *) (evt->cache + evt->lpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) dwc3_process_event_entry(dwc, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) * FIXME we wrap around correctly to the next entry as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) * almost all entries are 4 bytes in size. There is one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) * entry which has 12 bytes which is a regular entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) * followed by 8 bytes data. ATM I don't know how
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) * things are organized if we get next to the a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) * boundary so I worry about that once we try to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) * that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) evt->lpos = (evt->lpos + 4) % evt->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) left -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) evt->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) evt->flags &= ~DWC3_EVENT_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) /* Unmask interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) reg &= ~DWC3_GEVNTSIZ_INTMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) if (dwc->imod_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) struct dwc3_event_buffer *evt = _evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) struct dwc3 *dwc = evt->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) local_bh_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) ret = dwc3_process_event_buf(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) local_bh_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) struct dwc3 *dwc = evt->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) u32 amount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) if (pm_runtime_suspended(dwc->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) pm_runtime_get(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) disable_irq_nosync(dwc->irq_gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) dwc->pending_events = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) * With PCIe legacy interrupt, test shows that top-half irq handler can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) * be called again after HW interrupt deassertion. Check if bottom-half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) * irq event handler completes before caching new event to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) * losing events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) if (evt->flags & DWC3_EVENT_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) count &= DWC3_GEVNTCOUNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) evt->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) evt->flags |= DWC3_EVENT_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) /* Mask interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) reg |= DWC3_GEVNTSIZ_INTMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) amount = min(count, evt->length - evt->lpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) if (amount < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) memcpy(evt->cache, evt->buf, count - amount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) static irqreturn_t dwc3_interrupt(int irq, void *_evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) struct dwc3_event_buffer *evt = _evt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) return dwc3_check_event_buf(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) static int dwc3_gadget_get_irq(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) if (irq == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) irq = platform_get_irq(dwc3_pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) irq = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) static void dwc_gadget_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) kfree(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) * dwc3_gadget_init - initializes gadget related registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) * @dwc: pointer to our controller context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * Returns 0 on success otherwise negative errno.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) int dwc3_gadget_init(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) irq = dwc3_gadget_get_irq(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) dwc->irq_gadget = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) sizeof(*dwc->ep0_trb) * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) &dwc->ep0_trb_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) if (!dwc->ep0_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) dev_err(dwc->dev, "failed to allocate ep0 trb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) if (!dwc->setup_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) &dwc->bounce_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) if (!dwc->bounce) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) init_completion(&dwc->ep0_in_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) if (!dwc->gadget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) dev = &dwc->gadget->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) dev->platform_data = dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) dwc->gadget->ops = &dwc3_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) dwc->gadget->speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) dwc->gadget->sg_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) dwc->gadget->name = "dwc3-gadget";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) * FIXME We might be setting max_speed to <SUPER, however versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) * <2.20a of dwc3 have an issue with metastability (documented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) * elsewhere in this driver) which tells us we can't set max speed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * anything lower than SUPER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) * Because gadget.max_speed is only used by composite.c and function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) * drivers (i.e. it won't go into dwc3's registers) we are allowing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) * to happen so we avoid sending SuperSpeed Capability descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) * together with our BOS descriptor as that could confuse host into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) * thinking we can handle super speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) * Note that, in fact, we won't even support GetBOS requests when speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) * is less than super speed because we don't have means, yet, to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) * composite.c that we are USB 2.0 + LPM ECN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) !dwc->dis_metastability_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) dev_info(dwc->dev, "changing max_speed on rev %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) dwc->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) dwc->gadget->max_speed = dwc->maximum_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) * REVISIT: Here we should clear all pending IRQs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) * sure we're starting from a well known location.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) ret = usb_add_gadget(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) dev_err(dwc->dev, "failed to add gadget\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) goto err5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) err5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) dwc3_gadget_free_endpoints(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) usb_put_gadget(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) dwc->gadget = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) dwc->bounce_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) kfree(dwc->setup_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) dwc->ep0_trb, dwc->ep0_trb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) void dwc3_gadget_exit(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) if (!dwc->gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) usb_del_gadget(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) dwc3_gadget_free_endpoints(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) usb_put_gadget(dwc->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) dwc->bounce_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) kfree(dwc->setup_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) dwc->ep0_trb, dwc->ep0_trb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) int dwc3_gadget_suspend(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) if (!dwc->gadget_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) dwc3_gadget_run_stop(dwc, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) dwc3_disconnect_gadget(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) __dwc3_gadget_stop(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) int dwc3_gadget_resume(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) if (!dwc->gadget_driver || !vdwc->softconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) ret = __dwc3_gadget_start(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) ret = dwc3_gadget_run_stop(dwc, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) __dwc3_gadget_stop(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) if (dwc->pending_events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) dwc->pending_events = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) enable_irq(dwc->irq_gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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