^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Felipe Balbi <balbi@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/usb/composite.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "gadget.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dwc3_ep *dep, struct dwc3_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) dma_addr_t buf_dma, u32 len, u32 type, bool chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct dwc3 *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) trb = &dwc->ep0_trb[dep->trb_enqueue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) dep->trb_enqueue++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) trb->bpl = lower_32_bits(buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) trb->bph = upper_32_bits(buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) trb->size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) trb->ctrl = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) trb->ctrl |= (DWC3_TRB_CTRL_HWO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) | DWC3_TRB_CTRL_ISP_IMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) trb->ctrl |= DWC3_TRB_CTRL_CHN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) trb->ctrl |= (DWC3_TRB_CTRL_IOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) | DWC3_TRB_CTRL_LST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) trace_dwc3_prepare_trb(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dwc3 *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (dep->flags & DWC3_EP_TRANSFER_STARTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) params.param0 = upper_32_bits(dwc->ep0_trb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) params.param1 = lower_32_bits(dwc->ep0_trb_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dwc->ep0_next_event = DWC3_EP0_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) req->request.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) req->request.status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) req->epnum = dep->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) list_add_tail(&req->list, &dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Gadget driver might not be quick enough to queue a request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * before we get a Transfer Not Ready event on this endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * flag is set, it's telling us that as soon as Gadget queues the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * required request, we should kick the transfer here because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * IRQ we were waiting for is long gone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (dep->flags & DWC3_EP_PENDING_REQUEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) direction = !!(dep->flags & DWC3_EP0_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (dwc->ep0state != EP0_DATA_PHASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_WARN(dwc->dev, "Unexpected pending request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DWC3_EP0_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * In case gadget driver asked us to delay the STATUS phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * handle it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (dwc->delayed_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) direction = !dwc->ep0_expect_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dwc->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (dwc->ep0state == EP0_STATUS_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Unfortunately we have uncovered a limitation wrt the Data Phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Section 9.4 says we can wait for the XferNotReady(DATA) event to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * come before issueing Start Transfer command, but if we do, we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * miss situations where the host starts another SETUP phase instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * the DATA phase. Such cases happen at least on TD.7.6 of the Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Layer Compliance Suite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * The problem surfaces due to the fact that in case of back-to-back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * SETUP packets there will be no XferNotReady(DATA) generated and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * will be stuck waiting for XferNotReady(DATA) forever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * By looking at tables 9-13 and 9-14 of the Databook, we can see that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * it tells us to start Data Phase right away. It also mentions that if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * we receive a SETUP phase instead of the DATA phase, core will issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * XferComplete for the DATA phase, before actually initiating it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the wire, with the TRB's status set to "SETUP_PENDING". Such status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * can only be used to print some debugging logs, as the core expects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * just so it completes right away, without transferring anything and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * only then, we can go back to the SETUP phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Because of this scenario, SNPS decided to change the programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * model of control transfers and support on-demand transfers only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * the STATUS phase. To fix the issue we have now, we will always wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * for gadget driver to queue the DATA phase's struct usb_request, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * start it right away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * If we're actually in a 2-stage transfer, we will wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * XferNotReady(STATUS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (dwc->three_stage_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) direction = dwc->ep0_expect_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dwc->ep0state = EP0_DATA_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dep->flags &= ~DWC3_EP0_DIR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct dwc3_request *req = to_dwc3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* we share one TRB for ep0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = __dwc3_gadget_ep0_queue(dep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* reinitialize physical ep1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dep = dwc->eps[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dep->flags = DWC3_EP_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* stall is always issued on EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __dwc3_gadget_ep_set_halt(dep, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dep->flags = DWC3_EP_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dwc->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct dwc3_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) req = next_request(&dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dwc3_gadget_giveback(dep, req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dwc->eps[0]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dwc->eps[1]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dwc->ep0state = EP0_SETUP_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dwc3_ep0_out_start(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_lock_irqsave(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = __dwc3_gadget_ep0_set_halt(ep, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_unlock_irqrestore(&dwc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void dwc3_ep0_out_start(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) complete(&dwc->ep0_in_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DWC3_TRBCTL_CONTROL_SETUP, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) WARN_ON(ret < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct dwc3_ep *dwc3_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dwc3_ep = dwc->eps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!dwc3_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (dwc->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dwc3_stop_active_transfer(dwc3_ep, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 windex = le16_to_cpu(wIndex_le);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 ep, epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 num_in_eps, num_out_eps, min_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) num_in_eps = DWC3_NUM_IN_EPS(&dwc->hwparams);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) num_out_eps = dwc->num_eps - num_in_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) min_eps = min_t(u8, num_in_eps, num_out_eps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ep = windex & USB_ENDPOINT_NUMBER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ep + 1 > min_eps && num_in_eps != num_out_eps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) epnum = ep + min_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) epnum = ep << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) epnum |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dep = dwc->eps[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (dep == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (dep->flags & DWC3_EP_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * ch 9.4.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int dwc3_ep0_handle_status(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 recip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 usb_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __le16 *response_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* We don't support PTM_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) value = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (value != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) recip = ctrl->bRequestType & USB_RECIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (recip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * LTM will be set once we know how to set this in HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) usb_status |= dwc->gadget->is_selfpowered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (reg & DWC3_DCTL_INITU1ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (reg & DWC3_DCTL_INITU2ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Function Remote Wake Capable D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Function Remote Wakeup D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (dep->flags & DWC3_EP_STALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) usb_status = 1 << USB_ENDPOINT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) response_pkt = (__le16 *) dwc->setup_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *response_pkt = cpu_to_le16(usb_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dwc->ep0_usb_req.dep = dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dwc->ep0_usb_req.request.buf = dwc->setup_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (state != USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (set && dwc->dis_u1_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) reg |= DWC3_DCTL_INITU1ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) reg &= ~DWC3_DCTL_INITU1ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (state != USB_STATE_CONFIGURED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (set && dwc->dis_u2_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) reg |= DWC3_DCTL_INITU2ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reg &= ~DWC3_DCTL_INITU2ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 wIndex, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if ((wIndex & 0xff) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (wIndex >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case USB_TEST_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case USB_TEST_K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case USB_TEST_SE0_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case USB_TEST_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case USB_TEST_FORCE_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dwc->test_mode_nr = wIndex >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dwc->test_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int dwc3_ep0_handle_device(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct usb_ctrlrequest *ctrl, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) enum usb_device_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) wValue = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) wIndex = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) state = dwc->gadget->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case USB_DEVICE_REMOTE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * 9.4.1 says only for SS, in AddressState only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * default control pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case USB_DEVICE_U1_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = dwc3_ep0_handle_u1(dwc, state, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case USB_DEVICE_U2_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = dwc3_ep0_handle_u2(dwc, state, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case USB_DEVICE_LTM_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct usb_ctrlrequest *ctrl, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) wValue = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case USB_INTRF_FUNC_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * REVISIT: Ideally we would enable some low power mode here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * however it's unclear what we should be doing here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * For now, we're not doing anything, just making sure we return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * 0 so USB Command Verifier tests pass without any errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct usb_ctrlrequest *ctrl, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) wValue = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case USB_ENDPOINT_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = __dwc3_gadget_ep_set_halt(dep, set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* ClearFeature(Halt) may need delayed status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return USB_GADGET_DELAYED_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct usb_ctrlrequest *ctrl, int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 recip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) recip = ctrl->bRequestType & USB_RECIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) switch (recip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = dwc3_ep0_handle_device(dwc, ctrl, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) enum usb_device_state state = dwc->gadget->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) addr = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (addr > 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dwc->dev, "invalid device address %d\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (state == USB_STATE_CONFIGURED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) reg = dwc3_readl(dwc->regs, DWC3_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reg &= ~(DWC3_DCFG_DEVADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg |= DWC3_DCFG_DEVADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dwc3_writel(dwc->regs, DWC3_DCFG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (dwc->async_callbacks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_unlock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_lock(&dwc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) enum usb_device_state state = dwc->gadget->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cfg = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case USB_STATE_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case USB_STATE_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dwc3_gadget_clear_tx_fifos(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = dwc3_ep0_delegate_req(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* if the cfg matches and the cfg is non zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * only change state if set_config has already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * been processed. If gadget driver returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * USB_GADGET_DELAYED_STATUS, we will wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * to change the state on the next usb_ep_queue()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) usb_gadget_set_state(dwc->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) USB_STATE_CONFIGURED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Enable transition to U1/U2 state when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * nothing is pending from application.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!dwc->dis_u1_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) reg |= DWC3_DCTL_ACCEPTU1ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!dwc->dis_u2_entry_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) reg |= DWC3_DCTL_ACCEPTU2ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dwc3_writel(dwc->regs, DWC3_DCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case USB_STATE_CONFIGURED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = dwc3_ep0_delegate_req(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!cfg && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) usb_gadget_set_state(dwc->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) USB_STATE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct dwc3_ep *dep = to_dwc3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 param = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 u1sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u8 u1pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __le16 u2sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __le16 u2pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } __packed timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) memcpy(&timing, req->buf, sizeof(timing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dwc->u1sel = timing.u1sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dwc->u1pel = timing.u1pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dwc->u2sel = le16_to_cpu(timing.u2sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dwc->u2pel = le16_to_cpu(timing.u2pel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reg = dwc3_readl(dwc->regs, DWC3_DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (reg & DWC3_DCTL_INITU2ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) param = dwc->u2pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (reg & DWC3_DCTL_INITU1ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) param = dwc->u1pel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * According to Synopsys Databook, if parameter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * greater than 125, a value of zero should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * programmed in the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (param > 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) param = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* now that we have the time, issue DGCMD Set Sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = dwc3_send_gadget_generic_command(dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) DWC3_DGCMD_SET_PERIODIC_PAR, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) WARN_ON(ret < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) enum usb_device_state state = dwc->gadget->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u16 wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (state == USB_STATE_DEFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) wLength = le16_to_cpu(ctrl->wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (wLength != 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * To handle Set SEL we need to receive 6 bytes from Host. So let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * queue a usb_request for 6 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * Remember, though, this controller can't handle non-wMaxPacketSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * aligned transfers on the OUT direction, so we queue a request for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * wMaxPacketSize instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dwc->ep0_usb_req.dep = dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dwc->ep0_usb_req.request.buf = dwc->setup_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u16 wLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u16 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u16 wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) wValue = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) wLength = le16_to_cpu(ctrl->wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) wIndex = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (wIndex || wLength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dwc->gadget->isoch_delay = wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = dwc3_ep0_handle_status(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = dwc3_ep0_set_address(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case USB_REQ_SET_CONFIGURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = dwc3_ep0_set_config(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case USB_REQ_SET_SEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = dwc3_ep0_set_sel(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case USB_REQ_SET_ISOCH_DELAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = dwc3_ep0_delegate_req(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!dwc->gadget_driver || !vdwc->softconnect || !dwc->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) trace_dwc3_ctrl_req(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) len = le16_to_cpu(ctrl->wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dwc->three_stage_setup = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dwc->ep0_expect_in = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dwc->three_stage_setup = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = dwc3_ep0_std_request(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = dwc3_ep0_delegate_req(dwc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret == USB_GADGET_DELAYED_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dwc->delayed_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static void dwc3_ep0_complete_data(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct dwc3_request *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct usb_request *ur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct dwc3_ep *ep0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 transferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) epnum = event->endpoint_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ep0 = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) trb = dwc->ep0_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) trace_dwc3_complete_trb(ep0, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) r = next_request(&ep0->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) status = DWC3_TRB_SIZE_TRBSTS(trb->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (status == DWC3_TRBSTS_SETUP_PENDING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dwc->setup_packet_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dwc3_gadget_giveback(ep0, r, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ur = &r->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) length = trb->size & DWC3_TRB_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) transferred = ur->length - length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ur->actual += transferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ur->length && ur->zero) || dwc->ep0_bounced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) trb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) trace_dwc3_complete_trb(ep0, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (r->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dwc->eps[1]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dwc->eps[0]->trb_enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dwc->ep0_bounced = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if ((epnum & 1) && ur->actual < ur->length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dwc3_gadget_giveback(ep0, r, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void dwc3_ep0_complete_status(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct dwc3_request *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct dwc3_ep *dep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct dwc3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) trb = dwc->ep0_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) trace_dwc3_complete_trb(dep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) r = next_request(&dep->pending_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dwc3_gadget_giveback(dep, r, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (dwc->test_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(dwc->dev, "invalid test #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dwc->test_mode_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) status = DWC3_TRB_SIZE_TRBSTS(trb->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (status == DWC3_TRBSTS_SETUP_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dwc->setup_packet_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dwc->ep0state = EP0_SETUP_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dwc3_ep0_out_start(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dep->resource_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dwc->setup_packet_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) switch (dwc->ep0state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) case EP0_SETUP_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dwc3_ep0_inspect_setup(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case EP0_DATA_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dwc3_ep0_complete_data(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case EP0_STATUS_PHASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dwc3_ep0_complete_status(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct dwc3_ep *dep, struct dwc3_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned int trb_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) req->direction = !!dep->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (req->request.length == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!req->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) trb_length = dep->endpoint.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) DWC3_TRBCTL_CONTROL_DATA, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) && (dep->number == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = usb_gadget_map_request_by_dev(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) &req->request, dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) maxpacket = dep->endpoint.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) rem = req->request.length % maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dwc->ep0_bounced = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* prepare normal TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dwc3_ep0_prepare_one_trb(dep, req->request.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) req->request.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DWC3_TRBCTL_CONTROL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Now prepare one extra TRB to align transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) maxpacket - rem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) DWC3_TRBCTL_CONTROL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) req->request.length && req->request.zero) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = usb_gadget_map_request_by_dev(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &req->request, dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* prepare normal TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dwc3_ep0_prepare_one_trb(dep, req->request.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) req->request.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) DWC3_TRBCTL_CONTROL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!req->direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) trb_length = dep->endpoint.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Now prepare one extra TRB to align transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) trb_length, DWC3_TRBCTL_CONTROL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ret = usb_gadget_map_request_by_dev(dwc->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) &req->request, dep->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dwc3_ep0_prepare_one_trb(dep, req->request.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) req->request.length, DWC3_TRBCTL_CONTROL_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) req->trb = &dwc->ep0_trb[dep->trb_enqueue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) WARN_ON(ret < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct dwc3 *dwc = dep->dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) : DWC3_TRBCTL_CONTROL_STATUS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return dwc3_ep0_start_trans(dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) WARN_ON(dwc3_ep0_start_control_status(dep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __dwc3_ep0_do_control_status(dwc, dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) unsigned int direction = !dwc->ep0_expect_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dwc->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) vdwc->clear_stall_protocol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (dwc->ep0state != EP0_STATUS_PHASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct dwc3_gadget_ep_cmd_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * For status/DATA OUT stage, TRB will be queued on ep0 out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * endpoint for which resource index is zero. Hence allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * queuing ENDXFER command for ep0 out endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!dep->resource_index && dep->number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) cmd = DWC3_DEPCMD_ENDTRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) cmd |= DWC3_DEPCMD_CMDIOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) memset(¶ms, 0, sizeof(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) WARN_ON_ONCE(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dep->resource_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct dwc3_vendor *vdwc = container_of(dwc, struct dwc3_vendor, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) switch (event->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case DEPEVT_STATUS_CONTROL_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (!vdwc->softconnect || !dwc->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * We already have a DATA transfer in the controller's cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * if we receive a XferNotReady(DATA) we will ignore it, unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * it's for the wrong direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * In that case, we must issue END_TRANSFER command to the Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * Phase we already have started and issue SetStall on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * control endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (dwc->ep0_expect_in != event->endpoint_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(dwc->dev, "unexpected direction for Data Phase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dwc3_ep0_end_control_data(dwc, dep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case DEPEVT_STATUS_CONTROL_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (dwc->setup_packet_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dwc3_ep0_stall_and_restart(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dwc->ep0state = EP0_STATUS_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (dwc->delayed_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct dwc3_ep *dep = dwc->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) WARN_ON_ONCE(event->endpoint_number != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * We should handle the delay STATUS phase here if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * request for handling delay STATUS has been queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * into the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (!list_empty(&dep->pending_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dwc->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) usb_gadget_set_state(dwc->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) USB_STATE_CONFIGURED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dwc3_ep0_do_control_status(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dwc3_ep0_do_control_status(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) void dwc3_ep0_interrupt(struct dwc3 *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) const struct dwc3_event_depevt *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) switch (event->endpoint_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case DWC3_DEPEVT_XFERCOMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dwc3_ep0_xfer_complete(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case DWC3_DEPEVT_XFERNOTREADY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dwc3_ep0_xfernotready(dwc, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case DWC3_DEPEVT_XFERINPROGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case DWC3_DEPEVT_RXTXFIFOEVT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case DWC3_DEPEVT_STREAMEVT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case DWC3_DEPEVT_EPCMDCMPLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) cmd = DEPEVT_PARAMETER_CMD(event->parameters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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