Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This is a small driver for the dwc3 to provide the glue logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * to configure the controller. Tested on STi platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2014 Stmicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Contributors: Aymen Bouattay <aymen.bouattay@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *               Peter Griffin <peter.griffin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Inspired by dwc3-omap.c and dwc3-exynos.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/usb/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "io.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* glue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLKRST_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AUX_CLK_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SW_PIPEW_RESET_N	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EXT_CFG_RESET_N		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * 1'b0 : The host controller complies with the xHCI revision 0.96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * 1'b1 : The host controller complies with the xHCI revision 1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define XHCI_REVISION		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define USB2_VBUS_MNGMNT_SEL1	0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * For all fields in USB2_VBUS_MNGMNT_SEL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * 2’b00 : Override value from Reg 0x30 is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * 2’b01 : utmiotg_<signal_name> from usb3_top is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * 2’b10 : pipew_<signal_name> from PIPEW instance is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * 2’b11 : value is 1'b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define USB2_VBUS_REG30		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define USB2_VBUS_UTMIOTG	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define USB2_VBUS_PIPEW		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define USB2_VBUS_ZERO		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SEL_OVERRIDE_VBUSVALID(n)	(n << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SEL_OVERRIDE_POWERPRESENT(n)	(n << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SEL_OVERRIDE_BVALID(n)		(n << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Static DRD configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define USB3_CONTROL_MASK		0xf77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define USB3_DEVICE_NOT_HOST		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define USB3_FORCE_VBUSVALID		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define USB3_DELAY_VBUSVALID		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define USB3_SEL_FORCE_OPMODE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define USB3_FORCE_OPMODE(n)		(n << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define USB3_SEL_FORCE_DPPULLDOWN2	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define USB3_FORCE_DPPULLDOWN2		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define USB3_SEL_FORCE_DMPULLDOWN2	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define USB3_FORCE_DMPULLDOWN2		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * struct st_dwc3 - dwc3-st driver private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @dev:		device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @glue_base:		ioaddr for the glue registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @regmap:		regmap pointer for getting syscfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @syscfg_reg_off:	usb syscfg control offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * @dr_mode:		drd static host/device config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * @rstc_pwrdn:		rest controller for powerdown signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * @rstc_rst:		reset controller for softreset signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) struct st_dwc3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void __iomem *glue_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int syscfg_reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	enum usb_dr_mode dr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct reset_control *rstc_pwrdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct reset_control *rstc_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static inline u32 st_dwc3_readl(void __iomem *base, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel_relaxed(value, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * st_dwc3_drd_init: program the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * @dwc3_data: driver private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * Description: this function is to program the port as either host or device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * according to the static configuration passed from devicetree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * OTG and dual role are not yet supported!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	val &= USB3_CONTROL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	switch (dwc3_data->dr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case USB_DR_MODE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		val &= ~(USB3_DELAY_VBUSVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			| USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 * USB3_PORT2_FORCE_VBUSVALID When '1' and when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		 * USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		 * of the pico PHY to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	case USB_DR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			| USB3_SEL_FORCE_OPMODE	| USB3_FORCE_OPMODE(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			| USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			| USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		 * when set to ‘0‘, it can delay the arrival of VBUSVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 * information to VBUSVLDEXT2 input of the pico PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * We don't want to do that so we set the bit to '1'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		val |= USB3_DELAY_VBUSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			dwc3_data->dr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * st_dwc3_init: init the controller via glue logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * @dwc3_data: driver private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void st_dwc3_init(struct st_dwc3 *dwc3_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	reg &= ~SW_PIPEW_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* configure mux for vbus, powerpresent and bvalid signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	reg |= SW_PIPEW_RESET_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int st_dwc3_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct st_dwc3 *dwc3_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct device_node *node = dev->of_node, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct platform_device *child_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!dwc3_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	dwc3_data->glue_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		devm_platform_ioremap_resource_byname(pdev, "reg-glue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(dwc3_data->glue_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(dwc3_data->glue_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	dwc3_data->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	dwc3_data->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		goto undo_platform_dev_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dwc3_data->syscfg_reg_off = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dev_vdbg(&pdev->dev, "glue-logic addr 0x%pK, syscfg-reg offset 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		 dwc3_data->glue_base, dwc3_data->syscfg_reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	dwc3_data->rstc_pwrdn =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		devm_reset_control_get_exclusive(dev, "powerdown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (IS_ERR(dwc3_data->rstc_pwrdn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_err(&pdev->dev, "could not get power controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		ret = PTR_ERR(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		goto undo_platform_dev_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* Manage PowerDown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	reset_control_deassert(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dwc3_data->rstc_rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		devm_reset_control_get_shared(dev, "softreset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (IS_ERR(dwc3_data->rstc_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		dev_err(&pdev->dev, "could not get reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		ret = PTR_ERR(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		goto undo_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Manage SoftReset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	reset_control_deassert(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	child = of_get_child_by_name(node, "dwc3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		dev_err(&pdev->dev, "failed to find dwc3 core node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Allocate and initialize the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = of_platform_populate(node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(dev, "failed to add dwc3 core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	child_pdev = of_find_device_by_node(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (!child_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		dev_err(dev, "failed to find dwc3 core device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	of_dev_put(child_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 * Configure the USB port as device or host according to the static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * configuration passed from DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * DRD is the only mode currently supported so this will be enhanced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * as soon as OTG is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = st_dwc3_drd_init(dwc3_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(dev, "drd initialisation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto undo_softreset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/* ST glue logic init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	st_dwc3_init(dwc3_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	platform_set_drvdata(pdev, dwc3_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err_node_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) undo_softreset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	reset_control_assert(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) undo_powerdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	reset_control_assert(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) undo_platform_dev_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int st_dwc3_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	of_platform_depopulate(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	reset_control_assert(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	reset_control_assert(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int st_dwc3_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	reset_control_assert(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	reset_control_assert(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int st_dwc3_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	reset_control_deassert(dwc3_data->rstc_pwrdn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	reset_control_deassert(dwc3_data->rstc_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ret = st_dwc3_drd_init(dwc3_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(dev, "drd initialisation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* ST glue logic init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	st_dwc3_init(dwc3_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct of_device_id st_dwc3_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	{ .compatible = "st,stih407-dwc3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(of, st_dwc3_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct platform_driver st_dwc3_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.probe = st_dwc3_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.remove = st_dwc3_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.name = "usb-st-dwc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.of_match_table = st_dwc3_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.pm = &st_dwc3_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) module_platform_driver(st_dwc3_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_LICENSE("GPL v2");