Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * dwc3-rockchip-inno.c - Rockchip DWC3 Specific Glue layer with INNO PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors: William Wu <william.wu@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software: you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * it under the terms of the GNU General Public License version 2 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * the License as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/usb/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define XHCI_TSTCTRL_MASK		(0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct dwc3_rockchip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct clk		**clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	int			num_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct dwc3		*dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct usb_phy		*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct notifier_block	u3phy_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct work_struct      u3_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct mutex		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int u3phy_disconnect_det_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					 unsigned long event, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct dwc3_rockchip *rockchip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		container_of(nb, struct dwc3_rockchip, u3phy_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	schedule_work(&rockchip->u3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void u3phy_disconnect_det_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct dwc3_rockchip *rockchip =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		container_of(work, struct dwc3_rockchip, u3_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct usb_hcd	*hcd = dev_get_drvdata(&rockchip->dwc->xhci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32		count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mutex_lock(&rockchip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (hcd->state != HC_STATE_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		dwc3_host_exit(rockchip->dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (rockchip->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		usb_phy_shutdown(rockchip->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	while (hcd->state != HC_STATE_HALT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (++count > 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			dev_err(rockchip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				"wait for HCD remove 1s timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (hcd->state == HC_STATE_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		dwc3_host_init(rockchip->dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (rockchip->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		usb_phy_init(rockchip->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mutex_unlock(&rockchip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int dwc3_rockchip_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct dwc3_rockchip	*rockchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct device		*dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct device_node	*np = dev->of_node, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct platform_device	*child_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int		count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int			ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int			i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (!rockchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	child = of_get_child_by_name(np, "dwc3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (!child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		dev_err(dev, "failed to find dwc3 core node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	count = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rockchip->num_clocks = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			sizeof(struct clk *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (!rockchip->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	platform_set_drvdata(pdev, rockchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	rockchip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	for (i = 0; i < rockchip->num_clocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		struct clk	*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		clk = of_clk_get(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		rockchip->clks[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_err(dev, "get_sync failed with err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ret = of_platform_populate(np, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	child_pdev = of_find_device_by_node(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!child_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_err(dev, "failed to find dwc3 core device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rockchip->dwc = platform_get_drvdata(child_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!rockchip->dwc || !rockchip->dwc->xhci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		dev_dbg(dev, "failed to get drvdata dwc3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	mutex_init(&rockchip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	rockchip->phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (rockchip->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		INIT_WORK(&rockchip->u3_work, u3phy_disconnect_det_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		rockchip->u3phy_nb.notifier_call =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			u3phy_disconnect_det_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		usb_register_notifier(rockchip->phy, &rockchip->u3phy_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	of_platform_depopulate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (!pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			clk_disable(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		clk_unprepare(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		clk_put(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int dwc3_rockchip_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct dwc3_rockchip	*rockchip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct device		*dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int			i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	of_platform_depopulate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	for (i = 0; i < rockchip->num_clocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		if (!pm_runtime_status_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			clk_disable(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		clk_unprepare(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		clk_put(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int dwc3_rockchip_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct dwc3_rockchip	*rockchip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	int			i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	for (i = 0; i < rockchip->num_clocks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		clk_disable(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int dwc3_rockchip_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct dwc3_rockchip	*rockchip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int			ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int			i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	for (i = 0; i < rockchip->num_clocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ret = clk_enable(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				clk_disable(rockchip->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			   dwc3_rockchip_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DEV_PM_OPS	(&dwc3_rockchip_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DEV_PM_OPS	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id rockchip_dwc3_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{ .compatible = "rockchip,rk3328-dwc3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	{ /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_driver dwc3_rockchip_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.probe		= dwc3_rockchip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.remove		= dwc3_rockchip_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.name	= "rockchip-inno-dwc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.pm	= DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.of_match_table = rockchip_dwc3_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) module_platform_driver(dwc3_rockchip_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_ALIAS("platform:rockchip-inno-dwc3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DESCRIPTION("DesignWare USB3 rockchip-inno Glue Layer");