^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dwc3-pci.c - PCI Specific glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Felipe Balbi <balbi@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_DEVICE_ID_INTEL_JSP 0x4dee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_INTEL_TGL 0x9a15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_INTEL_BXT_STATE_D0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_INTEL_BXT_STATE_D3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GP_RWBAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GP_RWREG1 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct dwc3_pci - Driver private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @dwc3: child dwc3 platform_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pci: our link to PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @guid: _DSM GUID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @wakeup_work: work for asynchronous resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct dwc3_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct platform_device *dwc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) guid_t guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int has_dsm_for_pm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct work_struct wakeup_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "reset-gpios", &reset_gpios, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "cs-gpios", &cs_gpios, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct gpiod_lookup_table platform_bytcr_gpios = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .dev_id = "0000:00:16.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg = pcim_iomap(pci, GP_RWBAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) value = readl(reg + GP_RWREG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) goto unmap; /* ULPI refclk already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(value, reg + GP_RWREG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* This comes from the Intel Android x86 tree w/o any explanation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pcim_iounmap(pci, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct property_entry dwc3_pci_intel_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct property_entry dwc3_pci_mrfld_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PROPERTY_ENTRY_STRING("dr_mode", "otg"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct property_entry dwc3_pci_amd_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* FIXME these quirks should be removed when AMD NL tapes out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct software_node dwc3_pci_intel_swnode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .properties = dwc3_pci_intel_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct software_node dwc3_pci_intel_mrfld_swnode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .properties = dwc3_pci_mrfld_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct software_node dwc3_pci_amd_swnode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .properties = dwc3_pci_amd_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int dwc3_pci_quirks(struct dwc3_pci *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pci_dev *pdev = dwc->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pdev->device == PCI_DEVICE_ID_INTEL_EHLLP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dwc->has_dsm_for_pm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* On BYT the FW does not always enable the refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = dwc3_byt_enable_ulpi_refclock(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) acpi_dwc3_byt_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_dbg(&pdev->dev, "failed to add mapping table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * A lot of BYT devices lack ACPI resource entries for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * the GPIOs, add a fallback mapping to the reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * design GPIOs which all boards seem to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gpiod_add_lookup_table(&platform_bytcr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * These GPIOs will turn on the USB2 PHY. Note that we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * put the gpio descriptors again here because the phy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * might want to grab them, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) gpiod_set_value_cansleep(gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) gpiod_put(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gpiod_set_value_cansleep(gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gpiod_put(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void dwc3_pci_resume_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct platform_device *dwc3 = dwc->dwc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = pm_runtime_get_sync(&dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pm_runtime_put_sync_autosuspend(&dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pm_runtime_mark_last_busy(&dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pm_runtime_put_sync_autosuspend(&dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct dwc3_pci *dwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct resource res[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct device *dev = &pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = pcim_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(dev, "failed to enable pci device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!dwc->dwc3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) res[0].start = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) res[0].end = pci_resource_end(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) res[0].name = "dwc_usb3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) res[0].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) res[1].start = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) res[1].name = "dwc_usb3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) res[1].flags = IORESOURCE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "couldn't add resources to dwc3 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dwc->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dwc->dwc3->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = dwc3_pci_quirks(dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = platform_device_add(dwc->dwc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_err(dev, "failed to register dwc3 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) device_init_wakeup(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pci_set_drvdata(pci, dwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) device_remove_software_node(&dwc->dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) platform_device_put(dwc->dwc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void dwc3_pci_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct dwc3_pci *dwc = pci_get_drvdata(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct pci_dev *pdev = dwc->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gpiod_remove_lookup_table(&platform_bytcr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) cancel_work_sync(&dwc->wakeup_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) device_init_wakeup(&pci->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pm_runtime_get(&pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) device_remove_software_node(&dwc->dwc3->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) platform_device_unregister(dwc->dwc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct pci_device_id dwc3_pci_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (kernel_ulong_t) &dwc3_pci_intel_swnode },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (kernel_ulong_t) &dwc3_pci_intel_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (kernel_ulong_t) &dwc3_pci_amd_swnode, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { } /* Terminating Entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) union acpi_object tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!dwc->has_dsm_for_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tmp.type = ACPI_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tmp.integer.value = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!obj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ACPI_FREE(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int dwc3_pci_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct dwc3_pci *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (device_can_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int dwc3_pci_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct dwc3_pci *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) queue_work(pm_wq, &dwc->wakeup_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int dwc3_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct dwc3_pci *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int dwc3_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct dwc3_pci *dwc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct pci_driver dwc3_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "dwc3-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .id_table = dwc3_pci_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .probe = dwc3_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .remove = dwc3_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .pm = &dwc3_pci_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) module_pci_driver(dwc3_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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