^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dwc3-omap.c - OMAP Specific Glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Felipe Balbi <balbi@ti.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/extcon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * All these registers belong to OMAP's Wrapper around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * DesignWare USB3 Core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USBOTGSS_REVISION 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USBOTGSS_SYSCONFIG 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USBOTGSS_IRQ_EOI 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USBOTGSS_EOI_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USBOTGSS_IRQSTATUS_0 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USBOTGSS_IRQENABLE_SET_0 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBOTGSS_IRQENABLE_CLR_0 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBOTGSS_IRQ0_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USBOTGSS_IRQSTATUS_1 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USBOTGSS_IRQENABLE_SET_1 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USBOTGSS_IRQENABLE_CLR_1 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBOTGSS_IRQSTATUS_2 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USBOTGSS_IRQENABLE_SET_2 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USBOTGSS_IRQENABLE_CLR_2 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USBOTGSS_IRQSTATUS_3 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USBOTGSS_IRQENABLE_SET_3 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USBOTGSS_IRQENABLE_CLR_3 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USBOTGSS_IRQSTATUS_MISC 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USBOTGSS_IRQMISC_OFFSET 0x03fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USBOTGSS_UTMI_OTG_STATUS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USBOTGSS_UTMI_OTG_CTRL 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USBOTGSS_TXFIFO_DEPTH 0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USBOTGSS_RXFIFO_DEPTH 0x050c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USBOTGSS_MMRAM_OFFSET 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USBOTGSS_FLADJ 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USBOTGSS_DEBUG_CFG 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USBOTGSS_DEBUG_DATA 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USBOTGSS_DEV_EBC_EN 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USBOTGSS_DEBUG_OFFSET 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* SYSCONFIG REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USBOTGSS_SYSCONFIG_DMADISABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* IRQ_EOI REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USBOTGSS_IRQ_EOI_LINE_NUMBER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* IRQS0 BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USBOTGSS_IRQO_COREIRQ_ST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* IRQMISC BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USBOTGSS_IRQMISC_DMADISABLECLR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USBOTGSS_IRQMISC_OEVT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define USBOTGSS_IRQMISC_DRVVBUS_RISE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define USBOTGSS_IRQMISC_CHRGVBUS_RISE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USBOTGSS_IRQMISC_IDPULLUP_RISE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define USBOTGSS_IRQMISC_DRVVBUS_FALL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define USBOTGSS_IRQMISC_CHRGVBUS_FALL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define USBOTGSS_IRQMISC_IDPULLUP_FALL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* UTMI_OTG_STATUS REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define USBOTGSS_UTMI_OTG_STATUS_DRVVBUS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define USBOTGSS_UTMI_OTG_STATUS_IDPULLUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* UTMI_OTG_CTRL REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USBOTGSS_UTMI_OTG_CTRL_SW_MODE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define USBOTGSS_UTMI_OTG_CTRL_IDDIG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum dwc3_omap_utmi_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DWC3_OMAP_UTMI_MODE_HW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DWC3_OMAP_UTMI_MODE_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct dwc3_omap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 utmi_otg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 utmi_otg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 irqmisc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 irq_eoi_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 debug_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 irq0_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct notifier_block vbus_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct notifier_block id_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator *vbus_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum omap_dwc3_vbus_id_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OMAP_DWC3_ID_FLOAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OMAP_DWC3_ID_GROUND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) OMAP_DWC3_VBUS_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) OMAP_DWC3_VBUS_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(value, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u32 dwc3_omap_read_utmi_ctrl(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) omap->utmi_otg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void dwc3_omap_write_utmi_ctrl(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) omap->utmi_otg_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) omap->irq0_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) omap->irq0_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_RAW_MISC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) omap->irqmisc_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) omap->irqmisc_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) omap->irqmisc_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) omap->irq0_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) omap->irqmisc_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) omap->irq0_offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum omap_dwc3_vbus_id_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case OMAP_DWC3_ID_GROUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (omap->vbus_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = regulator_enable(omap->vbus_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(omap->dev, "regulator enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val &= ~USBOTGSS_UTMI_OTG_CTRL_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dwc3_omap_write_utmi_ctrl(omap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case OMAP_DWC3_VBUS_VALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val &= ~USBOTGSS_UTMI_OTG_CTRL_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val |= USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) | USBOTGSS_UTMI_OTG_CTRL_SESSVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dwc3_omap_write_utmi_ctrl(omap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case OMAP_DWC3_ID_FLOAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (omap->vbus_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regulator_disable(omap->vbus_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dwc3_omap_write_utmi_ctrl(omap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case OMAP_DWC3_VBUS_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val &= ~(USBOTGSS_UTMI_OTG_CTRL_SESSVALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) | USBOTGSS_UTMI_OTG_CTRL_VBUSVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val |= USBOTGSS_UTMI_OTG_CTRL_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dwc3_omap_write_utmi_ctrl(omap, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_WARN(omap->dev, "invalid state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void dwc3_omap_enable_irqs(struct dwc3_omap *omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void dwc3_omap_disable_irqs(struct dwc3_omap *omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct dwc3_omap *omap = _omap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (dwc3_omap_read_irqmisc_status(omap) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dwc3_omap_read_irq0_status(omap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* mask irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dwc3_omap_disable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static irqreturn_t dwc3_omap_interrupt_thread(int irq, void *_omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dwc3_omap *omap = _omap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* clear irq status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) reg = dwc3_omap_read_irqmisc_status(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dwc3_omap_write_irqmisc_status(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reg = dwc3_omap_read_irq0_status(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dwc3_omap_write_irq0_status(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* unmask irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dwc3_omap_enable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* enable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg = USBOTGSS_IRQO_COREIRQ_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dwc3_omap_write_irq0_set(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reg = (USBOTGSS_IRQMISC_OEVT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) USBOTGSS_IRQMISC_DRVVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) USBOTGSS_IRQMISC_CHRGVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) USBOTGSS_IRQMISC_IDPULLUP_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) USBOTGSS_IRQMISC_DRVVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) USBOTGSS_IRQMISC_CHRGVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) USBOTGSS_IRQMISC_IDPULLUP_FALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dwc3_omap_write_irqmisc_set(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* disable all IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg = USBOTGSS_IRQO_COREIRQ_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dwc3_omap_write_irq0_clr(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) reg = (USBOTGSS_IRQMISC_OEVT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) USBOTGSS_IRQMISC_DRVVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) USBOTGSS_IRQMISC_CHRGVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) USBOTGSS_IRQMISC_IDPULLUP_RISE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) USBOTGSS_IRQMISC_DRVVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) USBOTGSS_IRQMISC_CHRGVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) USBOTGSS_IRQMISC_IDPULLUP_FALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dwc3_omap_write_irqmisc_clr(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int dwc3_omap_id_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void dwc3_omap_map_offset(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_node *node = omap->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Differentiate between OMAP5 and AM437x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * though there are changes in wrapper register offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Using dt compatible to differentiate AM437x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct device_node *node = omap->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 utmi_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) reg = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) of_property_read_u32(node, "utmi-mode", &utmi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) switch (utmi_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case DWC3_OMAP_UTMI_MODE_SW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case DWC3_OMAP_UTMI_MODE_HW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_WARN(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dwc3_omap_write_utmi_ctrl(omap, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct device_node *node = omap->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct extcon_dev *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (of_property_read_bool(node, "extcon")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) edev = extcon_get_edev_by_phandle(omap->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(edev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_vdbg(omap->dev, "couldn't get extcon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = devm_extcon_register_notifier(omap->dev, edev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) EXTCON_USB, &omap->vbus_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_vdbg(omap->dev, "failed to register notifier for USB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) omap->id_nb.notifier_call = dwc3_omap_id_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = devm_extcon_register_notifier(omap->dev, edev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) EXTCON_USB_HOST, &omap->id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (extcon_get_state(edev, EXTCON_USB) == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (extcon_get_state(edev, EXTCON_USB_HOST) == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) omap->edev = edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int dwc3_omap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct dwc3_omap *omap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct regulator *vbus_reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(dev, "device node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) platform_set_drvdata(pdev, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (of_property_read_bool(node, "vbus-supply")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) vbus_reg = devm_regulator_get(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(vbus_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(dev, "vbus init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return PTR_ERR(vbus_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) omap->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) omap->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) omap->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) omap->vbus_reg = vbus_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(dev, "get_sync failed with err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dwc3_omap_map_offset(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dwc3_omap_set_utmi_mode(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = dwc3_omap_extcon_register(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = of_platform_populate(node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(&pdev->dev, "failed to create dwc3 core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = devm_request_threaded_irq(dev, omap->irq, dwc3_omap_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dwc3_omap_interrupt_thread, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "dwc3-omap", omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "failed to request IRQ #%d --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) omap->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dwc3_omap_enable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int dwc3_omap_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct dwc3_omap *omap = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dwc3_omap_disable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) disable_irq(omap->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) of_platform_depopulate(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct of_device_id of_dwc3_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .compatible = "ti,dwc3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .compatible = "ti,am437x-dwc3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MODULE_DEVICE_TABLE(of, of_dwc3_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int dwc3_omap_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct dwc3_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) omap->utmi_otg_ctrl = dwc3_omap_read_utmi_ctrl(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dwc3_omap_disable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int dwc3_omap_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct dwc3_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dwc3_omap_write_utmi_ctrl(omap, omap->utmi_otg_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dwc3_omap_enable_irqs(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void dwc3_omap_complete(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct dwc3_omap *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (extcon_get_state(omap->edev, EXTCON_USB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .complete = dwc3_omap_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct platform_driver dwc3_omap_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .probe = dwc3_omap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .remove = dwc3_omap_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .name = "omap-dwc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .of_match_table = of_dwc3_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .pm = DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) module_platform_driver(dwc3_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MODULE_ALIAS("platform:omap-dwc3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags