^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dwc3-exynos.c - Samsung Exynos DWC3 Specific Glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DWC3_EXYNOS_MAX_CLOCKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct dwc3_exynos_driverdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) const char *clk_names[DWC3_EXYNOS_MAX_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int suspend_clk_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct dwc3_exynos {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char **clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *clks[DWC3_EXYNOS_MAX_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int suspend_clk_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regulator *vdd33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regulator *vdd10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int dwc3_exynos_remove_child(struct device *dev, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) platform_device_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int dwc3_exynos_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dwc3_exynos *exynos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const struct dwc3_exynos_driverdata *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!exynos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) driver_data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) exynos->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) exynos->num_clks = driver_data->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) exynos->clk_names = (const char **)driver_data->clk_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) exynos->suspend_clk_idx = driver_data->suspend_clk_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) platform_set_drvdata(pdev, exynos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (i = 0; i < exynos->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) exynos->clks[i] = devm_clk_get(dev, exynos->clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (IS_ERR(exynos->clks[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(dev, "failed to get clock: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) exynos->clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return PTR_ERR(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (i = 0; i < exynos->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = clk_prepare_enable(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) while (i-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) clk_disable_unprepare(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (exynos->suspend_clk_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_prepare_enable(exynos->clks[exynos->suspend_clk_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) exynos->vdd33 = devm_regulator_get(dev, "vdd33");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (IS_ERR(exynos->vdd33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = PTR_ERR(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto vdd33_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = regulator_enable(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dev_err(dev, "Failed to enable VDD33 supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto vdd33_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) exynos->vdd10 = devm_regulator_get(dev, "vdd10");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (IS_ERR(exynos->vdd10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = PTR_ERR(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto vdd10_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regulator_enable(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dev, "Failed to enable VDD10 supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto vdd10_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = of_platform_populate(node, NULL, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_err(dev, "failed to add dwc3 core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto populate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(dev, "no device node, failed to add dwc3 core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto populate_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) populate_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regulator_disable(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vdd10_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regulator_disable(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) vdd33_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = exynos->num_clks - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) clk_disable_unprepare(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (exynos->suspend_clk_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int dwc3_exynos_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = exynos->num_clks - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_disable_unprepare(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (exynos->suspend_clk_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) regulator_disable(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) regulator_disable(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct dwc3_exynos_driverdata exynos5250_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .clk_names = { "usbdrd30" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .num_clks = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .suspend_clk_idx = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct dwc3_exynos_driverdata exynos5433_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .num_clks = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .suspend_clk_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct dwc3_exynos_driverdata exynos7_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .clk_names = { "usbdrd30", "usbdrd30_susp_clk", "usbdrd30_axius_clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .num_clks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .suspend_clk_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id exynos_dwc3_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .compatible = "samsung,exynos5250-dwusb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .data = &exynos5250_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .compatible = "samsung,exynos5433-dwusb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .data = &exynos5433_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .compatible = "samsung,exynos7-dwusb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .data = &exynos7_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(of, exynos_dwc3_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int dwc3_exynos_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct dwc3_exynos *exynos = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = exynos->num_clks - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_disable_unprepare(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) regulator_disable(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) regulator_disable(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int dwc3_exynos_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dwc3_exynos *exynos = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = regulator_enable(exynos->vdd33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(dev, "Failed to enable VDD33 supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = regulator_enable(exynos->vdd10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "Failed to enable VDD10 supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 0; i < exynos->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = clk_prepare_enable(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) while (i-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk_disable_unprepare(exynos->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct dev_pm_ops dwc3_exynos_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SET_SYSTEM_SLEEP_PM_OPS(dwc3_exynos_suspend, dwc3_exynos_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DEV_PM_OPS (&dwc3_exynos_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct platform_driver dwc3_exynos_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .probe = dwc3_exynos_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .remove = dwc3_exynos_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "exynos-dwc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .of_match_table = exynos_dwc3_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pm = DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) module_platform_driver(dwc3_exynos_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_AUTHOR("Anton Tikhomirov <av.tikhomirov@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DESCRIPTION("DesignWare USB3 Exynos Glue Layer");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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