^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004-2016 Synopsys, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 3. The names of the above-listed copyright holders may not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * to endorse or promote products derived from this software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Foundation; either version 2 of the License, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) p->host_rx_fifo_size = 774;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) p->max_transfer_size = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) p->max_packet_count = 511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) p->ahbcfg = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) p->speed = DWC2_SPEED_PARAM_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) p->host_rx_fifo_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) p->host_nperio_tx_fifo_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) p->host_perio_tx_fifo_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) p->max_transfer_size = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) p->max_packet_count = 511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) p->host_channels = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) p->phy_utmi_width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) p->i2c_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) p->reload_ctl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) p->change_speed_quirk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) p->phy_utmi_width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) p->host_rx_fifo_size = 525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) p->host_nperio_tx_fifo_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) p->host_perio_tx_fifo_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) p->lpm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) p->g_dma_desc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) p->otg_cap = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) p->host_rx_fifo_size = 288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) p->host_nperio_tx_fifo_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) p->host_perio_tx_fifo_size = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) p->max_transfer_size = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) p->max_packet_count = 511;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) p->speed = DWC2_SPEED_PARAM_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) p->host_rx_fifo_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) p->host_nperio_tx_fifo_size = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) p->host_perio_tx_fifo_size = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) p->host_channels = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) p->lpm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) p->lpm_clock_gating = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) p->besl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) p->hird_threshold_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) p->speed = DWC2_SPEED_PARAM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) p->host_rx_fifo_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) p->host_nperio_tx_fifo_size = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) p->host_perio_tx_fifo_size = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) p->max_packet_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) p->i2c_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) p->activate_stm_fs_transceiver = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) p->host_rx_fifo_size = 622;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) p->host_nperio_tx_fifo_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) p->host_perio_tx_fifo_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) p->speed = DWC2_SPEED_PARAM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) p->host_rx_fifo_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) p->host_nperio_tx_fifo_size = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) p->host_perio_tx_fifo_size = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) p->max_packet_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) p->i2c_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) p->activate_stm_fs_transceiver = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) p->activate_stm_id_vb_detection = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) p->host_support_fs_ls_low_power = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) p->host_ls_low_power_phy_clk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) p->host_rx_fifo_size = 440;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) p->host_nperio_tx_fifo_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) p->host_perio_tx_fifo_size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) p->lpm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) p->lpm_clock_gating = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) p->besl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) p->hird_threshold_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct of_device_id dwc2_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .compatible = "snps,dwc2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .compatible = "samsung,s3c6400-hsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .data = dwc2_set_s3c6400_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .compatible = "amlogic,meson8-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .data = dwc2_set_amlogic_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .compatible = "amlogic,meson8b-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .data = dwc2_set_amlogic_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .compatible = "amlogic,meson-gxbb-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .data = dwc2_set_amlogic_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .compatible = "amlogic,meson-g12a-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .data = dwc2_set_amlogic_g12a_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .compatible = "st,stm32f4x9-fsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .data = dwc2_set_stm32f4x9_fsotg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { .compatible = "st,stm32f4x9-hsotg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .compatible = "st,stm32f7-hsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .data = dwc2_set_stm32f7_hsotg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .compatible = "st,stm32mp15-fsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .data = dwc2_set_stm32mp15_fsotg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .compatible = "st,stm32mp15-hsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .data = dwc2_set_stm32mp15_hsotg_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch (hsotg->hw_params.op_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) hsotg->params.otg_cap = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val = DWC2_PHY_TYPE_PARAM_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) val = DWC2_PHY_TYPE_PARAM_UTMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = DWC2_PHY_TYPE_PARAM_ULPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (dwc2_is_fs_iot(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hsotg->params.phy_type = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (dwc2_is_fs_iot(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) val = DWC2_SPEED_PARAM_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (dwc2_is_hs_iot(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) val = DWC2_SPEED_PARAM_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) hsotg->params.speed = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val = (hsotg->hw_params.utmi_phy_data_width ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (hsotg->phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * If using the generic PHY framework, check if the PHY bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * width is 8-bit and set the phyif appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (phy_get_bus_width(hsotg->phy) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hsotg->params.phy_utmi_width = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int depth_average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) for (i = 1; i <= fifo_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) p->g_tx_fifo_size[i] = depth_average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (hsotg->hw_params.hibernation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else if (hsotg->hw_params.power_optimized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val = DWC2_POWER_DOWN_PARAM_PARTIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hsotg->params.power_down = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) p->lpm = hsotg->hw_params.lpm_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (p->lpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) p->lpm_clock_gating = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) p->besl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) p->hird_threshold_en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) p->hird_threshold = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) p->lpm_clock_gating = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) p->besl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) p->hird_threshold_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * dwc2_set_default_params() - Set all core parameters to their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * auto-detected default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dwc2_set_param_otg_cap(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dwc2_set_param_phy_type(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dwc2_set_param_speed(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dwc2_set_param_phy_utmi_width(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dwc2_set_param_power_down(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dwc2_set_param_lpm(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) p->phy_ulpi_ddr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) p->phy_ulpi_ext_vbus = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) p->i2c_enable = hw->i2c_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) p->acg_enable = hw->acg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) p->ulpi_fs_ls = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) p->ts_dline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) p->uframe_sched = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) p->external_id_pin_ctl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) p->ipg_isoc_en = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) p->service_interval = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) p->max_packet_count = hw->max_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) p->max_transfer_size = hw->max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) p->ref_clk_per = 33333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) p->sof_cnt_wkup_alert = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) (hsotg->dr_mode == USB_DR_MODE_OTG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) p->host_dma = dma_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) p->dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) p->dma_desc_fs_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) p->host_support_fs_ls_low_power = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) p->host_ls_low_power_phy_clk = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) p->host_channels = hw->host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) p->host_rx_fifo_size = hw->rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (hsotg->dr_mode == USB_DR_MODE_OTG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) p->g_dma = dma_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) p->g_dma_desc = hw->dma_desc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * The values for g_rx_fifo_size (2048) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * g_np_tx_fifo_size (1024) come from the legacy s3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * gadget driver. These defaults have been hard-coded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * for some time so many platforms depend on these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * values. Leave them as defaults for now and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * auto-detect if the hardware does not support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) p->g_rx_fifo_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) p->g_np_tx_fifo_size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dwc2_set_param_tx_fifo_sizes(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * dwc2_get_device_properties() - Read in device properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Read in the device properties and adjust core parameters if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (hsotg->dr_mode == USB_DR_MODE_OTG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &p->g_rx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &p->g_np_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (num > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) num = min(num, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) memset(p->g_tx_fifo_size, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sizeof(p->g_tx_fifo_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) device_property_read_u32_array(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "g-tx-fifo-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &p->g_tx_fifo_size[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) p->oc_disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (hsotg->params.otg_cap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (hsotg->hw_params.op_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* always valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dwc2_set_param_otg_cap(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 hs_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 fs_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hs_phy_type = hsotg->hw_params.hs_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fs_phy_type = hsotg->hw_params.fs_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (hsotg->params.phy_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case DWC2_PHY_TYPE_PARAM_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case DWC2_PHY_TYPE_PARAM_UTMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case DWC2_PHY_TYPE_PARAM_ULPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dwc2_set_param_phy_type(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int phy_type = hsotg->params.phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int speed = hsotg->params.speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case DWC2_SPEED_PARAM_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) (phy_type == DWC2_PHY_TYPE_PARAM_FS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case DWC2_SPEED_PARAM_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case DWC2_SPEED_PARAM_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dwc2_set_param_speed(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int param = hsotg->params.phy_utmi_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int width = hsotg->hw_params.utmi_phy_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) valid = (param == 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) valid = (param == 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) valid = (param == 8 || param == 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dwc2_set_param_phy_utmi_width(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int param = hsotg->params.power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case DWC2_POWER_DOWN_PARAM_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case DWC2_POWER_DOWN_PARAM_PARTIAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (hsotg->hw_params.power_optimized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "Partial power down isn't supported by HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) param = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case DWC2_POWER_DOWN_PARAM_HIBERNATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (hsotg->hw_params.hibernation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "Hibernation isn't supported by HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) param = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "%s: Invalid parameter power_down=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) __func__, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) param = DWC2_POWER_DOWN_PARAM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hsotg->params.power_down = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 dptxfszn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (fifo = 1; fifo <= fifo_count; fifo++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) total += hsotg->params.g_tx_fifo_size[fifo];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dwc2_set_param_tx_fifo_sizes(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (fifo = 1; fifo <= fifo_count; fifo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (hsotg->params.g_tx_fifo_size[fifo] < min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) __func__, fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) hsotg->params.g_tx_fifo_size[fifo]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define CHECK_RANGE(_param, _min, _max, _def) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((int)(hsotg->params._param) < (_min) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (hsotg->params._param) > (_max)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __func__, #_param, hsotg->params._param); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) hsotg->params._param = (_def); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define CHECK_BOOL(_param, _check) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (hsotg->params._param && !(_check)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __func__, #_param, hsotg->params._param); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hsotg->params._param = false; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static void dwc2_check_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct dwc2_core_params *p = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dwc2_check_param_otg_cap(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dwc2_check_param_phy_type(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dwc2_check_param_speed(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dwc2_check_param_phy_utmi_width(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dwc2_check_param_power_down(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CHECK_BOOL(i2c_enable, hw->i2c_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CHECK_BOOL(acg_enable, hw->acg_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CHECK_BOOL(lpm, hw->lpm_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CHECK_BOOL(besl, hsotg->params.lpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CHECK_BOOL(service_interval, hw->service_interval_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) CHECK_RANGE(max_packet_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 15, hw->max_packet_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) hw->max_packet_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) CHECK_RANGE(max_transfer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 2047, hw->max_transfer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) hw->max_transfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) (hsotg->dr_mode == USB_DR_MODE_OTG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) CHECK_BOOL(host_dma, dma_capable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) CHECK_BOOL(dma_desc_enable, p->host_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) CHECK_BOOL(host_ls_low_power_phy_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) CHECK_RANGE(host_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 1, hw->host_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hw->host_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) CHECK_RANGE(host_rx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 16, hw->rx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hw->rx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) CHECK_RANGE(host_nperio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 16, hw->host_nperio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hw->host_nperio_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CHECK_RANGE(host_perio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 16, hw->host_perio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hw->host_perio_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (hsotg->dr_mode == USB_DR_MODE_OTG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) CHECK_BOOL(g_dma, dma_capable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) CHECK_RANGE(g_rx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 16, hw->rx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) hw->rx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CHECK_RANGE(g_np_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 16, hw->dev_nperio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) hw->dev_nperio_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dwc2_check_param_tx_fifo_sizes(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * Gets host hardware parameters. Forces host mode if not currently in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * host mode. Should be called immediately after a core soft reset in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * order to get the reset values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 gnptxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 hptxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dwc2_force_mode(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) FIFOSIZE_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) FIFOSIZE_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * Gets device hardware parameters. Forces device mode if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * currently in device mode. Should be called immediately after a core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * soft reset in order to get the reset values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 gnptxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int fifo, fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (hsotg->dr_mode == USB_DR_MODE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dwc2_force_mode(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) for (fifo = 1; fifo <= fifo_count; fifo++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hw->g_tx_fifo_size[fifo] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) FIFOSIZE_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * During device initialization, read various hardware configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * registers and interpret the contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 grxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* hwcfg1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) hw->dev_ep_dirs = hwcfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* hwcfg2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GHWCFG2_OP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GHWCFG2_ARCHITECTURE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GHWCFG2_NUM_HOST_CHAN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GHWCFG2_HS_PHY_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GHWCFG2_FS_PHY_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GHWCFG2_NUM_DEV_EP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) hw->nperio_tx_q_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hw->host_perio_tx_q_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hw->dev_token_q_depth =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* hwcfg3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) hw->max_transfer_size = (1 << (width + 11)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) hw->max_packet_count = (1 << (width + 4)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GHWCFG3_DFIFO_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* hwcfg4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GHWCFG4_NUM_IN_EPS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) hw->service_interval_mode = !!(hwcfg4 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* fifo sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) GRXFSIZ_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Host specific hardware parameters. Reading these parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * requires the controller to be in host mode. The mode will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * be forced, if necessary, to read these values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dwc2_get_host_hwparams(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dwc2_get_dev_hwparams(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int dwc2_init_params(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) void (*set_params)(struct dwc2_hsotg *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dwc2_set_default_params(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dwc2_get_device_properties(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) match = of_match_device(dwc2_of_match_table, hsotg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (match && match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) set_params = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) set_params(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dwc2_check_params(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags