^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hw.h - DesignWare HS OTG Controller hardware definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2004-2013 Synopsys, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 3. The names of the above-listed copyright holders may not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to endorse or promote products derived from this software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Foundation; either version 2 of the License, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef __DWC2_HW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define __DWC2_HW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HSOTG_REG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GOTGCTL HSOTG_REG(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GOTGCTL_CHIRPEN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GOTGCTL_MULT_VALID_BC_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GOTGCTL_OTGVER BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GOTGCTL_BSESVLD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GOTGCTL_ASESVLD BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GOTGCTL_DBNC_SHORT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GOTGCTL_CONID_B BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GOTGCTL_DEVHNPEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GOTGCTL_HSTSETHNPEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GOTGCTL_HNPREQ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GOTGCTL_HSTNEGSCS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GOTGCTL_BVALOVAL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GOTGCTL_BVALOEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GOTGCTL_AVALOVAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GOTGCTL_AVALOEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GOTGCTL_VBVALOVAL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GOTGCTL_VBVALOEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GOTGCTL_SESREQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GOTGCTL_SESREQSCS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GOTGINT HSOTG_REG(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GOTGINT_DBNCE_DONE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GOTGINT_HST_NEG_DET BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GOTGINT_SES_END_DET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GAHBCFG HSOTG_REG(0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GAHBCFG_AHB_SINGLE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GAHBCFG_REM_MEM_SUPP BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GAHBCFG_DMA_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GAHBCFG_HBSTLEN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GAHBCFG_HBSTLEN_SINGLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GAHBCFG_HBSTLEN_INCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GAHBCFG_HBSTLEN_INCR4 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GAHBCFG_HBSTLEN_INCR8 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GAHBCFG_HBSTLEN_INCR16 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GAHBCFG_GLBL_INTR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GAHBCFG_NP_TXF_EMP_LVL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GAHBCFG_DMA_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GAHBCFG_GLBL_INTR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GUSBCFG HSOTG_REG(0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GUSBCFG_FORCEDEVMODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GUSBCFG_FORCEHOSTMODE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GUSBCFG_TXENDDELAY BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GUSBCFG_ICUSBCAP BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GUSBCFG_TERMSELDLPULSE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GUSBCFG_ULPI_AUTO_RES BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GUSBCFG_ULPI_FS_LS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GUSBCFG_USBTRDTIM_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GUSBCFG_HNPCAP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GUSBCFG_SRPCAP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GUSBCFG_DDRSEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GUSBCFG_PHYSEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GUSBCFG_FSINTF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GUSBCFG_PHYIF16 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GUSBCFG_PHYIF8 (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GUSBCFG_TOUTCAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GUSBCFG_TOUTCAL_LIMIT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GRSTCTL HSOTG_REG(0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GRSTCTL_AHBIDLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GRSTCTL_DMAREQ BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GRSTCTL_CSFTRST_DONE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GRSTCTL_TXFNUM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GRSTCTL_TXFNUM_LIMIT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GRSTCTL_TXFFLSH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GRSTCTL_RXFFLSH BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GRSTCTL_FRMCNTRRST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GRSTCTL_HSFTRST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GRSTCTL_CSFTRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GINTSTS HSOTG_REG(0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GINTMSK HSOTG_REG(0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GINTSTS_WKUPINT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GINTSTS_SESSREQINT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GINTSTS_DISCONNINT BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GINTSTS_CONIDSTSCHNG BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GINTSTS_LPMTRANRCVD BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GINTSTS_PTXFEMP BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GINTSTS_HCHINT BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GINTSTS_PRTINT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GINTSTS_RESETDET BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GINTSTS_FET_SUSP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GINTSTS_INCOMPL_IP BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GINTSTS_INCOMPL_SOOUT BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GINTSTS_INCOMPL_SOIN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GINTSTS_OEPINT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GINTSTS_IEPINT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GINTSTS_EPMIS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GINTSTS_RESTOREDONE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GINTSTS_EOPF BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GINTSTS_ISOUTDROP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GINTSTS_ENUMDONE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GINTSTS_USBRST BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GINTSTS_USBSUSP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GINTSTS_ERLYSUSP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GINTSTS_I2CINT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GINTSTS_ULPI_CK_INT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GINTSTS_GOUTNAKEFF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GINTSTS_GINNAKEFF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GINTSTS_NPTXFEMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GINTSTS_RXFLVL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GINTSTS_SOF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GINTSTS_OTGINT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GINTSTS_MODEMIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GINTSTS_CURMODE_HOST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GRXSTSR HSOTG_REG(0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GRXSTSP HSOTG_REG(0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GRXSTS_FN_MASK (0x7f << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GRXSTS_FN_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GRXSTS_PKTSTS_MASK (0xf << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GRXSTS_PKTSTS_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GRXSTS_PKTSTS_GLOBALOUTNAK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GRXSTS_PKTSTS_OUTRX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GRXSTS_PKTSTS_HCHIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GRXSTS_PKTSTS_OUTDONE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GRXSTS_PKTSTS_SETUPDONE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GRXSTS_PKTSTS_DATATOGGLEERR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GRXSTS_PKTSTS_SETUPRX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GRXSTS_PKTSTS_HCHHALTED 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GRXSTS_HCHNUM_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GRXSTS_HCHNUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GRXSTS_DPID_MASK (0x3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GRXSTS_DPID_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GRXSTS_BYTECNT_MASK (0x7ff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GRXSTS_BYTECNT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GRXSTS_EPNUM_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GRXSTS_EPNUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GRXFSIZ HSOTG_REG(0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GRXFSIZ_DEPTH_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GRXFSIZ_DEPTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GNPTXFSIZ HSOTG_REG(0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Use FIFOSIZE_* constants to access this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GNPTXSTS HSOTG_REG(0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GI2CCTL HSOTG_REG(0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GI2CCTL_BSYDNE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GI2CCTL_RW BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GI2CCTL_I2CDATSE0 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GI2CCTL_I2CDEVADDR_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GI2CCTL_I2CSUSPCTL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GI2CCTL_ACK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GI2CCTL_I2CEN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GI2CCTL_ADDR_MASK (0x7f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GI2CCTL_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GI2CCTL_REGADDR_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GI2CCTL_REGADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GI2CCTL_RWDATA_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GI2CCTL_RWDATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GPVNDCTL HSOTG_REG(0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GGPIO HSOTG_REG(0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GUID HSOTG_REG(0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GSNPSID HSOTG_REG(0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GHWCFG1 HSOTG_REG(0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GSNPSID_ID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GHWCFG2 HSOTG_REG(0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define GHWCFG2_MULTI_PROC_INT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define GHWCFG2_DYNAMIC_FIFO BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define GHWCFG2_NUM_DEV_EP_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GHWCFG2_FS_PHY_TYPE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define GHWCFG2_HS_PHY_TYPE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define GHWCFG2_HS_PHY_TYPE_UTMI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define GHWCFG2_HS_PHY_TYPE_ULPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define GHWCFG2_POINT2POINT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define GHWCFG2_ARCHITECTURE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define GHWCFG2_SLAVE_ONLY_ARCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GHWCFG2_EXT_DMA_ARCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GHWCFG2_INT_DMA_ARCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GHWCFG2_OP_MODE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GHWCFG2_OP_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GHWCFG2_OP_MODE_UNDEFINED 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define GHWCFG3 HSOTG_REG(0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GHWCFG3_OTG_LPM_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GHWCFG3_BC_SUPPORT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define GHWCFG3_ADP_SUPP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GHWCFG3_I2C BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GHWCFG3_OTG_FUNC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define GHWCFG4 HSOTG_REG(0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GHWCFG4_DESC_DMA_DYN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GHWCFG4_DESC_DMA BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GHWCFG4_NUM_IN_EPS_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GHWCFG4_DED_FIFO_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GHWCFG4_DED_FIFO_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GHWCFG4_B_VALID_FILT_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define GHWCFG4_A_VALID_FILT_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GHWCFG4_IDDIG_FILT_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define GHWCFG4_ACG_SUPPORTED BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define GHWCFG4_XHIBER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define GHWCFG4_HIBER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define GHWCFG4_MIN_AHB_FREQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define GHWCFG4_POWER_OPTIMIZ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define GLPMCFG HSOTG_REG(0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define GLPMCFG_INVSELHSIC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define GLPMCFG_HSICCON BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GLPMCFG_RSTRSLPSTS BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GLPMCFG_ENBESL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define GLPMCFG_SNDLPM BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GLPMCFG_RETRY_CNT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define GLPMCFG_L1RESUMEOK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GLPMCFG_SLPSTS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define GLPMCFG_COREL1RES_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GLPMCFG_HIRD_THRES_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define GLPMCFG_ENBLSLPM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define GLPMCFG_BREMOTEWAKE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define GLPMCFG_HIRD_MASK (0xf << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define GLPMCFG_HIRD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define GLPMCFG_APPL1RES BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define GLPMCFG_LPMCAP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define GPWRDN HSOTG_REG(0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define GPWRDN_ADP_INT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define GPWRDN_BSESSVLD BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define GPWRDN_IDSTS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define GPWRDN_LINESTATE_MASK (0x3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define GPWRDN_LINESTATE_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define GPWRDN_STS_CHGINT_MSK BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define GPWRDN_STS_CHGINT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define GPWRDN_SRP_DET_MSK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define GPWRDN_SRP_DET BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define GPWRDN_CONNECT_DET_MSK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define GPWRDN_CONNECT_DET BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define GPWRDN_DISCONN_DET_MSK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define GPWRDN_DISCONN_DET BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define GPWRDN_RST_DET_MSK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define GPWRDN_RST_DET BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define GPWRDN_LNSTSCHG_MSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define GPWRDN_LNSTSCHG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define GPWRDN_DIS_VBUS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define GPWRDN_PWRDNSWTCH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define GPWRDN_PWRDNRSTN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define GPWRDN_PWRDNCLMP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define GPWRDN_RESTORE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define GPWRDN_PMUACTV BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define GPWRDN_PMUINTSEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define GDFIFOCFG HSOTG_REG(0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define GDFIFOCFG_EPINFOBASE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define GDFIFOCFG_GDFIFOCFG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define ADPCTL HSOTG_REG(0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define ADPCTL_AR_MASK (0x3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define ADPCTL_AR_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define ADPCTL_ADP_TMOUT_INT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ADPCTL_ADP_SNS_INT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ADPCTL_ADP_PRB_INT BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ADPCTL_ADPENA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define ADPCTL_ADPRES BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ADPCTL_ENASNS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define ADPCTL_ENAPRB BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define ADPCTL_RTIM_MASK (0x7ff << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define ADPCTL_RTIM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define ADPCTL_PRB_PER_MASK (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ADPCTL_PRB_PER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define ADPCTL_PRB_DELTA_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define ADPCTL_PRB_DSCHRG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define GREFCLK HSOTG_REG(0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define GREFCLK_REFCLKPER_MASK (0x1ffff << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define GREFCLK_REFCLKPER_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define GREFCLK_REF_CLK_MODE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define GINTMSK2 HSOTG_REG(0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define GINTSTS2 HSOTG_REG(0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define GINTSTS2_WKUP_ALERT_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define HPTXFSIZ HSOTG_REG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Use FIFOSIZE_* constants to access this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* Use FIFOSIZE_* constants to access this register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define FIFOSIZE_DEPTH_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define FIFOSIZE_DEPTH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define FIFOSIZE_STARTADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Device mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DCFG HSOTG_REG(0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DCFG_DESCDMA_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define DCFG_EPMISCNT_MASK (0x1f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DCFG_EPMISCNT_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DCFG_EPMISCNT_LIMIT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DCFG_EPMISCNT(_x) ((_x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DCFG_IPG_ISOC_SUPPORDED BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DCFG_PERFRINT_MASK (0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DCFG_PERFRINT_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DCFG_PERFRINT_LIMIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define DCFG_PERFRINT(_x) ((_x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DCFG_DEVADDR_MASK (0x7f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DCFG_DEVADDR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define DCFG_DEVADDR_LIMIT 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DCFG_DEVADDR(_x) ((_x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DCFG_NZ_STS_OUT_HSHK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define DCFG_DEVSPD_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define DCFG_DEVSPD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define DCFG_DEVSPD_HS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define DCFG_DEVSPD_FS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define DCFG_DEVSPD_LS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define DCFG_DEVSPD_FS48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define DCTL HSOTG_REG(0x804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define DCTL_PWRONPRGDONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define DCTL_CGOUTNAK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define DCTL_SGOUTNAK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DCTL_CGNPINNAK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DCTL_SGNPINNAK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DCTL_TSTCTL_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DCTL_TSTCTL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DCTL_GOUTNAKSTS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DCTL_GNPINNAKSTS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DCTL_SFTDISCON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DCTL_RMTWKUPSIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DSTS HSOTG_REG(0x808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DSTS_SOFFN_MASK (0x3fff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DSTS_SOFFN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DSTS_SOFFN_LIMIT 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DSTS_SOFFN(_x) ((_x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DSTS_ERRATICERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DSTS_ENUMSPD_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DSTS_ENUMSPD_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DSTS_ENUMSPD_HS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DSTS_ENUMSPD_FS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DSTS_ENUMSPD_LS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DSTS_ENUMSPD_FS48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DSTS_SUSPSTS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DIEPMSK HSOTG_REG(0x810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DIEPMSK_NAKMSK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DIEPMSK_BNAININTRMSK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DIEPMSK_TXFIFOEMPTY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define DIEPMSK_INEPNAKEFFMSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DIEPMSK_INTKNEPMISMSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DIEPMSK_TIMEOUTMSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DIEPMSK_AHBERRMSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DIEPMSK_EPDISBLDMSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DIEPMSK_XFERCOMPLMSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DOEPMSK HSOTG_REG(0x814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DOEPMSK_BNAMSK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DOEPMSK_BACK2BACKSETUP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DOEPMSK_STSPHSERCVDMSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DOEPMSK_SETUPMSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DOEPMSK_AHBERRMSK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DOEPMSK_EPDISBLDMSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define DOEPMSK_XFERCOMPLMSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DAINT HSOTG_REG(0x818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DAINTMSK HSOTG_REG(0x81C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define DAINT_OUTEP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DAINT_OUTEP(_x) (1 << ((_x) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DAINT_INEP(_x) (1 << (_x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DTKNQR1 HSOTG_REG(0x820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DTKNQR2 HSOTG_REG(0x824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DTKNQR3 HSOTG_REG(0x830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DTKNQR4 HSOTG_REG(0x834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define DIEPEMPMSK HSOTG_REG(0x834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define DVBUSDIS HSOTG_REG(0x828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DVBUSPULSE HSOTG_REG(0x82C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DIEPCTL0 HSOTG_REG(0x900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DOEPCTL0 HSOTG_REG(0xB00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* EP0 specialness:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * bits[29..28] - reserved (no SetD0PID, SetD1PID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * bits[25..22] - should always be zero, this isn't a periodic endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * bits[10..0] - MPS setting different for EP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define D0EPCTL_MPS_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define D0EPCTL_MPS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define D0EPCTL_MPS_64 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define D0EPCTL_MPS_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define D0EPCTL_MPS_16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define D0EPCTL_MPS_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DXEPCTL_EPENA BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DXEPCTL_EPDIS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DXEPCTL_SETD1PID BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DXEPCTL_SETODDFR BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DXEPCTL_SETD0PID BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define DXEPCTL_SETEVENFR BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DXEPCTL_SNAK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DXEPCTL_CNAK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define DXEPCTL_TXFNUM_MASK (0xf << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define DXEPCTL_TXFNUM_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define DXEPCTL_TXFNUM_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DXEPCTL_STALL BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define DXEPCTL_SNP BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define DXEPCTL_NAKSTS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define DXEPCTL_DPID BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define DXEPCTL_EOFRNUM BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define DXEPCTL_USBACTEP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DXEPCTL_NEXTEP_MASK (0xf << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DXEPCTL_NEXTEP_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define DXEPCTL_NEXTEP_LIMIT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define DXEPCTL_NEXTEP(_x) ((_x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define DXEPCTL_MPS_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define DXEPCTL_MPS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define DXEPCTL_MPS_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define DXEPCTL_MPS(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define DXEPINT_SETUP_RCVD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define DXEPINT_NYETINTRPT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define DXEPINT_NAKINTRPT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define DXEPINT_BBLEERRINTRPT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define DXEPINT_PKTDRPSTS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define DXEPINT_BNAINTR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define DXEPINT_TXFIFOUNDRN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define DXEPINT_OUTPKTERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define DXEPINT_TXFEMP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define DXEPINT_INEPNAKEFF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define DXEPINT_BACK2BACKSETUP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define DXEPINT_INTKNEPMIS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define DXEPINT_STSPHSERCVD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define DXEPINT_INTKNTXFEMP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define DXEPINT_OUTTKNEPDIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define DXEPINT_TIMEOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define DXEPINT_SETUP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DXEPINT_AHBERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define DXEPINT_EPDISBLD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define DXEPINT_XFERCOMPL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define DIEPTSIZ0 HSOTG_REG(0x910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define DIEPTSIZ0_PKTCNT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define DIEPTSIZ0_XFERSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define DOEPTSIZ0 HSOTG_REG(0xB10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DOEPTSIZ0_SUPCNT_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DOEPTSIZ0_PKTCNT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DOEPTSIZ0_XFERSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DXEPTSIZ_MC_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define DXEPTSIZ_MC_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define DXEPTSIZ_MC_LIMIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DXEPTSIZ_MC(_x) ((_x) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DXEPTSIZ_PKTCNT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DXEPTSIZ_XFERSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PCGCTL HSOTG_REG(0x0e00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define PCGCTL_IF_DEV_MODE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define PCGCTL_MAX_TERMSEL BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define PCGCTL_PORT_POWER BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define PCGCTL_PRT_CLK_SEL_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define PCGCTL_ESS_REG_RESTORED BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define PCGCTL_RESTOREMODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define PCGCTL_RESETAFTSUSP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define PCGCTL_DEEP_SLEEP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define PCGCTL_PHY_IN_SLEEP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define PCGCTL_RSTPDWNMODULE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define PCGCTL_PWRCLMP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define PCGCTL_GATEHCLK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define PCGCTL_STOPPCLK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define PCGCCTL1 HSOTG_REG(0xe04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define PCGCCTL1_TIMER (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define PCGCCTL1_GATEEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Host Mode Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define HCFG HSOTG_REG(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define HCFG_MODECHTIMEN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define HCFG_PERSCHEDENA BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define HCFG_FRLISTEN_MASK (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define HCFG_FRLISTEN_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define HCFG_FRLISTEN_8 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define FRLISTEN_8_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define HCFG_FRLISTEN_16 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define FRLISTEN_16_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define HCFG_FRLISTEN_32 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define FRLISTEN_32_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define HCFG_FRLISTEN_64 (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define FRLISTEN_64_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define HCFG_DESCDMA BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define HCFG_RESVALID_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define HCFG_RESVALID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define HCFG_ENA32KHZ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define HCFG_FSLSSUPP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define HCFG_FSLSPCLKSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define HCFG_FSLSPCLKSEL_30_60_MHZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define HCFG_FSLSPCLKSEL_48_MHZ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define HCFG_FSLSPCLKSEL_6_MHZ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define HFIR HSOTG_REG(0x0404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define HFIR_FRINT_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define HFIR_FRINT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define HFIR_RLDCTRL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define HFNUM HSOTG_REG(0x0408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define HFNUM_FRREM_MASK (0xffff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define HFNUM_FRREM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define HFNUM_FRNUM_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define HFNUM_FRNUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define HFNUM_MAX_FRNUM 0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define HPTXSTS HSOTG_REG(0x0410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TXSTS_QTOP_ODD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define TXSTS_QTOP_CHNEP_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define TXSTS_QTOP_TOKEN_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define TXSTS_QTOP_TERMINATE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define TXSTS_QSPCAVAIL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define TXSTS_FSPCAVAIL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define HAINT HSOTG_REG(0x0414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define HAINTMSK HSOTG_REG(0x0418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define HFLBADDR HSOTG_REG(0x041c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define HPRT0 HSOTG_REG(0x0440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define HPRT0_SPD_MASK (0x3 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define HPRT0_SPD_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define HPRT0_SPD_HIGH_SPEED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define HPRT0_SPD_FULL_SPEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define HPRT0_SPD_LOW_SPEED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define HPRT0_TSTCTL_MASK (0xf << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define HPRT0_TSTCTL_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define HPRT0_PWR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define HPRT0_LNSTS_MASK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define HPRT0_LNSTS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define HPRT0_RST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define HPRT0_SUSP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define HPRT0_RES BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define HPRT0_OVRCURRCHG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define HPRT0_OVRCURRACT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define HPRT0_ENACHG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define HPRT0_ENA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define HPRT0_CONNDET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define HPRT0_CONNSTS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define HCCHAR_CHENA BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define HCCHAR_CHDIS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define HCCHAR_ODDFRM BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define HCCHAR_DEVADDR_MASK (0x7f << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define HCCHAR_DEVADDR_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define HCCHAR_MULTICNT_MASK (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define HCCHAR_MULTICNT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define HCCHAR_EPTYPE_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define HCCHAR_EPTYPE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define HCCHAR_LSPDDEV BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define HCCHAR_EPDIR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define HCCHAR_EPNUM_MASK (0xf << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define HCCHAR_EPNUM_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define HCCHAR_MPS_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define HCCHAR_MPS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define HCSPLT_SPLTENA BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define HCSPLT_COMPSPLT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define HCSPLT_XACTPOS_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define HCSPLT_XACTPOS_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define HCSPLT_XACTPOS_MID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define HCSPLT_XACTPOS_END 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define HCSPLT_XACTPOS_BEGIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define HCSPLT_XACTPOS_ALL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define HCSPLT_HUBADDR_MASK (0x7f << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define HCSPLT_HUBADDR_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define HCSPLT_PRTADDR_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define HCSPLT_PRTADDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define HCINTMSK_FRM_LIST_ROLL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define HCINTMSK_XCS_XACT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define HCINTMSK_BNA BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define HCINTMSK_DATATGLERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define HCINTMSK_FRMOVRUN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define HCINTMSK_BBLERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define HCINTMSK_XACTERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define HCINTMSK_NYET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define HCINTMSK_ACK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define HCINTMSK_NAK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define HCINTMSK_STALL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define HCINTMSK_AHBERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define HCINTMSK_CHHLTD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define HCINTMSK_XFERCOMPL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define TSIZ_DOPNG BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define TSIZ_SC_MC_PID_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define TSIZ_SC_MC_PID_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define TSIZ_SC_MC_PID_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define TSIZ_SC_MC_PID_DATA1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define TSIZ_SC_MC_PID_MDATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define TSIZ_SC_MC_PID_SETUP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define TSIZ_PKTCNT_MASK (0x3ff << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define TSIZ_PKTCNT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define TSIZ_NTD_MASK (0xff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define TSIZ_NTD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define TSIZ_SCHINFO_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define TSIZ_SCHINFO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define TSIZ_XFERSIZE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * struct dwc2_dma_desc - DMA descriptor structure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * used for both host and gadget modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * @status: DMA descriptor status quadlet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @buf: DMA descriptor data buffer pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * DMA Descriptor structure contains two quadlets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * Status quadlet and Data buffer pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct dwc2_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Host Mode DMA descriptor status quadlet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define HOST_DMA_A BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define HOST_DMA_STS_MASK (0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define HOST_DMA_STS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define HOST_DMA_STS_PKTERR BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define HOST_DMA_EOL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define HOST_DMA_IOC BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define HOST_DMA_SUP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define HOST_DMA_ALT_QTD BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define HOST_DMA_QTD_OFFSET_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define HOST_DMA_ISOC_NBYTES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define HOST_DMA_NBYTES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define HOST_DMA_NBYTES_LIMIT 131071
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Device Mode DMA descriptor status quadlet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define DEV_DMA_BUFF_STS_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DEV_DMA_BUFF_STS_HREADY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DEV_DMA_BUFF_STS_DMABUSY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define DEV_DMA_BUFF_STS_DMADONE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DEV_DMA_BUFF_STS_HBUSY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DEV_DMA_STS_MASK (0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DEV_DMA_STS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define DEV_DMA_STS_SUCC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DEV_DMA_STS_BUFF_FLUSH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define DEV_DMA_STS_BUFF_ERR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define DEV_DMA_L BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define DEV_DMA_SHORT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define DEV_DMA_IOC BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define DEV_DMA_SR BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DEV_DMA_MTRF BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define DEV_DMA_ISOC_PID_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define DEV_DMA_ISOC_PID_DATA0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define DEV_DMA_ISOC_PID_DATA2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define DEV_DMA_ISOC_PID_DATA1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define DEV_DMA_ISOC_PID_MDATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define DEV_DMA_ISOC_FRNUM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define DEV_DMA_ISOC_NBYTES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define DEV_DMA_NBYTES_MASK (0xffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define DEV_DMA_NBYTES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define DEV_DMA_NBYTES_LIMIT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MAX_DMA_DESC_NUM_GENERIC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MAX_DMA_DESC_NUM_HS_ISOC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif /* __DWC2_HW_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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