^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2013 Synopsys, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 3. The names of the above-listed copyright holders may not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to endorse or promote products derived from this software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Foundation; either version 2 of the License, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This file contains the interrupt handlers for Host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/usb/ch11.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "hcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * If we get this many NAKs on a split transaction we'll slow down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * retransmission. A 1 here means delay after the first NAK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DWC2_NAKS_BEFORE_DELAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* This function is for debug only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 curr_frame_number = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (expected != curr_frame_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) expected, curr_frame_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (expected != curr_frame_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) hsotg->frame_num_array[hsotg->frame_num_idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) curr_frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hsotg->last_frame_num_array[hsotg->frame_num_idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) hsotg->last_frame_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) hsotg->frame_num_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else if (!hsotg->dumped_frame_num_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_info(hsotg->dev, "Frame Last Frame\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_info(hsotg->dev, "----- ----------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_info(hsotg->dev, "0x%04x 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) hsotg->frame_num_array[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) hsotg->last_frame_num_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) hsotg->dumped_frame_num_array = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) hsotg->last_frame_num = curr_frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct urb *usb_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!chan->qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (chan->qh->dev_speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!qtd->urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) usb_urb = qtd->urb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The root hub doesn't really have a TT, but Linux thinks it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * does because how could you have a "high speed hub" that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * directly talks directly to low speed devices without a TT?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * It's all lies. Lies, I tell you.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (usb_urb->dev->tt->hub == root_hub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) chan->qh->tt_buffer_dirty = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (usb_hub_clear_tt_buffer(usb_urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Clear failed; let's hope things work anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chan->qh->tt_buffer_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Handles the start-of-frame interrupt in host mode. Non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * transactions may be queued to the DWC_otg controller for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * (micro)frame. Periodic transactions may be queued to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * for the next (micro)frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct list_head *qh_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum dwc2_transaction_type tr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef DEBUG_SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dwc2_track_missed_sofs(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Determine whether any periodic QHs should be executed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) qh_entry = hsotg->periodic_sched_inactive.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) while (qh_entry != &hsotg->periodic_sched_inactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) qh_entry = qh_entry->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (dwc2_frame_num_le(qh->next_active_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) hsotg->frame_number)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) qh, hsotg->frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) qh->next_active_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Move QH to the ready list to be executed next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * (micro)frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) list_move_tail(&qh->qh_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &hsotg->periodic_sched_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tr_type = dwc2_hcd_select_transactions(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (tr_type != DWC2_TRANSACTION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dwc2_hcd_queue_transactions(hsotg, tr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Handles the Rx FIFO Level Interrupt, which indicates that there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * memory if the DWC_otg controller is operating in Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 grxsts, chnum, bcnt, dpid, pktsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct dwc2_host_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) grxsts = dwc2_readl(hsotg, GRXSTSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) chan = hsotg->hc_ptr_array[chnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(hsotg->dev, "Unable to get corresponding channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Packet Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (dbg_perio()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chan->data_pid_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (pktsts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case GRXSTS_PKTSTS_HCHIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Read the data into the host buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (bcnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Update the HC fields for the next packet received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) chan->xfer_count += bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chan->xfer_buf += bcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case GRXSTS_PKTSTS_DATATOGGLEERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case GRXSTS_PKTSTS_HCHHALTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Handled in interrupt, just ignore data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * data packets may be written to the FIFO for OUT transfers. More requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * may be written to the non-periodic request queue for IN transfers. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * interrupt is enabled only in Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * packets may be written to the FIFO for OUT transfers. More requests may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * written to the periodic request queue for IN transfers. This interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * enabled only in Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 *hprt0_modify)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct dwc2_core_params *params = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int do_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 usbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 prtspd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 fslspclksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 hfir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Every time when port enables calculate HFIR.FrInterval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hfir = dwc2_readl(hsotg, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) hfir &= ~HFIR_FRINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) HFIR_FRINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dwc2_writel(hsotg, hfir, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Check if we need to adjust the PHY clock speed for low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!params->host_support_fs_ls_low_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Port has been enabled, set the reset change flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) hsotg->flags.b.port_reset_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Set PHY low power clock select for FS/LS devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) do_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) HCFG_FSLSPCLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (prtspd == HPRT0_SPD_LOW_SPEED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) params->host_ls_low_power_phy_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* 6 MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "FS_PHY programming HCFG to 6 MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) do_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* 48 MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "FS_PHY programming HCFG to 48 MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) do_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Not low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) do_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (do_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) *hprt0_modify |= HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dwc2_writel(hsotg, *hprt0_modify, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) msecs_to_jiffies(60));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Port has been enabled, set the reset change flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hsotg->flags.b.port_reset_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * There are multiple conditions that can cause a port interrupt. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * determines which interrupt conditions have occurred and handles them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 hprt0_modify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) hprt0_modify = hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Clear appropriate bits in HPRT0 to clear the interrupt bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * GINTSTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) HPRT0_OVRCURRCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Port Connect Detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Set flag and clear if detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (hprt0 & HPRT0_CONNDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hprt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dwc2_hcd_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * The Hub driver asserts a reset when it sees port connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * status change flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Port Enable Changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Clear if detected - Set internal flag if disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (hprt0 & HPRT0_ENACHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hprt0, !!(hprt0 & HPRT0_ENA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (hprt0 & HPRT0_ENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) hsotg->new_connection = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) hsotg->flags.b.port_enable_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (hsotg->params.dma_desc_fs_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) hsotg->new_connection = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) hcfg &= ~HCFG_DESCDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Overcurrent Change Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (hprt0 & HPRT0_OVRCURRCHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) hprt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) hsotg->flags.b.port_over_current_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Gets the actual length of a transfer after the transfer halts. halt_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * holds the reason for the halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * is set to 1 upon return if less than the requested number of bytes were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * transferred. short_read may also be NULL on entry, in which case it remains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) enum dwc2_halt_status halt_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int *short_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 hctsiz, count, length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (halt_status == DWC2_HC_XFER_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TSIZ_XFERSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) length = chan->xfer_len - count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (short_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *short_read = (count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else if (chan->qh->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) length = qtd->ssplit_out_xfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) length = chan->xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Must use the hctsiz.pktcnt field to determine how much data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * has been transferred. This field reflects the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * packets that have been transferred via the USB. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * always an integral number of packets if the transfer was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * halted before its normal completion. (Can't use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * hctsiz.xfersize field because that reflects the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * bytes transferred via the AHB, not the USB).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) length = (chan->start_pkt_count - count) * chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Complete interrupt on the host channel. Updates the actual_length field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * of the URB based on the number of bytes transferred via the host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Sets the URB status if the data transfer is finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @chan: Programming view of host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @chnum: Channel number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @urb: Processing URB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * @qtd: Queue transfer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Return: 1 if the data transfer specified by the URB is completely finished,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct dwc2_hcd_urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int xfer_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int short_read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DWC2_HC_XFER_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) &short_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (urb->actual_length + xfer_length > urb->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) xfer_length = urb->length - urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) urb->actual_length, xfer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) urb->actual_length += xfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (urb->flags & URB_SEND_ZERO_PACKET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) urb->actual_length >= urb->length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) !(urb->length % chan->max_packet)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) xfer_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else if (short_read || urb->actual_length >= urb->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) xfer_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) urb->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) xfer_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Save the starting data toggle for the next transfer. The data toggle is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * saved in the QH for non-control transfers and it's saved in the QTD for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * control transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (WARN(!chan || !chan->qh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "chan->qh must be specified for non-control eps\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (pid == TSIZ_SC_MC_PID_DATA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) chan->qh->data_toggle = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) chan->qh->data_toggle = DWC2_HC_PID_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (WARN(!qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "qtd must be specified for control eps\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (pid == TSIZ_SC_MC_PID_DATA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) qtd->data_toggle = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) qtd->data_toggle = DWC2_HC_PID_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * the transfer is stopped for any reason. The fields of the current entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * the frame descriptor array are set based on the transfer state and the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * halt_status. Completes the Isochronous URB if all the URB frames have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * @chan: Programming view of host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * @chnum: Channel number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @halt_status: Reason for halting a host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @qtd: Queue transfer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static enum dwc2_halt_status dwc2_update_isoc_urb_state(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int chnum, struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct dwc2_hcd_iso_packet_desc *frame_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct dwc2_hcd_urb *urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return DWC2_HC_XFER_NO_HALT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) switch (halt_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case DWC2_HC_XFER_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) frame_desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) chan, chnum, qtd, halt_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case DWC2_HC_XFER_FRAME_OVERRUN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) urb->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) frame_desc->status = -ENOSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) frame_desc->status = -ECOMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) frame_desc->actual_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case DWC2_HC_XFER_BABBLE_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) urb->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) frame_desc->status = -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Don't need to update actual_length in this case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case DWC2_HC_XFER_XACT_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) urb->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) frame_desc->status = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) chan, chnum, qtd, halt_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Skip whole frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (chan->qh->do_split &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) qtd->isoc_split_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (++qtd->isoc_frame_index == urb->packet_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * urb->status is not used for isoc transfers. The individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * frame_desc statuses are used instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dwc2_host_complete(hsotg, qtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) halt_status = DWC2_HC_XFER_URB_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * still linked to the QH, the QH is added to the end of the inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * non-periodic schedule. For periodic QHs, removes the QH from the periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * schedule if no more QTDs are linked to the QH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int free_qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int continue_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct dwc2_qtd *qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (dbg_qh(qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hsotg, qh, free_qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (list_empty(&qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_dbg(hsotg->dev, "## QTD list empty ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto no_qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (qtd->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) continue_split = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) continue_split = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (free_qtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) continue_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) no_qtd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) qh->channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * dwc2_release_channel() - Releases a host channel for use by other transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * @hsotg: The HCD state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * @chan: The host channel to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * @qtd: The QTD associated with the host channel. This QTD may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * freed if the transfer is complete or an error has occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @halt_status: Reason the channel is being released. This status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * determines the actions taken by this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Also attempts to select and queue more transactions since at least one host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * channel is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) enum dwc2_transaction_type tr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 haintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int free_qtd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __func__, chan->hc_num, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) switch (halt_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case DWC2_HC_XFER_URB_COMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) free_qtd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case DWC2_HC_XFER_AHB_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case DWC2_HC_XFER_STALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case DWC2_HC_XFER_BABBLE_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) free_qtd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case DWC2_HC_XFER_XACT_ERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (qtd && qtd->error_count >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) " Complete URB with transaction error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) free_qtd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dwc2_host_complete(hsotg, qtd, -EPROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case DWC2_HC_XFER_URB_DEQUEUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * The QTD has already been removed and the QH has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * deactivated. Don't want to do anything except release the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * host channel and try to queue more transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) free_qtd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dwc2_host_complete(hsotg, qtd, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case DWC2_HC_XFER_NO_HALT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Release the host channel for use by other transfers. The cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * function clears the channel interrupt enables and conditions, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * there's no need to clear the Channel Halted interrupt separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!list_empty(&chan->hc_list_entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) list_del(&chan->hc_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dwc2_hc_cleanup(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) hsotg->available_host_channels++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) switch (chan->ep_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) hsotg->non_periodic_channels--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * Don't release reservations for periodic channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * here. That's done when a periodic transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * descheduled (i.e. when the QH is removed from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * periodic schedule).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) haintmsk = dwc2_readl(hsotg, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) haintmsk &= ~(1 << chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dwc2_writel(hsotg, haintmsk, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Try to queue more transfers now that there's a free channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) tr_type = dwc2_hcd_select_transactions(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (tr_type != DWC2_TRANSACTION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dwc2_hcd_queue_transactions(hsotg, tr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Halts a host channel. If the channel cannot be halted immediately because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * the request queue is full, this function ensures that the FIFO empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * interrupt for the appropriate queue is enabled so that the halt request can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * be queued when there is space in the request queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * This function may also be called in DMA mode. In that case, the channel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * simply released since the core always halts the channel automatically in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_vdbg(hsotg->dev, "DMA enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dwc2_release_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Slave mode processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dwc2_hc_halt(hsotg, chan, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (chan->halt_on_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_vdbg(hsotg->dev, "Halt on queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) chan->ep_type == USB_ENDPOINT_XFER_BULK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_vdbg(hsotg->dev, "control/bulk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * Make sure the Non-periodic Tx FIFO empty interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * is enabled so that the non-periodic schedule will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * be processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) gintmsk |= GINTSTS_NPTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_vdbg(hsotg->dev, "isoc/intr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * Move the QH from the periodic queued schedule to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * the periodic assigned schedule. This allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * halt to be queued when the periodic schedule is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) list_move_tail(&chan->qh->qh_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) &hsotg->periodic_sched_assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * Make sure the Periodic Tx FIFO Empty interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * enabled so that the periodic schedule will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) gintmsk |= GINTSTS_PTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * Performs common cleanup for non-periodic transfers after a Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Complete interrupt. This function should be called after any endpoint type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * specific handling is finished to release the host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int chnum, struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (chan->hcint & HCINTMSK_NYET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Got a NYET on the last transaction of the transfer. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * means that the endpoint should be in the PING state at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * beginning of the next transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_vdbg(hsotg->dev, "got NYET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) chan->qh->ping_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * Always halt and release the host channel to make it available for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * more transfers. There may still be more phases for a control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * transfer or more data packets for a bulk transfer at this point,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * but the host channel is still halted. A channel will be reassigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * to the transfer when the non-periodic schedule is processed after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * the channel is released. This allows transactions to be queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * properly via dwc2_hcd_queue_transactions, which also enables the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Tx FIFO Empty interrupt if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * IN transfers in Slave mode require an explicit disable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * halt the channel. (In DMA mode, this call simply releases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * the channel.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dwc2_halt_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * The channel is automatically disabled by the core for OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * transfers in Slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dwc2_release_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Performs common cleanup for periodic transfers after a Transfer Complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * interrupt. This function should be called after any endpoint type specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * handling is finished to release the host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Core halts channel in these cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dwc2_release_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Flush any outstanding requests from the Tx queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dwc2_halt_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct dwc2_hcd_iso_packet_desc *frame_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!qtd->urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DWC2_HC_XFER_COMPLETE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!len && !qtd->isoc_split_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) frame_desc->actual_length += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (chan->align_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_vdbg(hsotg->dev, "non-aligned buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DWC2_KMEM_UNALIGNED_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) memcpy(qtd->urb->buf + (chan->xfer_dma - qtd->urb->dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) chan->qh->dw_align_buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) qtd->isoc_split_offset += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (frame_desc->actual_length >= frame_desc->length || pid == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) frame_desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) qtd->isoc_frame_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) qtd->isoc_split_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (qtd->isoc_frame_index == qtd->urb->packet_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dwc2_host_complete(hsotg, qtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dwc2_release_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) DWC2_HC_XFER_URB_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dwc2_release_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) DWC2_HC_XFER_NO_HALT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 1; /* Indicates that channel released */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Handles a host channel Transfer Complete interrupt. This handler may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * called in either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct dwc2_hcd_urb *urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int pipe_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int urb_xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "--Host Channel %d Interrupt: Transfer Complete--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto handle_xfercomp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (pipe_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Do not disable the interrupt, just clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) goto handle_xfercomp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Handle xfer complete on CSPLIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (chan->qh->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (qtd->complete_split &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) qtd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto handle_xfercomp_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Update the QTD and URB states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) switch (pipe_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) switch (qtd->control_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case DWC2_CONTROL_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (urb->length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) qtd->control_phase = DWC2_CONTROL_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) qtd->control_phase = DWC2_CONTROL_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) " Control setup transaction done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case DWC2_CONTROL_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) chnum, urb, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (urb_xfer_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) qtd->control_phase = DWC2_CONTROL_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) " Control data transfer done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) case DWC2_CONTROL_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_vdbg(hsotg->dev, " Control transfer complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (urb->status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) urb->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dwc2_host_complete(hsotg, qtd, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) halt_status = DWC2_HC_XFER_URB_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (urb_xfer_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dwc2_host_complete(hsotg, qtd, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) halt_status = DWC2_HC_XFER_URB_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * Interrupt URB is done on the first transfer complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (urb_xfer_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dwc2_host_complete(hsotg, qtd, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) halt_status = DWC2_HC_XFER_URB_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) halt_status = DWC2_HC_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) DWC2_HC_XFER_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) handle_xfercomp_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * Handles a host channel STALL interrupt. This handler may be called in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct dwc2_hcd_urb *urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int pipe_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) DWC2_HC_XFER_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) goto handle_stall_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) goto handle_stall_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dwc2_host_complete(hsotg, qtd, -EPIPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (pipe_type == USB_ENDPOINT_XFER_BULK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pipe_type == USB_ENDPOINT_XFER_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dwc2_host_complete(hsotg, qtd, -EPIPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * USB protocol requires resetting the data toggle for bulk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * setup command is issued to the endpoint. Anticipate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * CLEAR_FEATURE command since a STALL has occurred and reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * the data toggle now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) chan->qh->data_toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) handle_stall_halt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) handle_stall_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Updates the state of the URB when a transfer has been stopped due to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * abnormal condition before the transfer completes. Modifies the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * actual_length field of the URB to reflect the number of bytes that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * actually been transferred via the host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct dwc2_hcd_urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) qtd, halt_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (urb->actual_length + xfer_length > urb->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (urb->length & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) xfer_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) xfer_length = urb->length - urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) urb->actual_length += xfer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) chan->start_pkt_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) xfer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) urb->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * Handles a host channel NAK interrupt. This handler may be called in either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!qtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!qtd->urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * interrupt. Re-start the SSPLIT transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * Normally for non-periodic transfers we'll retry right away, but to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * avoid interrupt storms we'll wait before retrying if we've got
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * several NAKs. If we didn't do this we'd retry directly from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * interrupt handler and could end up quickly getting another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * interrupt (another NAK), which we'd retry. Note that we do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * delay retries for IN parts of control requests, as those are expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * to complete fairly quickly, and if we delay them we risk confusing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * the device and cause it issue STALL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * Note that in DMA mode software only gets involved to re-send NAKed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * transfers for split transactions, so we only need to apply this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * delaying logic when handling splits. In non-DMA mode presumably we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * might want a similar delay if someone can demonstrate this problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * affects that code path too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (chan->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) qtd->num_naks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) qtd->qh->want_wait = qtd->num_naks >= DWC2_NAKS_BEFORE_DELAY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) !(chan->ep_type == USB_ENDPOINT_XFER_CONTROL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) chan->ep_is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) goto handle_nak_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (hsotg->params.host_dma && chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * NAK interrupts are enabled on bulk/control IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * transfers in DMA mode for the sole purpose of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * resetting the error count after a transaction error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * occurs. The core will continue transferring data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * NAK interrupts normally occur during OUT transfers in DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * or Slave mode. For IN transfers, more requests will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * queued as request queue space is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!chan->qh->ping_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) qtd, DWC2_HC_XFER_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (chan->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) chan->qh->ping_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * Halt the channel so the transfer can be re-started from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * the appropriate point or the PING protocol will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * start/continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* Should never get called for isochronous transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) handle_nak_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * Handles a host channel ACK interrupt. This interrupt is enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * performing the PING protocol in Slave mode, when errors occur during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * either Slave mode or DMA mode, and during Start Split transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct dwc2_hcd_iso_packet_desc *frame_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!chan->ep_is_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) chan->data_pid_start != DWC2_HC_PID_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) qtd->ssplit_out_xfer_count = chan->xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) qtd->complete_split = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* ISOC OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) switch (chan->xact_pos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) case DWC2_HCSPLT_XACTPOS_ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case DWC2_HCSPLT_XACTPOS_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) qtd->isoc_split_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) case DWC2_HCSPLT_XACTPOS_BEGIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case DWC2_HCSPLT_XACTPOS_MID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * For BEGIN or MID, calculate the length for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * the next microframe to determine the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * SSPLIT token, either MID or END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) frame_desc = &qtd->urb->iso_descs[
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) qtd->isoc_frame_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) qtd->isoc_split_offset += 188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (frame_desc->length - qtd->isoc_split_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) <= 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) qtd->isoc_split_pos =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) DWC2_HCSPLT_XACTPOS_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) qtd->isoc_split_pos =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) DWC2_HCSPLT_XACTPOS_MID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (chan->qh->ping_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) chan->qh->ping_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * Halt the channel so the transfer can be re-started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * from the appropriate point. This only happens in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * Slave mode. In DMA mode, the ping_state is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * when the transfer is started because the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * automatically executes the PING, then the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * If the ACK occurred when _not_ in the PING state, let the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * continue transferring data after clearing the error count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * Handles a host channel NYET interrupt. This interrupt should only occur on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * Bulk and Control OUT endpoints and for complete split transactions. If a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * NYET occurs at the same time as a Transfer Complete interrupt, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * handled in the xfercomp interrupt handler, not here. This handler may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * called in either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * NYET on CSPLIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * re-do the CSPLIT immediately on non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (chan->do_split && chan->complete_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) qtd->isoc_split_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) qtd->isoc_frame_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if (qtd->urb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) qtd->isoc_frame_index == qtd->urb->packet_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dwc2_host_complete(hsotg, qtd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dwc2_release_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) DWC2_HC_XFER_URB_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dwc2_release_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) DWC2_HC_XFER_NO_HALT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) goto handle_nyet_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct dwc2_qh *qh = chan->qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) bool past_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (!hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int frnum = dwc2_hcd_get_frame_number(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Don't have num_hs_transfers; simple logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) past_end = dwc2_full_frame_num(frnum) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dwc2_full_frame_num(qh->next_active_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int end_frnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * Figure out the end frame based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * schedule.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * We don't want to go on trying again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * and again forever. Let's stop when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * we've done all the transfers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * were scheduled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * We're going to be comparing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * start_active_frame and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * next_active_frame, both of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * are 1 before the time the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * goes on the wire, so that cancels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * out. Basically if had 1 transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * and we saw 1 NYET then we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * We're getting a NYET here so if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * next >= (start + num_transfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * we're done. The complexity is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * for all but ISOC_OUT we skip one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) end_frnum = dwc2_frame_num_inc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) qh->start_active_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) qh->num_hs_transfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) qh->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) end_frnum =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dwc2_frame_num_inc(end_frnum, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) past_end = dwc2_frame_num_le(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) end_frnum, qh->next_active_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (past_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Treat this as a transaction error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * Todo: Fix system performance so this can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * be treated as an error. Right now complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * splits cannot be scheduled precisely enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * due to other system activity, so this error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * occurs regularly in Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) qtd->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dwc2_halt_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Todo: add support for isoc release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) goto handle_nyet_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) goto handle_nyet_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) chan->qh->ping_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) DWC2_HC_XFER_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * Halt the channel and re-start the transfer so the PING protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * will start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) handle_nyet_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * Handles a host channel babble interrupt. This handler may be called in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) DWC2_HC_XFER_BABBLE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto disable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) enum dwc2_halt_status halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) qtd, DWC2_HC_XFER_BABBLE_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dwc2_halt_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) disable_int:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Handles a host channel AHB error interrupt. This handler is only called in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct dwc2_hcd_urb *urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) char *pipetype, *speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) u32 hcsplt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) u32 hc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) goto handle_ahberr_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_err(hsotg->dev, " Device address: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) dwc2_hcd_get_dev_addr(&urb->pipe_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dev_err(hsotg->dev, " Endpoint: %d, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dwc2_hcd_get_ep_num(&urb->pipe_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) pipetype = "CONTROL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) pipetype = "BULK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) pipetype = "INTERRUPT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) pipetype = "ISOCHRONOUS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pipetype = "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) switch (chan->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) speed = "HIGH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) speed = "FULL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) speed = "LOW";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) speed = "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_err(hsotg->dev, " Speed: %s\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev_err(hsotg->dev, " Max packet size: %d (mult %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dwc2_hcd_get_maxp(&urb->pipe_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dwc2_hcd_get_maxp_mult(&urb->pipe_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) urb->buf, (unsigned long)urb->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) urb->setup_packet, (unsigned long)urb->setup_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* Core halts the channel for Descriptor DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) DWC2_HC_XFER_AHB_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) goto handle_ahberr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) dwc2_host_complete(hsotg, qtd, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) handle_ahberr_halt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Force a channel halt. Don't call dwc2_halt_channel because that won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * write to the HCCHARn register in DMA mode to force the halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) handle_ahberr_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * Handles a host channel transaction error interrupt. This handler may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * called in either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) goto handle_xacterr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) qtd->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (!chan->qh->ping_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) chan->qh->ping_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * Halt the channel so the transfer can be re-started from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * the appropriate point or the PING protocol will start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) qtd->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (chan->do_split && chan->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) qtd->complete_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) enum dwc2_halt_status halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) chnum, qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) dwc2_halt_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) handle_xacterr_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * Handles a host channel frame overrun interrupt. This handler may be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * in either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) enum dwc2_halt_status halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) qtd, DWC2_HC_XFER_FRAME_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dwc2_halt_channel(hsotg, chan, qtd, halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * Handles a host channel data toggle error interrupt. This handler may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * called in either DMA mode or Slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) "Data Toggle Error on OUT transfer, channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * For debug only. It checks that a valid halt status is set and that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * HCCHARn.chdis is clear. If there's a problem, corrective action is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * taken and a warning is issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * Return: true if halt status is ok, false otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u32 hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u32 hcsplt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * This code is here only as a check. This condition should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * never happen. Ignore the halt if it does occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) chnum, hcchar, hctsiz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) chan->hcint, hcintmsk, hcsplt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) qtd->complete_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) "%s: no halt status, channel %d, ignoring interrupt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) __func__, chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) * This code is here only as a check. hcchar.chdis should never be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) * when the halt interrupt occurs. Halt the channel again if it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (hcchar & HCCHAR_CHDIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) __func__, hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) chan->halt_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * Handles a host Channel Halted interrupt in DMA mode. This handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * determines the reason the channel halted and proceeds accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) u32 hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) int out_nak_enh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) "--Host Channel %d Interrupt: DMA Channel Halted--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * For core with OUT NAK enhancement, the flow for high-speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * CONTROL/BULK OUT is handled a little differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) out_nak_enh = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) !hsotg->params.dma_desc_enable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (hsotg->params.dma_desc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * Just release the channel. A dequeue can happen on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) * transfer timeout. In the case of an AHB Error, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * channel was forced to halt because there's no way to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * gracefully recover.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dwc2_release_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (chan->hcint & HCINTMSK_XFERCOMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * Todo: This is here because of a possible hardware bug. Spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) * interrupt w/ACK bit set should occur, but I only see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * XFERCOMP bit, even with it masked out. This is a workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * for that behavior. Should fix this when hardware is fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) } else if (chan->hcint & HCINTMSK_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) } else if ((chan->hcint & HCINTMSK_XACTERR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) !hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (out_nak_enh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (chan->hcint &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "XactErr with NYET/NAK/ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) qtd->error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) "XactErr without NYET/NAK/ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * Must handle xacterr before nak or ack. Could get a xacterr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * at the same time as either of these on a BULK/CONTROL OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * that started with a PING. The xacterr takes precedence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) } else if ((chan->hcint & HCINTMSK_AHBERR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) } else if (chan->hcint & HCINTMSK_BBLERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) } else if (!out_nak_enh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (chan->hcint & HCINTMSK_NYET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * Must handle nyet before nak or ack. Could get a nyet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * at the same time as either of those on a BULK/CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * OUT that started with a PING. The nyet takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * precedence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) } else if ((chan->hcint & HCINTMSK_NAK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) !(hcintmsk & HCINTMSK_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * If nak is not masked, it's because a non-split IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * transfer is in an error state. In that case, the nak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * is handled by the nak interrupt handler, not here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) * Handle nak here for BULK/CONTROL OUT transfers, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * halt on a NAK to allow rewinding the buffer pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) } else if ((chan->hcint & HCINTMSK_ACK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) !(hcintmsk & HCINTMSK_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * If ack is not masked, it's because a non-split IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * transfer is in an error state. In that case, the ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * is handled by the ack interrupt handler, not here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * Handle ack here for split transfers. Start splits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * halt on ACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * A periodic transfer halted with no other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * channel interrupts set. Assume it was halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * by the core because it could not be completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * in its scheduled (micro)frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "%s: Halt channel %d (assume incomplete periodic transfer)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) __func__, chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) dwc2_halt_channel(hsotg, chan, qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) DWC2_HC_XFER_PERIODIC_INCOMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "%s: Channel %d - ChHltd set, but reason is unknown\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) __func__, chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) "hcint 0x%08x, intsts 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) chan->hcint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dwc2_readl(hsotg, GINTSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) dev_info(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) chan->hcint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* Failthrough: use 3-strikes rule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) qtd->error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * We can get here after a completed transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * (urb->actual_length >= urb->length) which was not reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * as completed. If that is the case, and we do not abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) * the transfer, a transfer of size 0 will be enqueued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * subsequently. If urb->actual_length is not DMA-aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * the buffer will then point to an unaligned address, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) * the resulting behavior is undefined. Bail out in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (qtd->urb->actual_length >= qtd->urb->length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) qtd->error_count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * Handles a host channel Channel Halted interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * In slave mode, this handler is called only when the driver specifically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * requests a halt. This occurs during handling other host channel interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * (e.g. nak, xacterr, stall, nyet, etc.).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * In DMA mode, this is the interrupt that occurs when the core has finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * processing a transfer on a channel. Other host channel interrupts (except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * ahberr) are disabled in DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct dwc2_host_chan *chan, int chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * Check if the given qtd is still the top of the list (and thus valid).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * the qtd from the top of the list, this will return false (otherwise true).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct dwc2_qtd *cur_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (!qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) qtd_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return (cur_head == qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /* Handles interrupt for a specific Host Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) struct dwc2_qtd *qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct dwc2_host_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) u32 hcint, hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) chan = hsotg->hc_ptr_array[chnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) hcint = dwc2_readl(hsotg, HCINT(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dwc2_writel(hsotg, hcint, HCINT(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) hcint, hcintmsk, hcint & hcintmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) * If we got an interrupt after someone called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) * dwc2_hcd_endpoint_disable() we don't want to crash below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (!chan->qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) chan->hcint = hcint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) hcint &= hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) dwc2_writel(hsotg, hcint, HCINT(chnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) * If the channel was halted due to a dequeue, the qtd list might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * be empty or at least the first entry will not be the active qtd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * In this case, take a shortcut and just release the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * If the channel was halted, this should be the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * interrupt unmasked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) WARN_ON(hcint != HCINTMSK_CHHLTD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (hsotg->params.dma_desc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dwc2_release_channel(hsotg, chan, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (list_empty(&chan->qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) * TODO: Will this ever happen with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * DWC2_HC_XFER_URB_DEQUEUE handling above?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) chnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) chan->hcint, hcintmsk, hcint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) chan->hcint = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) qtd_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) hcint &= ~HCINTMSK_CHHLTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (hcint & HCINTMSK_XFERCOMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) * If NYET occurred at same time as Xfer Complete, the NYET is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) * handled by the Xfer Complete interrupt handler. Don't want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * to call the NYET interrupt handler in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) hcint &= ~HCINTMSK_NYET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (hcint & HCINTMSK_CHHLTD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (hcint & HCINTMSK_AHBERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (hcint & HCINTMSK_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (hcint & HCINTMSK_NAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (hcint & HCINTMSK_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (hcint & HCINTMSK_NYET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (hcint & HCINTMSK_XACTERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (hcint & HCINTMSK_BBLERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (hcint & HCINTMSK_FRMOVRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (hcint & HCINTMSK_DATATGLERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) chan->hcint = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * This interrupt indicates that one or more host channels has a pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) * interrupt. There are multiple conditions that can cause each host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) * interrupt. This function determines which conditions have occurred for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * host channel interrupt and handles them appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) u32 haint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) struct dwc2_host_chan *chan, *chan_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) haint = dwc2_readl(hsotg, HAINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) if (dbg_perio()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * According to USB 2.0 spec section 11.18.8, a host must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * issue complete-split transactions in a microframe for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) * set of full-/low-speed endpoints in the same relative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * order as the start-splits were issued in a microframe for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) split_order_list_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int hc_num = chan->hc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (haint & (1 << hc_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) dwc2_hc_n_intr(hsotg, hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) haint &= ~(1 << hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) for (i = 0; i < hsotg->params.host_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) if (haint & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) dwc2_hc_n_intr(hsotg, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /* This function handles interrupts for the HCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) u32 gintsts, dbg_gintsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (!dwc2_is_controller_alive(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) dev_warn(hsotg->dev, "Controller is dead\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) /* Check if HOST Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (dwc2_is_host_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) gintsts = dwc2_read_core_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!gintsts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) retval = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) dbg_gintsts = gintsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #ifndef DEBUG_SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) dbg_gintsts &= ~GINTSTS_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (!dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) GINTSTS_PTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) /* Only print if there are any non-suppressed interrupts left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) if (dbg_gintsts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) gintsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (gintsts & GINTSTS_SOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) dwc2_sof_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (gintsts & GINTSTS_RXFLVL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) dwc2_rx_fifo_level_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (gintsts & GINTSTS_NPTXFEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) dwc2_np_tx_fifo_empty_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (gintsts & GINTSTS_PRTINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) dwc2_port_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) if (gintsts & GINTSTS_HCHINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) dwc2_hc_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (gintsts & GINTSTS_PTXFEMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) dwc2_perio_tx_fifo_empty_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (dbg_gintsts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) "DWC OTG HCD Finished Servicing Interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) dwc2_readl(hsotg, GINTSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) dwc2_readl(hsotg, GINTMSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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