^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * hcd.c - DesignWare HS OTG Controller host-mode routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2013 Synopsys, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions, and the following disclaimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * without modification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 3. The names of the above-listed copyright holders may not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to endorse or promote products derived from this software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Foundation; either version 2 of the License, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * This file contains the core HCD code, and implements the Linux hc_driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/usb/ch11.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "hcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Host Core Layer Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * used in both device and host modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Clear any pending OTG Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dwc2_writel(hsotg, 0xffffffff, GOTGINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Enable the interrupts in the GINTMSK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) intmsk |= GINTSTS_RXFLVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!hsotg->params.external_id_pin_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) intmsk |= GINTSTS_CONIDSTSCHNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GINTSTS_SESSREQINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) intmsk |= GINTSTS_LPMTRANRCVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dwc2_writel(hsotg, intmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) switch (hsotg->hw_params.arch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) case GHWCFG2_EXT_DMA_ARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(hsotg->dev, "External DMA Mode not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case GHWCFG2_INT_DMA_ARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(hsotg->dev, "Internal DMA Mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (hsotg->params.ahbcfg != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ahbcfg &= GAHBCFG_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ahbcfg |= hsotg->params.ahbcfg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ~GAHBCFG_CTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case GHWCFG2_SLAVE_ONLY_ARCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(hsotg->dev, "Slave Only Mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ahbcfg |= GAHBCFG_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dwc2_writel(hsotg, ahbcfg, GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 usbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (hsotg->hw_params.op_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (hsotg->params.otg_cap ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) usbcfg |= GUSBCFG_HNPCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (hsotg->params.otg_cap !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) usbcfg |= GUSBCFG_SRPCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (hsotg->params.otg_cap !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) usbcfg |= GUSBCFG_SRPCAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (hsotg->vbus_supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return regulator_enable(hsotg->vbus_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (hsotg->vbus_supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return regulator_disable(hsotg->vbus_supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_dbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dwc2_writel(hsotg, 0, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dwc2_writel(hsotg, 0, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Enable the common interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dwc2_enable_common_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Enable host mode interrupts without disturbing common interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) intmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dwc2_writel(hsotg, intmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 intmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Disable host mode interrupts without disturbing common interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dwc2_writel(hsotg, intmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * For system that have a total fifo depth that is smaller than the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * RX + TX fifo size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dwc2_core_params *params = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct dwc2_hw_params *hw = &hsotg->hw_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) total_fifo_size = hw->total_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rxfsiz = params->host_rx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) nptxfsiz = params->host_nperio_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ptxfsiz = params->host_perio_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * allocation with support for high bandwidth endpoints. Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * defines MPS(Max Packet size) for a periodic EP=1024, and for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * non-periodic as 512.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * For Buffer DMA mode/Scatter Gather DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * 2 * ((Largest Packet size / 4) + 1 + 1) + n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * with n = number of host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * 2 * ((1024/4) + 2) = 516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) rxfsiz = 516 + hw->host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * min non-periodic tx fifo depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * 2 * (largest non-periodic USB packet used / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 2 * (512/4) = 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) nptxfsiz = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * min periodic tx fifo depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * (largest packet size*MC)/4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * (1024 * 3)/4 = 768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ptxfsiz = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) params->host_rx_fifo_size = rxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) params->host_nperio_tx_fifo_size = nptxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) params->host_perio_tx_fifo_size = ptxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * If the summation of RX, NPTX and PTX fifo sizes is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * bigger than the total_fifo_size, then we have a problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * We won't be able to allocate as many endpoints. Right now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * we're just printing an error message, but ideally this FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * allocation algorithm would be improved in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * FIXME improve this FIFO allocation algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(hsotg->dev, "invalid fifo sizes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct dwc2_core_params *params = &hsotg->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!params->enable_dynamic_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dwc2_calculate_dynamic_fifo(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) grxfsiz |= params->host_rx_fifo_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dwc2_readl(hsotg, GRXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Non-periodic Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dwc2_readl(hsotg, GNPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) nptxfsiz = params->host_nperio_tx_fifo_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) nptxfsiz |= params->host_rx_fifo_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dwc2_readl(hsotg, GNPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Periodic Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dwc2_readl(hsotg, HPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hptxfsiz = params->host_perio_tx_fifo_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) hptxfsiz |= (params->host_rx_fifo_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) params->host_nperio_tx_fifo_size) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dwc2_readl(hsotg, HPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (hsotg->params.en_multiple_tx_fifo &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * This feature was implemented in 2.91a version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Global DFIFOCFG calculation for Host mode -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * include RxFIFO, NPTXFIFO and HPTXFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dfifocfg |= (params->host_rx_fifo_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) params->host_nperio_tx_fifo_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) params->host_perio_tx_fifo_size) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GDFIFOCFG_EPINFOBASE_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GDFIFOCFG_EPINFOBASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * the HFIR register according to PHY type and speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * NOTE: The caller can modify the value of the HFIR register only after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * has been set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 usbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int clock = 60; /* default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) !(usbcfg & GUSBCFG_PHYIF16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) clock = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) clock = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) clock = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) clock = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) clock = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clock = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((usbcfg & GUSBCFG_PHYSEL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clock = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* High speed case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 125 * clock - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* FS/LS case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 1000 * clock - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @dest: Destination buffer for the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @bytes: Number of bytes to copy to the destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 *data_buf = (u32 *)dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int word_count = (bytes + 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Todo: Account for the case where dest is not dword aligned. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * requires reading data from the FIFO into a u32 temp buffer, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * moving it into the data buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (i = 0; i < word_count; i++, data_buf++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *data_buf = dwc2_readl(hsotg, HCFIFO(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * dwc2_dump_channel_info() - Prints the state of a host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @chan: Pointer to the channel to dump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * NOTE: This function will be removed once the peripheral controller code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * is integrated and the driver is stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 hcsplt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 hc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) hcchar, hcsplt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hctsiz, hc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) chan->dev_addr, chan->ep_num, chan->ep_is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) (unsigned long)chan->xfer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(hsotg->dev, " NP inactive sched:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) qh_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(hsotg->dev, " %p\n", qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(hsotg->dev, " NP waiting sched:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) qh_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_dbg(hsotg->dev, " %p\n", qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_dbg(hsotg->dev, " NP active sched:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) qh_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_dbg(hsotg->dev, " %p\n", qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(hsotg->dev, " Channels:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif /* VERBOSE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int _dwc2_hcd_start(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void dwc2_host_start(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) _dwc2_hcd_start(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hcd->self.is_b_host = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int *hub_addr, int *hub_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct urb *urb = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (urb->dev->tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *hub_addr = urb->dev->tt->hub->devnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *hub_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) *hub_port = urb->dev->ttport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Low Level Host Channel Access Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 hcintmsk = HCINTMSK_CHHLTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) switch (chan->ep_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_vdbg(hsotg->dev, "control/bulk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hcintmsk |= HCINTMSK_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hcintmsk |= HCINTMSK_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) hcintmsk |= HCINTMSK_XACTERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hcintmsk |= HCINTMSK_DATATGLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hcintmsk |= HCINTMSK_BBLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) hcintmsk |= HCINTMSK_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hcintmsk |= HCINTMSK_NYET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (chan->do_ping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) hcintmsk |= HCINTMSK_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (chan->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) hcintmsk |= HCINTMSK_NYET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (chan->error_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_vdbg(hsotg->dev, "intr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hcintmsk |= HCINTMSK_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) hcintmsk |= HCINTMSK_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) hcintmsk |= HCINTMSK_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) hcintmsk |= HCINTMSK_XACTERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) hcintmsk |= HCINTMSK_DATATGLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hcintmsk |= HCINTMSK_FRMOVRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hcintmsk |= HCINTMSK_BBLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (chan->error_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (chan->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) hcintmsk |= HCINTMSK_NYET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_vdbg(hsotg->dev, "isoc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hcintmsk |= HCINTMSK_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) hcintmsk |= HCINTMSK_FRMOVRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hcintmsk |= HCINTMSK_XACTERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hcintmsk |= HCINTMSK_BBLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(hsotg->dev, "## Unknown EP type ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 hcintmsk = HCINTMSK_CHHLTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * For Descriptor DMA mode core halts the channel on AHB error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Interrupt is not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_vdbg(hsotg->dev, "desc DMA disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hcintmsk |= HCINTMSK_AHBERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_vdbg(hsotg->dev, "desc DMA enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hcintmsk |= HCINTMSK_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (chan->error_state && !chan->do_split &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_vdbg(hsotg->dev, "setting ACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) hcintmsk |= HCINTMSK_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) hcintmsk |= HCINTMSK_DATATGLERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (chan->ep_type != USB_ENDPOINT_XFER_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hcintmsk |= HCINTMSK_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_vdbg(hsotg->dev, "DMA enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dwc2_hc_enable_dma_ints(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_vdbg(hsotg->dev, "DMA disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dwc2_hc_enable_slave_ints(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Enable the top level host channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) intmsk = dwc2_readl(hsotg, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) intmsk |= 1 << chan->hc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dwc2_writel(hsotg, intmsk, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* Make sure host channel interrupts are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) intmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) intmsk |= GINTSTS_HCHINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dwc2_writel(hsotg, intmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * a specific endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * @chan: Information needed to initialize the host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * The HCCHARn register is set up with the characteristics specified in chan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Host channel interrupts that may need to be serviced while this transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * in progress are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 hc_num = chan->hc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 hcsplt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Clear old interrupt conditions for this host channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) hcintmsk = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hcintmsk &= ~HCINTMSK_RESERVED14_31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Enable channel interrupts required for this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dwc2_hc_enable_ints(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * Program the HCCHARn register with the endpoint characteristics for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * the current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hcchar |= HCCHAR_EPDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (chan->speed == USB_SPEED_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hcchar |= HCCHAR_LSPDDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) hc_num, hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_vdbg(hsotg->dev, "%s: Channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __func__, hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) chan->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_vdbg(hsotg->dev, " Ep Num: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) chan->ep_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_vdbg(hsotg->dev, " Is In: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) chan->ep_is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) chan->speed == USB_SPEED_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_vdbg(hsotg->dev, " Ep Type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) chan->ep_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) chan->max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Program the HCSPLT register for SPLITs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "Programming HC %d with split --> %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) hc_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) chan->complete_split ? "CSPLIT" : "SSPLIT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (chan->complete_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) hcsplt |= HCSPLT_COMPSPLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) HCSPLT_XACTPOS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) HCSPLT_HUBADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) HCSPLT_PRTADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_vdbg(hsotg->dev, " comp split %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) chan->complete_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_vdbg(hsotg->dev, " xact pos %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) chan->xact_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_vdbg(hsotg->dev, " hub addr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) chan->hub_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev_vdbg(hsotg->dev, " hub port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) chan->hub_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_vdbg(hsotg->dev, " is_in %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chan->ep_is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_vdbg(hsotg->dev, " Max Pkt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) chan->max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_vdbg(hsotg->dev, " xferlen %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) chan->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * dwc2_hc_halt() - Attempts to halt a host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * @hsotg: Controller register interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * @chan: Host channel to halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * @halt_status: Reason for halting the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * This function should only be called in Slave mode or to abort a transfer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * controller halts the channel when the transfer is complete or a condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * occurs that requires application intervention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * In slave mode, checks for a free request queue entry, then sets the Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Enable and Channel Disable bits of the Host Channel Characteristics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * register of the specified channel to intiate the halt. If there is no free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * request queue entry, sets only the Channel Disable bit of the HCCHARn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * register to flush requests for this channel. In the latter case, sets a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * flag to indicate that the host channel needs to be halted when a request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * queue slot is open.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * HCCHARn register. The controller ensures there is space in the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * queue before submitting the halt request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Some time may elapse before the core flushes any posted requests for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * host channel and halts. The Channel Halted interrupt handler completes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * deactivation of the host channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) enum dwc2_halt_status halt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 nptxsts, hptxsts, hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * In buffer DMA or external DMA mode channel can't be halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * for non-split periodic channels. At the end of the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * uframe/frame (in the worst case), the core generates a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * halted and disables the channel automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if ((hsotg->params.host_dma && !hsotg->params.dma_desc_enable) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!chan->do_split &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) chan->ep_type == USB_ENDPOINT_XFER_INT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) (halt_status == DWC2_HC_XFER_URB_DEQUEUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) chan->halt_status = halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(hsotg->dev, "%s() Channel can't be halted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) halt_status == DWC2_HC_XFER_AHB_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * Disable all channel interrupts except Ch Halted. The QTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * and QH state associated with this transfer has been cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * (in the case of URB_DEQUEUE), so the channel needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * shut down carefully to prevent crashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 hcintmsk = HCINTMSK_CHHLTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_vdbg(hsotg->dev, "dequeue/error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Make sure no other interrupts besides halt are currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * pending. Handling another interrupt could cause a crash due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * to the QTD and QH state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * even if the channel was already halted for some other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) chan->halt_status = halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!(hcchar & HCCHAR_CHENA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * The channel is either already halted or it hasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * started yet. In DMA mode, the transfer may halt if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * it finishes normally or a condition occurs that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * requires driver intervention. Don't want to halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * the channel again. In either Slave or DMA mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * it's possible that the transfer has been assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * to a channel, but not started yet when an URB is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * dequeued. Don't want to halt a channel that hasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * started yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (chan->halt_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * A halt has already been issued for this channel. This might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * happen when a transfer is aborted by a higher level in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "*** %s: Channel %d, chan->halt_pending already set ***\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) __func__, chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* No need to set the bit in DDMA for disabling the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* TODO check it everywhere channel is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_vdbg(hsotg->dev, "desc DMA disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_dbg(hsotg->dev, "desc DMA enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hcchar |= HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_vdbg(hsotg->dev, "DMA not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Check for space in the request queue to issue the halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) chan->ep_type == USB_ENDPOINT_XFER_BULK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_vdbg(hsotg->dev, "control/bulk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) nptxsts = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_vdbg(hsotg->dev, "Disabling channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) hcchar &= ~HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_vdbg(hsotg->dev, "isoc/intr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) hptxsts = dwc2_readl(hsotg, HPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hsotg->queuing_high_bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_vdbg(hsotg->dev, "Disabling channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) hcchar &= ~HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev_vdbg(hsotg->dev, "DMA enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) chan->halt_status = halt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (hcchar & HCCHAR_CHENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_vdbg(hsotg->dev, "Channel enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) chan->halt_pending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) chan->halt_on_queue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_vdbg(hsotg->dev, "Channel disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) chan->halt_on_queue = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_vdbg(hsotg->dev, " halt_pending: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) chan->halt_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) chan->halt_on_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_vdbg(hsotg->dev, " halt_status: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * dwc2_hc_cleanup() - Clears the transfer state for a host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * @chan: Identifies the host channel to clean up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * This function is normally called after a transfer is done and the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * channel is being released
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) chan->xfer_started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) list_del_init(&chan->split_order_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * Clear channel interrupt enables and any unhandled channel interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) hcintmsk = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) hcintmsk &= ~HCINTMSK_RESERVED14_31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * which frame a periodic transfer should occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * @chan: Identifies the host channel to set up and its properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * @hcchar: Current value of the HCCHAR register for the specified host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * This function has no effect on non-periodic transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct dwc2_host_chan *chan, u32 *hcchar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int host_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int xfer_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int xfer_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int bytes_in_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u16 fifo_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u16 frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) u16 wire_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Try to figure out if we're an even or odd frame. If we set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * even and the current frame number is even the the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * will happen immediately. Similar if both are odd. If one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * even and the other is odd then the transfer will happen when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * the frame number ticks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * There's a bit of a balancing act to get this right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Sometimes we may want to send data in the current frame (AK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * right away). We might want to do this if the frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * _just_ ticked, but we might also want to do this in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * to continue a split transaction that happened late in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * microframe (so we didn't know to queue the next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * until the frame number had ticked). The problem is that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * need a lot of knowledge to know if there's actually still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * time to send things or if it would be better to wait until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * the next frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * We can look at how much time is left in the current frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * and make a guess about whether we'll have time to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * We'll do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Get speed host is running at */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) host_speed = (chan->speed != USB_SPEED_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* See how many bytes are in the periodic FIFO right now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) bytes_in_fifo = sizeof(u32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) (hsotg->params.host_perio_tx_fifo_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) fifo_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Roughly estimate bus time for everything in the periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * queue + our new transfer. This is "rough" because we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * using a function that makes takes into account IN/OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * and INT/ISO and we're just slamming in one value for all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * transfers. This should be an over-estimate and that should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * be OK, but we can probably tighten it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) xfer_ns = usb_calc_bus_time(host_speed, false, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) chan->xfer_len + bytes_in_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) xfer_us = NS_TO_US(xfer_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* See what frame number we'll be at by the time we finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* This is when we were scheduled to be on the wire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * If we'd finish _after_ the frame we're scheduled in then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * it's hopeless. Just schedule right away and hope for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * best. Note that it _might_ be wise to call back into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * scheduler to pick a better frame, but this is better than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (dwc2_frame_num_gt(frame_number, wire_frame)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dwc2_sch_vdbg(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) chan->qh, wire_frame, frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dwc2_frame_num_dec(frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) wire_frame));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) wire_frame = frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * We picked a different frame number; communicate this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * back to the scheduler so it doesn't try to schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * another in the same frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * Remember that next_active_frame is 1 before the wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) chan->qh->next_active_frame =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dwc2_frame_num_dec(frame_number, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (wire_frame & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) *hcchar |= HCCHAR_ODDFRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *hcchar &= ~HCCHAR_ODDFRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Set up the initial PID for the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (chan->speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (chan->multi_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) chan->data_pid_start = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) else if (chan->multi_count == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) chan->data_pid_start = DWC2_HC_PID_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) chan->data_pid_start = DWC2_HC_PID_DATA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (chan->multi_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) chan->data_pid_start = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) chan->data_pid_start = DWC2_HC_PID_MDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) chan->data_pid_start = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * the Host Channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * @chan: Information needed to initialize the host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * This function should only be called in Slave mode. For a channel associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * associated with a periodic EP, the periodic Tx FIFO is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * Upon return the xfer_buf and xfer_count fields in chan are incremented by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * the number of bytes written to the Tx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) u32 remaining_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 dword_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 *data_buf = (u32 *)chan->xfer_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) remaining_count = chan->xfer_len - chan->xfer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (remaining_count > chan->max_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) byte_count = chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) byte_count = remaining_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dword_count = (byte_count + 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (((unsigned long)data_buf & 0x3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* xfer_buf is DWORD aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) for (i = 0; i < dword_count; i++, data_buf++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* xfer_buf is not DWORD aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) for (i = 0; i < dword_count; i++, data_buf++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 data = data_buf[0] | data_buf[1] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) data_buf[2] << 16 | data_buf[3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) chan->xfer_count += byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) chan->xfer_buf += byte_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * dwc2_hc_do_ping() - Starts a PING transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * @chan: Information needed to initialize the host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * This function should only be called in Slave mode. The Do Ping bit is set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * the HCTSIZ register, then the channel is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) u32 hctsiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) hctsiz = TSIZ_DOPNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) hcchar &= ~HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * channel and starts the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * @chan: Information needed to initialize the host channel. The xfer_len value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * may be reduced to accommodate the max widths of the XferSize and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * PktCnt fields in the HCTSIZn register. The multi_count value may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * changed to reflect the final xfer_len value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * This function may be called in either Slave mode or DMA mode. In Slave mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * the caller must ensure that there is sufficient space in the request queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * and Tx Data FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) * For an OUT transfer in Slave mode, it loads a data packet into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * appropriate FIFO. If necessary, additional data packets are loaded in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * Host ISR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * For an IN transfer in Slave mode, a data packet is requested. The data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * additional data packets are requested in the Host ISR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * register along with a packet count of 1 and the channel is enabled. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * causes a single PING transaction to occur. Other fields in HCTSIZ are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * simply set to 0 since no data transfer occurs in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * all the information required to perform the subsequent data transfer. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * controller performs the entire PING protocol, then starts the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u16 max_hc_pkt_count = hsotg->params.max_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 hctsiz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) u16 num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u32 ec_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_vdbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (chan->do_ping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) dev_vdbg(hsotg->dev, "ping, no DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dwc2_hc_do_ping(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) chan->xfer_started = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_vdbg(hsotg->dev, "ping, DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) hctsiz |= TSIZ_DOPNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_vdbg(hsotg->dev, "split\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) num_packets = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (chan->complete_split && !chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * For CSPLIT OUT Transfer, set the size to 0 so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * core doesn't expect any data written to the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) chan->xfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) chan->xfer_len = chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else if (!chan->ep_is_in && chan->xfer_len > 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) chan->xfer_len = 188;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) TSIZ_XFERSIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* For split set ec_mc for immediate retries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ec_mc = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ec_mc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev_vdbg(hsotg->dev, "no split\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * Ensure that the transfer length and packet count will fit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * in the widths allocated for them in the HCTSIZn register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * Make sure the transfer size is no larger than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * (micro)frame's worth of data. (A check was done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * when the periodic transfer was accepted to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * that a (micro)frame's worth of data can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * programmed into a channel.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u32 max_periodic_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) chan->multi_count * chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (chan->xfer_len > max_periodic_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) chan->xfer_len = max_periodic_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) } else if (chan->xfer_len > max_hc_xfer_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * Make sure that xfer_len is a multiple of max packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) chan->xfer_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) max_hc_xfer_size - chan->max_packet + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (chan->xfer_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) num_packets = (chan->xfer_len + chan->max_packet - 1) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (num_packets > max_hc_pkt_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) num_packets = max_hc_pkt_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) chan->xfer_len = num_packets * chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * Always program an integral # of max packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * for IN transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * Note: This assumes that the input buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * aligned and sized accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) chan->xfer_len = num_packets * chan->max_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* Need 1 packet for transfer length of 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) num_packets = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * Make sure that the multi_count field matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * actual transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) chan->multi_count = num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dwc2_set_pid_isoc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) TSIZ_XFERSIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* The ec_mc gets the multi_count for non-split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ec_mc = chan->multi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) chan->start_pkt_count = num_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) TSIZ_SC_MC_PID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) hctsiz, chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) (hctsiz & TSIZ_XFERSIZE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) TSIZ_XFERSIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) (hctsiz & TSIZ_PKTCNT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) TSIZ_PKTCNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dev_vdbg(hsotg->dev, " Start PID: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) (hctsiz & TSIZ_SC_MC_PID_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) TSIZ_SC_MC_PID_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (chan->align_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_vdbg(hsotg->dev, "align_buf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dma_addr = chan->align_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dma_addr = chan->xfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) (unsigned long)dma_addr, chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Start the split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (chan->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) hcsplt |= HCSPLT_SPLTENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) hcchar &= ~HCCHAR_MULTICNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (hcchar & HCCHAR_CHDIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) "%s: chdis set, channel %d, hcchar 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) __func__, chan->hc_num, hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* Set host channel enable after all other setup is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hcchar &= ~HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) (hcchar & HCCHAR_MULTICNT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) HCCHAR_MULTICNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) chan->xfer_started = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) chan->requests++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (!hsotg->params.host_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) !chan->ep_is_in && chan->xfer_len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Load OUT packet into the appropriate Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dwc2_hc_write_packet(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * host channel and starts the transfer in Descriptor DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * @chan: Information needed to initialize the host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * with micro-frame bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * Initializes HCDMA register with descriptor list address and CTD value then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * starts the transfer via enabling the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 hctsiz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (chan->do_ping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) hctsiz |= TSIZ_DOPNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dwc2_set_pid_isoc(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) TSIZ_SC_MC_PID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Non-zero only for high-speed interrupt endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (dbg_hc(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) dev_vdbg(hsotg->dev, " Start PID: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) chan->data_pid_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) chan->desc_list_sz, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) &chan->desc_list_addr, chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) hcchar &= ~HCCHAR_MULTICNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) HCCHAR_MULTICNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (hcchar & HCCHAR_CHDIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) "%s: chdis set, channel %d, hcchar 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) __func__, chan->hc_num, hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* Set host channel enable after all other setup is complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) hcchar &= ~HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) (hcchar & HCCHAR_MULTICNT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) HCCHAR_MULTICNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) chan->xfer_started = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) chan->requests++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * a previous call to dwc2_hc_start_transfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * @chan: Information needed to initialize the host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * The caller must ensure there is sufficient space in the request queue and Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * Data FIFO. This function should only be called in Slave mode. In DMA mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * the controller acts autonomously to complete transfers programmed to a host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * if there is any data remaining to be queued. For an IN transfer, another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * data packet is always requested. For the SETUP phase of a control transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * this function does nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * Return: 1 if a new request is queued, 0 if no more requests are required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * for this transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) chan->hc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (chan->do_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* SPLITs always queue just once per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (chan->data_pid_start == DWC2_HC_PID_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* SETUPs are queued only once since they can't be NAK'd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Always queue another request for other IN transfers. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * back-to-back INs are issued and NAKs are received for both,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * the driver may still be processing the first NAK when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * second NAK is received. When the interrupt handler clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * the NAK interrupt for the first NAK, the second NAK will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * not be seen. So we can't depend on the NAK interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * handler to requeue a NAK'd request. Instead, IN requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * are issued each time this function is called. When the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * transfer completes, the extra requests for the channel will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * be flushed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) hcchar |= HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) hcchar &= ~HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (dbg_hc(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) chan->requests++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* OUT transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (chan->xfer_count < chan->xfer_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) u32 hcchar = dwc2_readl(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) HCCHAR(chan->hc_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dwc2_hc_set_even_odd_frame(hsotg, chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) &hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* Load OUT packet into the appropriate Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dwc2_hc_write_packet(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) chan->requests++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * HCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * Processes all the URBs in a single list of QHs. Completes them with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) * -ETIMEDOUT and frees the QTD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) struct list_head *qh_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct dwc2_qh *qh, *qh_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct dwc2_qtd *qtd, *qtd_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) qtd_list_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) dwc2_host_complete(hsotg, qtd, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct list_head *qh_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct dwc2_qtd *qtd, *qtd_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct dwc2_qh *qh, *qh_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!qh_list->next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* The list hasn't been initialized yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* Ensure there are no QTDs or URBs left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) dwc2_hcd_qh_unlink(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* Free each QTD in the QH's QTD list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) qtd_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (qh->channel && qh->channel->qh == qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) qh->channel->qh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dwc2_hcd_qh_free(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * and periodic schedules. The QTD associated with each URB is removed from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * the schedule and freed. This function may be called when a disconnect is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * detected or when the HCD is being stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * dwc2_hcd_start() - Starts the HCD when switching to Host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * @hsotg: Pointer to struct dwc2_hsotg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (hsotg->op_state == OTG_STATE_B_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * Reset the port. During a HNP mode switch the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) * needs to occur within 1ms and have a duration of at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * least 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hprt0 |= HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Must be called with interrupt disabled and spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) int num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct dwc2_host_chan *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /* Flush out any channel requests in slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) channel = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (!list_empty(&channel->hc_list_entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) hcchar = dwc2_readl(hsotg, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (hcchar & HCCHAR_CHENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) hcchar |= HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dwc2_writel(hsotg, hcchar, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) channel = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (!list_empty(&channel->hc_list_entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) hcchar = dwc2_readl(hsotg, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (hcchar & HCCHAR_CHENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* Halt the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) hcchar |= HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dwc2_writel(hsotg, hcchar, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dwc2_hc_cleanup(hsotg, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * Added for Descriptor DMA to prevent channel double cleanup in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * release_channel_ddma(), which is called from ep_disable when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) * device disconnects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) channel->qh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* All channels have been freed, mark them available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) hsotg->available_host_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) hsotg->non_periodic_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) hsotg->periodic_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * dwc2_hcd_connect() - Handles connect of the HCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * @hsotg: Pointer to struct dwc2_hsotg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (hsotg->lx_state != DWC2_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) usb_hcd_resume_root_hub(hsotg->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) hsotg->flags.b.port_connect_status_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) hsotg->flags.b.port_connect_status = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * dwc2_hcd_disconnect() - Handles disconnect of the HCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * @hsotg: Pointer to struct dwc2_hsotg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * @force: If true, we won't try to reconnect even if we see device connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* Set status flags for the hub driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) hsotg->flags.b.port_connect_status_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) hsotg->flags.b.port_connect_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * Shutdown any transfers in process by clearing the Tx FIFO Empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * interrupt mask and status bits and disabling subsequent host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * channel interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) intr = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dwc2_writel(hsotg, intr, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dwc2_writel(hsotg, intr, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * Turn off the vbus power only if the core has transitioned to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * mode. If still in host mode, need to keep power on to detect a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * reconnection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (dwc2_is_device_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) dwc2_writel(hsotg, 0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dwc2_disable_host_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) /* Respond with an error status to all URBs in the schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dwc2_kill_all_urbs(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (dwc2_is_host_mode(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* Clean up any host channels that were in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dwc2_hcd_cleanup_channels(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) dwc2_host_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * Add an extra check here to see if we're actually connected but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) * we don't have a detection interrupt pending. This can happen if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * 1. hardware sees connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * 2. hardware sees disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * 3. hardware sees connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * 4. dwc2_port_intr() - clears connect interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * 5. dwc2_handle_common_intr() - calls here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * Without the extra check here we will end calling disconnect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * and won't get any future interrupts to handle the connect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (!force && !(hprt0 & HPRT0_CONNDET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) (hprt0 & HPRT0_CONNSTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) dwc2_hcd_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) else if (hsotg->lx_state != DWC2_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) usb_hcd_resume_root_hub(hsotg->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * @hsotg: Pointer to struct dwc2_hsotg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (hsotg->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) hsotg->flags.b.port_suspend_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) usb_hcd_resume_root_hub(hsotg->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (hsotg->lx_state == DWC2_L1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) hsotg->flags.b.port_l1_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * @hsotg: Pointer to struct dwc2_hsotg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * The root hub should be disconnected before this function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) * and the QH lists (via ..._hcd_endpoint_disable).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* Turn off all host-specific interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) dwc2_disable_host_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* Turn off the vbus power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_dbg(hsotg->dev, "PortPower off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) dwc2_writel(hsotg, 0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /* Caller must hold driver lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) u32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) int dev_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (!hsotg->flags.b.port_connect_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* No longer connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dev_err(hsotg->dev, "Not connected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* Some configurations cannot support LS traffic on a FS root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if ((dev_speed == USB_SPEED_LOW) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) u32 hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (prtspd == HPRT0_SPD_FULL_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (!qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dwc2_hcd_qtd_init(qtd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) intr_mask = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (!(intr_mask & GINTSTS_SOF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) enum dwc2_transaction_type tr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) !(qtd->urb->flags & URB_GIVEBACK_ASAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * Do not schedule SG transactions until qtd has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * URB_GIVEBACK_ASAP set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) tr_type = dwc2_hcd_select_transactions(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (tr_type != DWC2_TRANSACTION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) dwc2_hcd_queue_transactions(hsotg, tr_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /* Must be called with interrupt disabled and spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) struct dwc2_hcd_urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct dwc2_qtd *urb_qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) urb_qtd = urb->qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (!urb_qtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) qh = urb_qtd->qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (!qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) urb->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (urb_qtd->in_process && qh->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dwc2_dump_channel_info(hsotg, qh->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* The QTD is in process (it has been assigned to a channel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (hsotg->flags.b.port_connect_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * If still connected (i.e. in host mode), halt the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * channel so it can be used for other transfers. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * no longer connected, the host registers can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * written to halt the channel since the core is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * device mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) dwc2_hc_halt(hsotg, qh->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) DWC2_HC_XFER_URB_DEQUEUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * Free the QTD and clean up the associated QH. Leave the QH in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * schedule if it has any remaining QTDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (!hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) u8 in_process = urb_qtd->in_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (in_process) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dwc2_hcd_qh_deactivate(hsotg, qh, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) qh->channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) } else if (list_empty(&qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dwc2_hcd_qh_unlink(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /* Must NOT be called with interrupt disabled or spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct usb_host_endpoint *ep, int retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct dwc2_qtd *qtd, *qtd_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (!qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) while (!list_empty(&qh->qtd_list) && retry--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (retry == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "## timeout in dwc2_hcd_endpoint_disable() ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (!qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) dwc2_hcd_qh_unlink(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Free each QTD in the QH's QTD list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (qh->channel && qh->channel->qh == qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) qh->channel->qh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) dwc2_hcd_qh_free(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* Must be called with interrupt disabled and spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) struct dwc2_qh *qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) qh->data_toggle = DWC2_HC_PID_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * dwc2_core_init() - Initializes the DWC_otg controller registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * prepares the core for device mode or host mode operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * @initial_setup: If true then this is the first init for this instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) u32 usbcfg, otgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /* Set ULPI External VBUS bit if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (hsotg->params.phy_ulpi_ext_vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) /* Set external TS Dline pulsing bit if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (hsotg->params.ts_dline)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) usbcfg |= GUSBCFG_TERMSELDLPULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) * Reset the Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) * We only need to reset the controller if this is a re-init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) * For the first init we know for sure that earlier code reset us (it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) * needed to in order to properly detect various parameters).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) if (!initial_setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) retval = dwc2_core_reset(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * This needs to happen in FS mode before any other programming occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) retval = dwc2_phy_init(hsotg, initial_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /* Program the GAHBCFG Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) retval = dwc2_gahbcfg_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /* Program the GUSBCFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dwc2_gusbcfg_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* Program the GOTGCTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) otgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) otgctl &= ~GOTGCTL_OTGVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dwc2_writel(hsotg, otgctl, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* Clear the SRP success bit for FS-I2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) hsotg->srp_success = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* Enable common interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) dwc2_enable_common_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * Do device or host initialization based on mode during PCD and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * HCD initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (dwc2_is_host_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) dev_dbg(hsotg->dev, "Host Mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) hsotg->op_state = OTG_STATE_A_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) dev_dbg(hsotg->dev, "Device Mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) hsotg->op_state = OTG_STATE_B_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * Host mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) * This function flushes the Tx and Rx FIFOs and flushes any entries in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * request queues. Host channels are reset to ensure that they are ready for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * performing transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) u32 hcfg, hfir, otgctl, usbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) /* Set HS/FS Timeout Calibration to 7 (max available value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) * The number of PHY clocks that the application programs in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * this field is added to the high/full speed interpacket timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * duration in the core to account for any additional delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * introduced by the PHY. This can be required, because the delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * introduced by the PHY in generating the linestate condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * can vary from one PHY to another.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) usbcfg |= GUSBCFG_TOUTCAL(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /* Restart the Phy Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dwc2_writel(hsotg, 0, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /* Initialize Host Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) dwc2_init_fs_ls_pclk_sel(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) hcfg |= HCFG_FSLSSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * This bit allows dynamic reloading of the HFIR register during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * runtime. This bit needs to be programmed during initial configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * and its value must not be changed during runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) if (hsotg->params.reload_ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) hfir = dwc2_readl(hsotg, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) hfir |= HFIR_RLDCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) dwc2_writel(hsotg, hfir, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) u32 op_mode = hsotg->hw_params.op_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) !hsotg->hw_params.dma_desc_enable ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) "Hardware does not support descriptor DMA mode -\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) "falling back to buffer DMA mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) hcfg |= HCFG_DESCDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /* Configure data FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) dwc2_config_fifos(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* TODO - check this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* Clear Host Set HNP Enable in the OTG Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) otgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) otgctl &= ~GOTGCTL_HSTSETHNPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) dwc2_writel(hsotg, otgctl, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Make sure the FIFOs are flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) dwc2_flush_rx_fifo(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) /* Clear Host Set HNP Enable in the OTG Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) otgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) otgctl &= ~GOTGCTL_HSTSETHNPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) dwc2_writel(hsotg, otgctl, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (!hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) int num_channels, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) u32 hcchar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* Flush out any leftover queued requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) hcchar = dwc2_readl(hsotg, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (hcchar & HCCHAR_CHENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) hcchar &= ~HCCHAR_CHENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) hcchar |= HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) hcchar &= ~HCCHAR_EPDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dwc2_writel(hsotg, hcchar, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /* Halt all channels to put them into a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) hcchar = dwc2_readl(hsotg, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if (hcchar & HCCHAR_CHENA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) hcchar &= ~HCCHAR_EPDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) dwc2_writel(hsotg, hcchar, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) HCCHAR_CHENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) "Unable to clear enable on channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /* Enable ACG feature in host mode, if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) dwc2_enable_acg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /* Turn on the vbus power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (hsotg->op_state == OTG_STATE_A_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) u32 hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) !!(hprt0 & HPRT0_PWR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (!(hprt0 & HPRT0_PWR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) hprt0 |= HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dwc2_enable_host_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * Initializes dynamic portions of the DWC_otg HCD state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct dwc2_host_chan *chan, *chan_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) hsotg->flags.d32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) hsotg->available_host_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) hsotg->non_periodic_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) hsotg->periodic_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) * Put all channels in the free channel list and clean up channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) hc_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) list_del_init(&chan->hc_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) chan = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) dwc2_hc_cleanup(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /* Initialize the DWC core for host mode operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) dwc2_core_host_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) int hub_addr, hub_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) chan->do_split = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) chan->xact_pos = qtd->isoc_split_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) chan->complete_split = qtd->complete_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) chan->hub_addr = (u8)hub_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) chan->hub_port = (u8)hub_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct dwc2_qtd *qtd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) struct dwc2_hcd_urb *urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) struct dwc2_hcd_iso_packet_desc *frame_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) switch (qtd->control_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) case DWC2_CONTROL_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) dev_vdbg(hsotg->dev, " Control setup transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) chan->do_ping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) chan->ep_is_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) chan->data_pid_start = DWC2_HC_PID_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) chan->xfer_dma = urb->setup_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) chan->xfer_buf = urb->setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) chan->xfer_len = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) case DWC2_CONTROL_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) dev_vdbg(hsotg->dev, " Control data transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) chan->data_pid_start = qtd->data_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) case DWC2_CONTROL_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * Direction is opposite of data direction or IN if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) dev_vdbg(hsotg->dev, " Control status transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (urb->length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) chan->ep_is_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) chan->ep_is_in =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) dwc2_hcd_is_pipe_out(&urb->pipe_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) chan->do_ping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) chan->data_pid_start = DWC2_HC_PID_DATA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) chan->xfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) chan->xfer_dma = hsotg->status_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) chan->xfer_buf = hsotg->status_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) chan->ep_type = USB_ENDPOINT_XFER_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) chan->ep_type = USB_ENDPOINT_XFER_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) chan->ep_type = USB_ENDPOINT_XFER_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (hsotg->params.dma_desc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) frame_desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) chan->xfer_dma = urb->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) chan->xfer_dma += frame_desc->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) qtd->isoc_split_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) chan->xfer_buf = urb->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) chan->xfer_buf += frame_desc->offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) qtd->isoc_split_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (chan->xfer_len <= 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static int dwc2_alloc_qh_dma_aligned_buf(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct dwc2_qh *qh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) struct dwc2_host_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (!hsotg->unaligned_cache ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (!qh->dw_align_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) GFP_ATOMIC | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (!qh->dw_align_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (!chan->ep_is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (qh->do_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) offset = chan->xfer_dma - qtd->urb->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) memcpy(qh->dw_align_buf, (u8 *)qtd->urb->buf + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) (chan->xfer_len > 188 ? 188 : chan->xfer_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) offset = chan->xfer_dma - qtd->urb->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) memcpy(qh->dw_align_buf, (u8 *)qtd->urb->buf + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) chan->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) DWC2_KMEM_UNALIGNED_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) dev_err(hsotg->dev, "can't map align_buf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) chan->align_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) chan->align_buf = qh->dw_align_buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define DWC2_USB_DMA_ALIGN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) static void dwc2_free_dma_aligned_buffer(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) void *stored_xfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) /* Restore urb->transfer_buffer from the end of the allocated area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) memcpy(&stored_xfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) dma_get_cache_alignment()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) sizeof(urb->transfer_buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (usb_urb_dir_in(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (usb_pipeisoc(urb->pipe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) length = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) length = urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) kfree(urb->transfer_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) urb->transfer_buffer = stored_xfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) void *kmalloc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) size_t kmalloc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (urb->num_sgs || urb->sg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) urb->transfer_buffer_length == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) * Allocate a buffer with enough padding for original transfer_buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) * pointer. This allocation is guaranteed to be aligned properly for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) * DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) kmalloc_size = urb->transfer_buffer_length +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) (dma_get_cache_alignment() - 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) sizeof(urb->transfer_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) if (!kmalloc_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) * Position value of original urb->transfer_buffer pointer to the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * of allocation for later referencing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) dma_get_cache_alignment()),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) &urb->transfer_buffer, sizeof(urb->transfer_buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (usb_urb_dir_out(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) memcpy(kmalloc_ptr, urb->transfer_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) urb->transfer_buffer = kmalloc_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* We assume setup_dma is always aligned; warn if not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) WARN_ON_ONCE(urb->setup_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) dwc2_free_dma_aligned_buffer(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) usb_hcd_unmap_urb_for_dma(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) dwc2_free_dma_aligned_buffer(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) * channel and initializes the host channel to perform the transactions. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) * host channel is removed from the free list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) * @hsotg: The HCD state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) * @qh: Transactions from the first QTD for this QH are selected and assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) * to a free host channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) struct dwc2_host_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) struct dwc2_hcd_urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) struct dwc2_qtd *qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) if (dbg_qh(qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (list_empty(&qh->qtd_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) dev_dbg(hsotg->dev, "No QTDs in QH list\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (list_empty(&hsotg->free_hc_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) dev_dbg(hsotg->dev, "No free channel to assign\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) hc_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) /* Remove host channel from free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) list_del_init(&chan->hc_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) qh->channel = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) qtd->in_process = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) * Use usb_pipedevice to determine device address. This address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) * 0 before the SET_ADDRESS command and the correct address afterward.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) chan->speed = qh->dev_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) chan->max_packet = qh->maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) chan->xfer_started = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) chan->error_state = (qtd->error_count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) chan->halt_on_queue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) chan->halt_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) chan->requests = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * The following values may be modified in the transfer type section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) * below. The xfer_len value may be reduced when the transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * started to accommodate the max widths of the XferSize and PktCnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * fields in the HCTSIZn register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (chan->ep_is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) chan->do_ping = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) chan->do_ping = qh->ping_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) chan->data_pid_start = qh->data_toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) chan->multi_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (urb->actual_length > urb->length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) !dwc2_hcd_is_pipe_in(&urb->pipe_info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) urb->actual_length = urb->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) chan->xfer_dma = urb->dma + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) chan->xfer_len = urb->length - urb->actual_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) chan->xfer_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) /* Set the split attributes if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (qh->do_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) dwc2_hc_init_split(hsotg, chan, qtd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) chan->do_split = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) /* Set the transfer attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) dwc2_hc_init_xfer(hsotg, chan, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* For non-dword aligned buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (hsotg->params.host_dma && (chan->xfer_dma & 0x3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) if (dwc2_alloc_qh_dma_aligned_buf(hsotg, qh, qtd, chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) "Failed to allocate memory to handle non-aligned buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* Add channel back to free list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) chan->align_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) chan->multi_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) list_add_tail(&chan->hc_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) &hsotg->free_hc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) qtd->in_process = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) qh->channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) * We assume that DMA is always aligned in other case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) * Warn if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) WARN_ON_ONCE(hsotg->params.host_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) (chan->xfer_dma & 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) chan->align_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) chan->ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) * This value may be modified when the transfer is started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) * to reflect the actual transfer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) chan->multi_count = qh->maxp_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) chan->desc_list_addr = qh->desc_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) chan->desc_list_sz = qh->desc_list_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) dwc2_hc_init(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) chan->qh = qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) * schedule and assigns them to available host channels. Called from the HCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) * interrupt handler functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) * @hsotg: The HCD state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * Return: The types of new transactions that were assigned to host channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) enum dwc2_transaction_type dwc2_hcd_select_transactions(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct list_head *qh_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #ifdef DWC2_DEBUG_SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) dev_vdbg(hsotg->dev, " Select Transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) /* Process entries in the periodic ready list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) qh_ptr = hsotg->periodic_sched_ready.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) while (qh_ptr != &hsotg->periodic_sched_ready) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) if (list_empty(&hsotg->free_hc_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) if (hsotg->available_host_channels <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) hsotg->available_host_channels--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) if (dwc2_assign_and_init_hc(hsotg, qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) * Move the QH from the periodic ready schedule to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) * periodic assigned schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) qh_ptr = qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) list_move_tail(&qh->qh_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) &hsotg->periodic_sched_assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) ret_val = DWC2_TRANSACTION_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) * Process entries in the inactive portion of the non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) * schedule. Some free host channels may not be used if they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * reserved for periodic transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) qh_ptr = hsotg->non_periodic_sched_inactive.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) if (!hsotg->params.uframe_sched &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) hsotg->non_periodic_channels >= num_channels -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) hsotg->periodic_channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (list_empty(&hsotg->free_hc_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) if (hsotg->params.uframe_sched) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) if (hsotg->available_host_channels < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) hsotg->available_host_channels--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (dwc2_assign_and_init_hc(hsotg, qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) * Move the QH from the non-periodic inactive schedule to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) * non-periodic active schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) qh_ptr = qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) list_move_tail(&qh->qh_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) &hsotg->non_periodic_sched_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) if (ret_val == DWC2_TRANSACTION_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) ret_val = DWC2_TRANSACTION_NON_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ret_val = DWC2_TRANSACTION_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) if (!hsotg->params.uframe_sched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) hsotg->non_periodic_channels++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * dwc2_queue_transaction() - Attempts to queue a single transaction request for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * a host channel associated with either a periodic or non-periodic transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * @hsotg: The HCD state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) * @chan: Host channel descriptor associated with either a periodic or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) * non-periodic transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) * for periodic transfers or the non-periodic Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) * for non-periodic transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) * Return: 1 if a request is queued and more requests may be needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) * complete the transfer, 0 if no more requests are required for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) * transfer, -1 if there is insufficient space in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) * This function assumes that there is space available in the appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) * request queue. For an OUT transfer or SETUP transaction in Slave mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) * it checks whether space is available in the appropriate Tx FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) struct dwc2_host_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) u16 fifo_dwords_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) if (chan->do_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) /* Put ourselves on the list to keep order straight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) list_move_tail(&chan->split_order_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) &hsotg->split_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) if (hsotg->params.host_dma && chan->qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) if (hsotg->params.dma_desc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (!chan->xfer_started ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) chan->qh->ping_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) } else if (!chan->xfer_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) dwc2_hc_start_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) chan->qh->ping_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) } else if (chan->halt_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) /* Don't queue a request if the channel has been halted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) } else if (chan->halt_on_queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) dwc2_hc_halt(hsotg, chan, chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) } else if (chan->do_ping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) if (!chan->xfer_started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) dwc2_hc_start_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) } else if (!chan->ep_is_in ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) chan->data_pid_start == DWC2_HC_PID_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if ((fifo_dwords_avail * 4) >= chan->max_packet) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) if (!chan->xfer_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) dwc2_hc_start_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) } else if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) retval = dwc2_hc_continue_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) retval = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) if (!chan->xfer_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) dwc2_hc_start_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) } else if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) retval = dwc2_hc_continue_transfer(hsotg, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) * Processes periodic channels for the next frame and queues transactions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) * these channels to the DWC_otg controller. After queueing transactions, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) * to queue as Periodic Tx FIFO or request queue space becomes available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) struct list_head *qh_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) u32 tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) u32 fspcavail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) bool no_queue_space = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) bool no_fifo_space = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) u32 qspcavail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) /* If empty list then just adjust interrupt enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (list_empty(&hsotg->periodic_sched_assigned))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) if (dbg_perio())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) tx_status = dwc2_readl(hsotg, HPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) TXSTS_QSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if (dbg_perio()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) qspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) fspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) qh_ptr = hsotg->periodic_sched_assigned.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) while (qh_ptr != &hsotg->periodic_sched_assigned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) tx_status = dwc2_readl(hsotg, HPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) TXSTS_QSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) if (qspcavail == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) no_queue_space = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) if (!qh->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) qh_ptr = qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /* Make sure EP's TT buffer is clean before queueing qtds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) if (qh->tt_buffer_dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) qh_ptr = qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) * Set a flag if we're queuing high-bandwidth in slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * The flag prevents any halts to get into the request queue in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) * the middle of multiple high-bandwidth packets getting queued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) if (!hsotg->params.host_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) qh->channel->multi_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) hsotg->queuing_high_bandwidth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) no_fifo_space = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) * In Slave mode, stay on the current transfer until there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) * nothing more to do or the high-bandwidth request count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) * reached. In DMA mode, only need to queue one request. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) * controller automatically handles multiple packets for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) * high-bandwidth transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) if (hsotg->params.host_dma || status == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) qh->channel->requests == qh->channel->multi_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) qh_ptr = qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) * Move the QH from the periodic assigned schedule to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) * the periodic queued schedule
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) list_move_tail(&qh->qh_list_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) &hsotg->periodic_sched_queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* done queuing high bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) hsotg->queuing_high_bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (no_queue_space || no_fifo_space ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) (!hsotg->params.host_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) !list_empty(&hsotg->periodic_sched_assigned))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * May need to queue more transactions as the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) * queue or Tx FIFO empties. Enable the periodic Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) * FIFO empty interrupt. (Always use the half-empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * level to ensure that new requests are loaded as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) * soon as possible.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) if (!(gintmsk & GINTSTS_PTXFEMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) gintmsk |= GINTSTS_PTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) * Disable the Tx FIFO empty interrupt since there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) * no more transactions that need to be queued right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) * now. This function is called from interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * handlers to queue more transactions as transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * states change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) if (gintmsk & GINTSTS_PTXFEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) gintmsk &= ~GINTSTS_PTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) * Processes active non-periodic channels and queues transactions for these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) * channels to the DWC_otg controller. After queueing transactions, the NP Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) * FIFO Empty interrupt is enabled if there are more transactions to queue as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) * FIFO Empty interrupt is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) struct list_head *orig_qh_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) u32 tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) u32 qspcavail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) u32 fspcavail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) int no_queue_space = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) int no_fifo_space = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) int more_to_do = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) tx_status = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) TXSTS_QSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) qspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) fspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) * Keep track of the starting point. Skip over the start-of-list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) * entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) orig_qh_ptr = hsotg->non_periodic_qh_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) * Process once through the active list or until no more space is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) * available in the request queue or the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) tx_status = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) TXSTS_QSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (!hsotg->params.host_dma && qspcavail == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) no_queue_space = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) qh_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) if (!qh->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) /* Make sure EP's TT buffer is clean before queueing qtds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (qh->tt_buffer_dirty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) if (status > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) more_to_do = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) } else if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) no_fifo_space = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) /* Advance to next QH, skipping start-of-list entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) if (hsotg->non_periodic_qh_ptr ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) &hsotg->non_periodic_sched_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) hsotg->non_periodic_qh_ptr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) hsotg->non_periodic_qh_ptr->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) if (!hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) tx_status = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) TXSTS_QSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) TXSTS_FSPCAVAIL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) " NP Tx Req Queue Space Avail (after queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) qspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) " NP Tx FIFO Space Avail (after queue): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) fspcavail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) if (more_to_do || no_queue_space || no_fifo_space) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) * May need to queue more transactions as the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) * queue or Tx FIFO empties. Enable the non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) * Tx FIFO empty interrupt. (Always use the half-empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) * level to ensure that new requests are loaded as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * soon as possible.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) gintmsk |= GINTSTS_NPTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) * Disable the Tx FIFO empty interrupt since there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) * no more transactions that need to be queued right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) * now. This function is called from interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) * handlers to queue more transactions as transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) * states change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) gintmsk &= ~GINTSTS_NPTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) * dwc2_hcd_queue_transactions() - Processes the currently active host channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) * and queues transactions for these channels to the DWC_otg controller. Called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) * from the HCD interrupt handler functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * @hsotg: The HCD state structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) * or both)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) enum dwc2_transaction_type tr_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) #ifdef DWC2_DEBUG_SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) dev_vdbg(hsotg->dev, "Queue Transactions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* Process host channels associated with periodic transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) if (tr_type == DWC2_TRANSACTION_PERIODIC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) tr_type == DWC2_TRANSACTION_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) dwc2_process_periodic_channels(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /* Process host channels associated with non-periodic transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) tr_type == DWC2_TRANSACTION_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if (!list_empty(&hsotg->non_periodic_sched_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) dwc2_process_non_periodic_channels(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) * Ensure NP Tx FIFO empty interrupt is disabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) * there are no non-periodic transfers to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) gintmsk &= ~GINTSTS_NPTXFEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) static void dwc2_conn_id_status_change(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) wf_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) u32 count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) u32 gotgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) dev_dbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) if (!hsotg->ll_phy_enabled && dwc2_is_host_mode(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) dwc2_lowlevel_phy_enable(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) gotgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) !!(gotgctl & GOTGCTL_CONID_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) /* B-Device connector (Device Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) if (gotgctl & GOTGCTL_CONID_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) dwc2_vbus_supply_exit(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /* Wait for switch to device mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) dev_dbg(hsotg->dev, "connId B\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if (hsotg->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) dev_info(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) "Do port resume before switching to device mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) dwc2_port_resume(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) while (!dwc2_is_device_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) dev_info(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) "Waiting for Peripheral Mode, Mode=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dwc2_is_host_mode(hsotg) ? "Host" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) "Peripheral");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) * Sometimes the initial GOTGCTRL read is wrong, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) * check it again and jump to host mode if that was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) * the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) gotgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (!(gotgctl & GOTGCTL_CONID_B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) goto host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) if (++count > 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (count > 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) "Connection id status change timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) hsotg->op_state = OTG_STATE_B_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) dwc2_core_init(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) dwc2_enable_global_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) dwc2_hsotg_core_init_disconnected(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* Enable ACG feature in device mode,if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dwc2_enable_acg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) dwc2_hsotg_core_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) /* A-Device connector (Host Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) dev_dbg(hsotg->dev, "connId A\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) while (!dwc2_is_host_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) dwc2_is_host_mode(hsotg) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) "Host" : "Peripheral");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (++count > 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) if (count > 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) "Connection id status change timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) dwc2_hsotg_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) hsotg->op_state = OTG_STATE_A_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /* Initialize the Core for Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) dwc2_core_init(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) dwc2_enable_global_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) dwc2_hcd_start(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) static void dwc2_wakeup_detected(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) dev_dbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) * so that OPT tests pass with all PHYs.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) hprt0 &= ~HPRT0_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) dwc2_readl(hsotg, HPRT0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dwc2_hcd_rem_wakeup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) hsotg->bus_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) /* Change to L0 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) return hcd->self.b_hnp_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) /* Must NOT be called with interrupt disabled or spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) u32 pcgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) u32 gotgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) dev_dbg(hsotg->dev, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) gotgctl = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) gotgctl |= GOTGCTL_HSTSETHNPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) dwc2_writel(hsotg, gotgctl, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) hsotg->op_state = OTG_STATE_A_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) hprt0 |= HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) hsotg->bus_suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) * If power_down is supported, Phy clock will be suspended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) * after registers are backuped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (!hsotg->params.power_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) /* Suspend the Phy Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) pcgctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) pcgctl |= PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) dwc2_writel(hsotg, pcgctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) /* For HNP the bus must be suspended for at least 200ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) if (dwc2_host_is_b_hnp_enabled(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) pcgctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) pcgctl &= ~PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) dwc2_writel(hsotg, pcgctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* Must NOT be called with interrupt disabled or spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) u32 pcgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * If power_down is supported, Phy clock is already resumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) * after registers restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) if (!hsotg->params.power_down) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) pcgctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) pcgctl &= ~PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) dwc2_writel(hsotg, pcgctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) hprt0 |= HPRT0_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) hprt0 &= ~HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) msleep(USB_RESUME_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) hsotg->bus_suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) /* Handles hub class-specific requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) u16 wvalue, u16 windex, char *buf, u16 wlength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) struct usb_hub_descriptor *hub_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) u32 port_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) u32 pcgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) u32 pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) switch (typereq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) case ClearHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) switch (wvalue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) case C_HUB_LOCAL_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) case C_HUB_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) /* Nothing required here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) "ClearHubFeature request %1xh unknown\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) wvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) case ClearPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) if (wvalue != USB_PORT_FEAT_L1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) if (!windex || windex > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) switch (wvalue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) case USB_PORT_FEAT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) hprt0 |= HPRT0_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) if (hsotg->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) if (hsotg->hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) dwc2_exit_hibernation(hsotg, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) dwc2_port_resume(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) "ClearPortFeature USB_PORT_FEAT_POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) pwr = hprt0 & HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) hprt0 &= ~HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) if (pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) dwc2_vbus_supply_exit(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) case USB_PORT_FEAT_INDICATOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /* Port indicator not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) case USB_PORT_FEAT_C_CONNECTION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) * Clears driver's internal Connect Status Change flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) hsotg->flags.b.port_connect_status_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) case USB_PORT_FEAT_C_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) /* Clears driver's internal Port Reset Change flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) hsotg->flags.b.port_reset_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) case USB_PORT_FEAT_C_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) * Clears the driver's internal Port Enable/Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) * Change flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) hsotg->flags.b.port_enable_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) case USB_PORT_FEAT_C_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) * Clears the driver's internal Port Suspend Change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) * flag, which is set when resume signaling on the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) * port is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) hsotg->flags.b.port_suspend_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) case USB_PORT_FEAT_C_PORT_L1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) hsotg->flags.b.port_l1_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) case USB_PORT_FEAT_C_OVER_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) hsotg->flags.b.port_over_current_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) "ClearPortFeature request %1xh unknown or unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) wvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) case GetHubDescriptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) dev_dbg(hsotg->dev, "GetHubDescriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) hub_desc = (struct usb_hub_descriptor *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) hub_desc->bDescLength = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) hub_desc->bDescriptorType = USB_DT_HUB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) hub_desc->bNbrPorts = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) hub_desc->wHubCharacteristics =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) cpu_to_le16(HUB_CHAR_COMMON_LPSM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) HUB_CHAR_INDV_PORT_OCPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) hub_desc->bPwrOn2PwrGood = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) hub_desc->bHubContrCurrent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) hub_desc->u.hs.DeviceRemovable[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) hub_desc->u.hs.DeviceRemovable[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) case GetHubStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) dev_dbg(hsotg->dev, "GetHubStatus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) memset(buf, 0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) case GetPortStatus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) hsotg->flags.d32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) if (!windex || windex > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) port_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) if (hsotg->flags.b.port_connect_status_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) port_status |= USB_PORT_STAT_C_CONNECTION << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) if (hsotg->flags.b.port_enable_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) port_status |= USB_PORT_STAT_C_ENABLE << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) if (hsotg->flags.b.port_suspend_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) port_status |= USB_PORT_STAT_C_SUSPEND << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) if (hsotg->flags.b.port_l1_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) port_status |= USB_PORT_STAT_C_L1 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) if (hsotg->flags.b.port_reset_change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) port_status |= USB_PORT_STAT_C_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) if (hsotg->flags.b.port_over_current_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) dev_warn(hsotg->dev, "Overcurrent change detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) if (!hsotg->flags.b.port_connect_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) * The port is disconnected, which means the core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) * either in device mode or it soon will be. Just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) * return 0's for the remainder of the port status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) * since the port register can't be read if the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * is in device mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) *(__le32 *)buf = cpu_to_le32(port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) if (hprt0 & HPRT0_CONNSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) port_status |= USB_PORT_STAT_CONNECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) if (hprt0 & HPRT0_ENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) port_status |= USB_PORT_STAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) if (hprt0 & HPRT0_SUSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) port_status |= USB_PORT_STAT_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) if (hprt0 & HPRT0_OVRCURRACT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) port_status |= USB_PORT_STAT_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) if (hprt0 & HPRT0_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) port_status |= USB_PORT_STAT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) if (hprt0 & HPRT0_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) port_status |= USB_PORT_STAT_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) if (speed == HPRT0_SPD_HIGH_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) port_status |= USB_PORT_STAT_HIGH_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) else if (speed == HPRT0_SPD_LOW_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) port_status |= USB_PORT_STAT_LOW_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) if (hprt0 & HPRT0_TSTCTL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) port_status |= USB_PORT_STAT_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) if (hsotg->params.dma_desc_fs_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) * Enable descriptor DMA only if a full speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) * device is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) if (hsotg->new_connection &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) ((port_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) (USB_PORT_STAT_CONNECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) USB_PORT_STAT_HIGH_SPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) USB_PORT_STAT_LOW_SPEED)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) USB_PORT_STAT_CONNECTION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) hsotg->params.dma_desc_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) hcfg |= HCFG_DESCDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) dwc2_writel(hsotg, hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) hsotg->new_connection = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) *(__le32 *)buf = cpu_to_le32(port_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) case SetHubFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) dev_dbg(hsotg->dev, "SetHubFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) /* No HUB features supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) case SetPortFeature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) dev_dbg(hsotg->dev, "SetPortFeature\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) if (!hsotg->flags.b.port_connect_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * The port is disconnected, which means the core is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * either in device mode or it soon will be. Just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) * return without doing anything since the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) * register can't be written if the core is in device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) switch (wvalue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) case USB_PORT_FEAT_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) if (windex != hsotg->otg_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) dwc2_enter_hibernation(hsotg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) dwc2_port_suspend(hsotg, windex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) case USB_PORT_FEAT_POWER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) "SetPortFeature - USB_PORT_FEAT_POWER\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) pwr = hprt0 & HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) hprt0 |= HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) if (!pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) dwc2_vbus_supply_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) case USB_PORT_FEAT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) hsotg->hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) dwc2_exit_hibernation(hsotg, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) "SetPortFeature - USB_PORT_FEAT_RESET\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) pcgctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) dwc2_writel(hsotg, pcgctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) /* ??? Original driver does this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) dwc2_writel(hsotg, 0, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) pwr = hprt0 & HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) /* Clear suspend bit if resetting from suspend state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) hprt0 &= ~HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) * When B-Host the Port reset bit is set in the Start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) * HCD Callback function, so that the reset is started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) * within 1ms of the HNP success interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) if (!dwc2_hcd_is_b_host(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) hprt0 |= HPRT0_PWR | HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) "In host mode, hprt0=%08x\n", hprt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) if (!pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) dwc2_vbus_supply_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) hprt0 &= ~HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) hsotg->lx_state = DWC2_L0; /* Now back to On state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) case USB_PORT_FEAT_INDICATOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) /* Not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) case USB_PORT_FEAT_TEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) "SetPortFeature - USB_PORT_FEAT_TEST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) hprt0 &= ~HPRT0_TSTCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) "SetPortFeature %1xh unknown or unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) wvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) typereq, windex, wvalue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) if (port != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) retval = (hsotg->flags.b.port_connect_status_change ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) hsotg->flags.b.port_reset_change ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) hsotg->flags.b.port_enable_change ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) hsotg->flags.b.port_suspend_change ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) hsotg->flags.b.port_over_current_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) hsotg->flags.b.port_connect_status_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) dev_dbg(hsotg->dev, " port_reset_change: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) hsotg->flags.b.port_reset_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) dev_dbg(hsotg->dev, " port_enable_change: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) hsotg->flags.b.port_enable_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) hsotg->flags.b.port_suspend_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) hsotg->flags.b.port_over_current_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) u32 hfnum = dwc2_readl(hsotg, HFNUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) #ifdef DWC2_DEBUG_SOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) u32 hprt = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) u32 hfir = dwc2_readl(hsotg, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) u32 hfnum = dwc2_readl(hsotg, HFNUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) unsigned int us_per_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) unsigned int frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) unsigned int remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) unsigned int interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) unsigned int phy_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) /* High speed has 125 us per (micro) frame; others are 1 ms per */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /* Extract fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) * Number of phy clocks since the last tick of the frame number after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) * "us" has passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) phy_clks = (interval - remaining) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) DIV_ROUND_UP(interval * us, us_per_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) return dwc2_frame_num_inc(frame_number, phy_clks / interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) return hsotg->op_state == OTG_STATE_B_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) int iso_desc_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) struct dwc2_hcd_urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) if (urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) urb->packet_count = iso_desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) return urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) struct dwc2_hcd_urb *urb, u8 dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) u8 ep_num, u8 ep_type, u8 ep_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) u16 maxp, u16 maxp_mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) if (dbg_perio() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) ep_type == USB_ENDPOINT_XFER_BULK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) ep_type == USB_ENDPOINT_XFER_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) urb->pipe_info.dev_addr = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) urb->pipe_info.ep_num = ep_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) urb->pipe_info.pipe_type = ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) urb->pipe_info.pipe_dir = ep_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) urb->pipe_info.maxp = maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) urb->pipe_info.maxp_mult = maxp_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) * NOTE: This function will be removed once the peripheral controller code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) * is integrated and the driver is stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) struct dwc2_host_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) struct dwc2_hcd_urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) struct dwc2_qtd *qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) u32 np_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) u32 p_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) dev_dbg(hsotg->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) "************************************************************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) dev_dbg(hsotg->dev, "HCD State:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) chan = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) dev_dbg(hsotg->dev, " Channel %d:\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) chan->dev_addr, chan->ep_num, chan->ep_is_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) dev_dbg(hsotg->dev, " data_pid_start: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) chan->data_pid_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) dev_dbg(hsotg->dev, " xfer_started: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) chan->xfer_started);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) (unsigned long)chan->xfer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) chan->halt_on_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) dev_dbg(hsotg->dev, " halt_pending: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) chan->halt_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) dev_dbg(hsotg->dev, " complete_split: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) chan->complete_split);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) if (chan->xfer_started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) hfnum = dwc2_readl(hsotg, HFNUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) hcchar = dwc2_readl(hsotg, HCCHAR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) hcint = dwc2_readl(hsotg, HCINT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) if (!(chan->xfer_started && chan->qh))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) if (!qtd->in_process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) urb = qtd->urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) dev_dbg(hsotg->dev, " URB Info:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) qtd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) if (urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) " Dev: %d, EP: %d %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) dwc2_hcd_get_dev_addr(&urb->pipe_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) dwc2_hcd_get_ep_num(&urb->pipe_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) "IN" : "OUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) " Max packet size: %d (%d mult)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dwc2_hcd_get_maxp(&urb->pipe_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) dwc2_hcd_get_maxp_mult(&urb->pipe_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) " transfer_buffer: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) urb->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) " transfer_dma: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) (unsigned long)urb->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) " transfer_buffer_length: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) urb->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) dev_dbg(hsotg->dev, " actual_length: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) hsotg->non_periodic_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) dev_dbg(hsotg->dev, " periodic_channels: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) hsotg->periodic_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) p_tx_status = dwc2_readl(hsotg, HPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) dwc2_dump_global_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) dwc2_dump_host_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) "************************************************************\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) dev_dbg(hsotg->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) struct wrapper_priv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) struct dwc2_hsotg *hsotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) /* Gets the dwc2_hsotg from a usb_hcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) struct wrapper_priv_data *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) p = (struct wrapper_priv_data *)&hcd->hcd_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) return p->hsotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) * This will get the dwc2_tt structure (and ttport) associated with the given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) * context (which is really just a struct urb pointer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) * The first time this is called for a given TT we allocate memory for our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) * structure. When everyone is done and has called dwc2_host_put_tt_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) * then the refcount for the structure will go to 0 and we'll free it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) * @hsotg: The HCD state structure for the DWC OTG controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) * @context: The priv pointer from a struct dwc2_hcd_urb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) * @mem_flags: Flags for allocating memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) * @ttport: We'll return this device's port number here. That's used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) * reference into the bitmap if we're on a multi_tt hub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) * Return: a pointer to a struct dwc2_tt. Don't forget to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) gfp_t mem_flags, int *ttport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) struct urb *urb = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) struct dwc2_tt *dwc_tt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) if (urb->dev->tt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) *ttport = urb->dev->ttport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) dwc_tt = urb->dev->tt->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) if (!dwc_tt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) size_t bitmap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) * For single_tt we need one schedule. For multi_tt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) * we need one per port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) sizeof(dwc_tt->periodic_bitmaps[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) if (urb->dev->tt->multi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) bitmap_size *= urb->dev->tt->hub->maxchild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) if (!dwc_tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) dwc_tt->usb_tt = urb->dev->tt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) dwc_tt->usb_tt->hcpriv = dwc_tt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) dwc_tt->refcount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) return dwc_tt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) * of the structure are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) * It's OK to call this with NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) * @hsotg: The HCD state structure for the DWC OTG controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) /* Model kfree and make put of NULL a no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) if (!dwc_tt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) WARN_ON(dwc_tt->refcount < 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) dwc_tt->refcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) if (!dwc_tt->refcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) dwc_tt->usb_tt->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) kfree(dwc_tt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) struct urb *urb = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) return urb->dev->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) struct usb_bus *bus = hcd_to_bus(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) if (urb->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) bus->bandwidth_allocated += bw / urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) bus->bandwidth_isoc_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) bus->bandwidth_int_reqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) struct usb_bus *bus = hcd_to_bus(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) if (urb->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) bus->bandwidth_allocated -= bw / urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) bus->bandwidth_isoc_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) bus->bandwidth_int_reqs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) * Sets the final status of an URB and returns it to the upper layer. Any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) * required cleanup of the URB is performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) * Must be called with interrupt disabled and spinlock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) if (!qtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) if (!qtd->urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) urb = qtd->urb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) if (!urb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) if (dbg_urb(urb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) dev_vdbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) "%s: urb %p device %d ep %d-%s status %d actual %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) __func__, urb, usb_pipedevice(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) usb_pipeendpoint(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) usb_pipein(urb->pipe) ? "IN" : "OUT", status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) for (i = 0; i < urb->number_of_packets; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) urb->iso_frame_desc[i].actual_length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) dwc2_hcd_urb_get_iso_desc_actual_length(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) qtd->urb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) urb->iso_frame_desc[i].status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) for (i = 0; i < urb->number_of_packets; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) i, urb->iso_frame_desc[i].status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) urb->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) urb->actual_length < urb->transfer_buffer_length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) urb->status = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) struct usb_host_endpoint *ep = urb->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) if (ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) dwc2_hcd_get_ep_bandwidth(hsotg, ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) kfree(qtd->urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) qtd->urb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) * Work queue function for starting the HCD when A-Cable is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) static void dwc2_hcd_start_func(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) start_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) dwc2_host_start(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) * Reset work queue function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) static void dwc2_hcd_reset_func(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) reset_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) dev_dbg(hsotg->dev, "USB RESET function called\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) hprt0 &= ~HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) hsotg->flags.b.port_reset_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) static void dwc2_hcd_phy_reset_func(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) phy_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) ret = phy_reset(hsotg->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) dev_warn(hsotg->dev, "PHY reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) * Linux HC Driver Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) * =========================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) * Initializes the DWC_otg controller and its root hub and prepares it for host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) * mode operation. Activates the root port. Returns 0 on success and a negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) * error code on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) static int _dwc2_hcd_start(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) struct usb_bus *bus = hcd_to_bus(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) hcd->state = HC_STATE_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) if (dwc2_is_device_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) return 0; /* why 0 ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) dwc2_hcd_reinit(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) /* Has vbus power been turned on in dwc2_core_host_init ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) if (hprt0 & HPRT0_PWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) /* Enable external vbus supply before resuming root hub */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) ret = dwc2_vbus_supply_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) /* Initialize and connect root hub if one is not already attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) if (bus->root_hub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) /* Inform the HUB driver to resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) usb_hcd_resume_root_hub(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) * stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) static void _dwc2_hcd_stop(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) /* Turn off all host-specific interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) dwc2_disable_host_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) /* Wait for interrupt processing to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) synchronize_irq(hcd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) /* Ensure hcd is disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) dwc2_hcd_disconnect(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) dwc2_hcd_stop(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) hsotg->lx_state = DWC2_L3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) hcd->state = HC_STATE_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) /* keep balanced supply init/exit by checking HPRT0_PWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) if (hprt0 & HPRT0_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) dwc2_vbus_supply_exit(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) u32 pcgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) if (dwc2_is_device_mode(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) if (hsotg->lx_state != DWC2_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) if (!HCD_HW_ACCESSIBLE(hcd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) hsotg->flags.b.port_connect_status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) goto skip_power_saving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) * Drive USB suspend and disable port Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) * if usb bus is not suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) if (!hsotg->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) if (hprt0 & HPRT0_CONNSTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) hprt0 |= HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) hprt0 &= ~HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) dwc2_vbus_supply_exit(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) pcgctl = readl(hsotg->regs + PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) pcgctl |= PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) writel(pcgctl, hsotg->regs + PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) /* Enter partial_power_down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) ret = dwc2_enter_partial_power_down(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) if (ret != -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) "enter partial_power_down failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) goto skip_power_saving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) /* After entering partial_power_down, hardware is no more accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) /* Ask phy to be suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) if (!IS_ERR_OR_NULL(hsotg->uphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) usb_phy_set_suspend(hsotg->uphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) skip_power_saving:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) hsotg->lx_state = DWC2_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) static int _dwc2_hcd_resume(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) u32 pcgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) if (dwc2_is_device_mode(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) if (hsotg->lx_state != DWC2_L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) * Enable power if not already done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) * This must not be spinlocked since duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) * of this call is unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) if (!IS_ERR_OR_NULL(hsotg->uphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) usb_phy_set_suspend(hsotg->uphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) * Set HW accessible bit before powering on the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) * since an interrupt may rise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) /* Exit partial_power_down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) ret = dwc2_exit_partial_power_down(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) if (ret && (ret != -ENOTSUPP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) dev_err(hsotg->dev, "exit partial_power_down failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) pcgctl = readl(hsotg->regs + PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) pcgctl &= ~PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) writel(pcgctl, hsotg->regs + PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) if (hsotg->bus_suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) hsotg->flags.b.port_suspend_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) dwc2_port_resume(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) dwc2_vbus_supply_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) /* Wait for controller to correctly update D+/D- level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) * Clear Port Enable and Port Status changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) * Enable Port Power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) HPRT0_ENACHG, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) /* Wait for controller to detect Port Connect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) usleep_range(5000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) /* Returns the current frame number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) return dwc2_hcd_get_frame_number(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) char *fn_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) char *pipetype = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) char *speed = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) dev_vdbg(hsotg->dev, " Device address: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) usb_pipedevice(urb->pipe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) usb_pipeendpoint(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) usb_pipein(urb->pipe) ? "IN" : "OUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) switch (usb_pipetype(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) pipetype = "CONTROL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) pipetype = "BULK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) pipetype = "INTERRUPT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) pipetype = "ISOCHRONOUS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) "IN" : "OUT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) switch (urb->dev->speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) speed = "HIGH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) speed = "FULL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) case USB_SPEED_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) speed = "LOW";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) speed = "UNKNOWN";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) usb_endpoint_maxp(&urb->ep->desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) usb_endpoint_maxp_mult(&urb->ep->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) urb->transfer_buffer_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) urb->transfer_buffer, (unsigned long)urb->transfer_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) urb->setup_packet, (unsigned long)urb->setup_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) for (i = 0; i < urb->number_of_packets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) urb->iso_frame_desc[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) urb->iso_frame_desc[i].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) * Starts processing a USB transfer request specified by a USB Request Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) * (URB). mem_flags indicates the type of memory allocation to use while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) * processing this URB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) gfp_t mem_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) struct usb_host_endpoint *ep = urb->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) struct dwc2_hcd_urb *dwc2_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) int alloc_bandwidth = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) u8 ep_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) u32 tflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) bool qh_allocated = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) struct dwc2_qtd *qtd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) if (dbg_urb(urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) alloc_bandwidth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) switch (usb_pipetype(urb->pipe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) case PIPE_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) ep_type = USB_ENDPOINT_XFER_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) case PIPE_ISOCHRONOUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) ep_type = USB_ENDPOINT_XFER_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) case PIPE_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) ep_type = USB_ENDPOINT_XFER_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) case PIPE_INTERRUPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) ep_type = USB_ENDPOINT_XFER_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) if (!dwc2_urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) usb_pipeendpoint(urb->pipe), ep_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) usb_pipein(urb->pipe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) usb_endpoint_maxp(&ep->desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) usb_endpoint_maxp_mult(&ep->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) buf = urb->transfer_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) if (hcd_uses_dma(hcd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) if (!buf && (urb->transfer_dma & 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) "%s: unaligned transfer with no transfer_buffer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) if (!(urb->transfer_flags & URB_NO_INTERRUPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) tflags |= URB_GIVEBACK_ASAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) if (urb->transfer_flags & URB_ZERO_PACKET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) tflags |= URB_SEND_ZERO_PACKET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) dwc2_urb->priv = urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) dwc2_urb->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) dwc2_urb->dma = urb->transfer_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) dwc2_urb->length = urb->transfer_buffer_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) dwc2_urb->setup_packet = urb->setup_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) dwc2_urb->setup_dma = urb->setup_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) dwc2_urb->flags = tflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) dwc2_urb->interval = urb->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) dwc2_urb->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) for (i = 0; i < urb->number_of_packets; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) urb->iso_frame_desc[i].offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) urb->iso_frame_desc[i].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) urb->hcpriv = dwc2_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) qh = (struct dwc2_qh *)ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) /* Create QH for the endpoint if it doesn't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) if (!qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) if (!qh) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) ep->hcpriv = qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) qh_allocated = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) qtd = kzalloc(sizeof(*qtd), mem_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) if (!qtd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) retval = usb_hcd_link_urb_to_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) if (alloc_bandwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) dwc2_allocate_bus_bandwidth(hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) dwc2_hcd_get_ep_bandwidth(hsotg, ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) fail3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) dwc2_urb->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) if (qh_allocated && qh->channel && qh->channel->qh == qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) qh->channel->qh = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) kfree(qtd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) if (qh_allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) struct dwc2_qtd *qtd2, *qtd2_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) ep->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) dwc2_hcd_qh_unlink(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) /* Free each QTD in the QH's QTD list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) qtd_list_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) dwc2_hcd_qh_free(hsotg, qh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) kfree(dwc2_urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) rc = usb_hcd_check_unlink_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) if (!urb->hcpriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) usb_hcd_unlink_urb_from_ep(hcd, urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) kfree(urb->hcpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) urb->hcpriv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) /* Higher layer software sets URB status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) usb_hcd_giveback_urb(hcd, urb, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) * Frees resources in the DWC_otg controller related to a given endpoint. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) * clears state in the HCD related to the endpoint. Any URBs for the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) * must already be dequeued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) ep->desc.bEndpointAddress, ep->hcpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) dwc2_hcd_endpoint_disable(hsotg, ep, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) * Resets endpoint specific parameter values, in current version used to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) * the data toggle (as a WA). This function can be called from usb_clear_halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) * routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) ep->desc.bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) dwc2_hcd_endpoint_reset(hsotg, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) * This function is called by the USB core when an interrupt occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) return dwc2_handle_hcd_intr(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) * Creates Status Change bitmap for the root hub and root port. The bitmap is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) * is the status change indicator for the single root port. Returns 1 if either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) * change indicator is 1, otherwise returns 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) return buf[0] != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) /* Handles hub class-specific requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) u16 windex, char *buf, u16 wlength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) wvalue, windex, buf, wlength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) /* Handles hub TT buffer clear completions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) struct usb_host_endpoint *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) struct dwc2_qh *qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) qh = ep->hcpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) if (!qh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) qh->tt_buffer_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) if (hsotg->flags.b.port_connect_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) * HPRT0_SPD_HIGH_SPEED: high speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) * HPRT0_SPD_FULL_SPEED: full speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) if (hsotg->params.speed == speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) hsotg->params.speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) queue_work(hsotg->wq_otg, &hsotg->wf_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) if (!hsotg->params.change_speed_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) * On removal, set speed to default high-speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) udev->parent->speed < USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) dev_info(hsotg->dev, "Set speed to default high-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) if (!hsotg->params.change_speed_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) if (udev->speed == USB_SPEED_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) dev_info(hsotg->dev, "Set speed to high-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) } else if ((udev->speed == USB_SPEED_FULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) udev->speed == USB_SPEED_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) * Change speed setting to full-speed if there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) * a full-speed or low-speed device plugged in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) dev_info(hsotg->dev, "Set speed to full-speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) static struct hc_driver dwc2_hc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) .description = "dwc2_hsotg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) .product_desc = "DWC OTG Controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) .hcd_priv_size = sizeof(struct wrapper_priv_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) .irq = _dwc2_hcd_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) .start = _dwc2_hcd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) .stop = _dwc2_hcd_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) .urb_enqueue = _dwc2_hcd_urb_enqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) .urb_dequeue = _dwc2_hcd_urb_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) .endpoint_disable = _dwc2_hcd_endpoint_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) .endpoint_reset = _dwc2_hcd_endpoint_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) .get_frame_number = _dwc2_hcd_get_frame_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) .hub_status_data = _dwc2_hcd_hub_status_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) .hub_control = _dwc2_hcd_hub_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) .bus_suspend = _dwc2_hcd_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) .bus_resume = _dwc2_hcd_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) .map_urb_for_dma = dwc2_map_urb_for_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) * Frees secondary storage associated with the dwc2_hsotg structure contained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) * in the struct usb_hcd field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) u32 ahbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) u32 dctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) /* Free memory for QH/QTD lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) /* Free memory for the host channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) for (i = 0; i < MAX_EPS_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) if (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) i, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) hsotg->hc_ptr_array[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) kfree(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) if (hsotg->status_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) hsotg->status_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) hsotg->status_buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) hsotg->status_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) kfree(hsotg->status_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) hsotg->status_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) ahbcfg = dwc2_readl(hsotg, GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) dwc2_writel(hsotg, ahbcfg, GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) dwc2_writel(hsotg, 0, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) dctl |= DCTL_SFTDISCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) if (hsotg->wq_otg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) if (!cancel_work_sync(&hsotg->wf_otg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) flush_workqueue(hsotg->wq_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) destroy_workqueue(hsotg->wq_otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) cancel_work_sync(&hsotg->phy_reset_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) del_timer(&hsotg->wkp_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) /* Turn off all host-specific interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) dwc2_disable_host_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) dwc2_hcd_free(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) * Initializes the HCD. This function allocates memory for and initializes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) * USB bus with the core and calls the hc_driver->start() function. It returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) * a negative error on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) struct platform_device *pdev = to_platform_device(hsotg->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) struct dwc2_host_chan *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) int i, num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) sizeof(*hsotg->frame_num_array),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) if (!hsotg->frame_num_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) hsotg->last_frame_num_array =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) kcalloc(FRAME_NUM_ARRAY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) if (!hsotg->last_frame_num_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) hsotg->last_frame_num = HFNUM_MAX_FRNUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) /* Check if the bus driver or platform code has setup a dma_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) if (hsotg->params.host_dma &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) !hsotg->dev->dma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) "dma_mask not set, disabling DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) hsotg->params.host_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) /* Set device flags indicating whether the HCD supports DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) dev_warn(hsotg->dev, "can't set DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) if (hsotg->params.change_speed_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) dwc2_hc_driver.free_dev = dwc2_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) dwc2_hc_driver.reset_device = dwc2_reset_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) dwc2_hc_driver.flags |= HCD_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) if (!hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) hcd->rsrc_start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) hcd->rsrc_len = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) hsotg->priv = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) * Disable the global interrupt until all the interrupt handlers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) * installed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) dwc2_disable_global_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) /* Initialize the DWC_otg core, and select the Phy type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) retval = dwc2_core_init(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) /* Create new workqueue and init work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) if (!hsotg->wq_otg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) dev_err(hsotg->dev, "Failed to create workqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) /* Initialize the non-periodic schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) /* Initialize the periodic schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) INIT_LIST_HEAD(&hsotg->split_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) * Create a host channel descriptor for each host channel implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) * in the controller. Initialize the channel descriptor array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) INIT_LIST_HEAD(&hsotg->free_hc_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) num_channels = hsotg->params.host_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) for (i = 0; i < num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) channel = kzalloc(sizeof(*channel), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) if (!channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) goto error3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) channel->hc_num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) INIT_LIST_HEAD(&channel->split_order_list_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) hsotg->hc_ptr_array[i] = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) /* Initialize work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) * Allocate space for storing data on status transactions. Normally no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) * data is sent, but this space acts as a bit bucket. This must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) * done after usb_add_hcd since that function allocates the DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) * pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) if (hsotg->params.host_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) DWC2_HCD_STATUS_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) &hsotg->status_buf_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) if (!hsotg->status_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) goto error3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) * Create kmem caches to handle descriptor buffers in descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) * DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) * Alignment must be set to 512 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) if (hsotg->params.dma_desc_enable ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) hsotg->params.dma_desc_fs_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) sizeof(struct dwc2_dma_desc) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) if (!hsotg->desc_gen_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) "unable to create dwc2 generic desc cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) * Disable descriptor dma mode since it will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) * usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) hsotg->params.dma_desc_fs_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) sizeof(struct dwc2_dma_desc) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) if (!hsotg->desc_hsisoc_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) "unable to create dwc2 hs isoc desc cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) kmem_cache_destroy(hsotg->desc_gen_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) * Disable descriptor dma mode since it will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) * usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) hsotg->params.dma_desc_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) hsotg->params.dma_desc_fs_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) if (hsotg->params.host_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) * Create kmem caches to handle non-aligned buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) * in Buffer DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) SLAB_CACHE_DMA, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) if (!hsotg->unaligned_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) "unable to create dwc2 unaligned cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) hsotg->otg_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) hsotg->frame_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) hsotg->frame_list_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) hsotg->periodic_qh_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) /* Initiate lx_state to L3 disconnected state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) hsotg->lx_state = DWC2_L3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) hcd->self.otg_port = hsotg->otg_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) /* Don't support SG list at this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) hcd->self.sg_tablesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) if (!IS_ERR_OR_NULL(hsotg->uphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) otg_set_host(hsotg->uphy->otg, &hcd->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) * do not manage the PHY state in the HCD core, instead let the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) * handle this (for example if the PHY can only be turned on after a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) * specific event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) hcd->skip_phy_initialization = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) * Finish generic HCD initialization and start the HCD. This function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) * allocates the DMA buffer pool, registers the USB bus, requests the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) * IRQ line, and calls hcd_start method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) goto error4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) device_wakeup_enable(hcd->self.controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) dwc2_hcd_dump_state(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) dwc2_enable_global_interrupts(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) error4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) kmem_cache_destroy(hsotg->unaligned_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) kmem_cache_destroy(hsotg->desc_hsisoc_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) kmem_cache_destroy(hsotg->desc_gen_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) error3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) dwc2_hcd_release(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) error2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) kfree(hsotg->last_frame_num_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) kfree(hsotg->frame_num_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) * Removes the HCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) * Frees memory and resources associated with the HCD and deregisters the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) hcd = dwc2_hsotg_to_hcd(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) if (!hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) if (!IS_ERR_OR_NULL(hsotg->uphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) otg_set_host(hsotg->uphy->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) hsotg->priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) kmem_cache_destroy(hsotg->unaligned_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) kmem_cache_destroy(hsotg->desc_hsisoc_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) kmem_cache_destroy(hsotg->desc_gen_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) dwc2_hcd_release(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) kfree(hsotg->last_frame_num_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) kfree(hsotg->frame_num_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) * dwc2_backup_host_registers() - Backup controller host registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) * When suspending usb bus, registers needs to be backuped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) * if controller power is disabled once suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) struct dwc2_hregs_backup *hr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) dev_dbg(hsotg->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) /* Backup Host regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) hr = &hsotg->hr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) hr->hcfg = dwc2_readl(hsotg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) for (i = 0; i < hsotg->params.host_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) hr->hprt0 = dwc2_read_hprt0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) hr->hfir = dwc2_readl(hsotg, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) hr->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) * dwc2_restore_host_registers() - Restore controller host registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) * When resuming usb bus, device registers needs to be restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) * if controller power were disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) struct dwc2_hregs_backup *hr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) dev_dbg(hsotg->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) /* Restore host regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) hr = &hsotg->hr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) if (!hr->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) dev_err(hsotg->dev, "%s: no host registers to restore\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) hr->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) dwc2_writel(hsotg, hr->hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) for (i = 0; i < hsotg->params.host_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) dwc2_writel(hsotg, hr->hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) dwc2_writel(hsotg, hr->hfir, HFIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) hsotg->frame_number = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) * dwc2_host_enter_hibernation() - Put controller in Hibernation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) u32 pcgcctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) u32 gusbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) u32 gpwrdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) ret = dwc2_backup_global_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) dev_err(hsotg->dev, "%s: failed to backup global registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) ret = dwc2_backup_host_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) dev_err(hsotg->dev, "%s: failed to backup host registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) /* Enter USB Suspend Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) hprt0 |= HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) hprt0 &= ~HPRT0_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) /* Wait for the HPRT0.PrtSusp register field to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) dev_warn(hsotg->dev, "Suspend wasn't generated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) * We need to disable interrupts to prevent servicing of any IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) * during going to hibernation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) hsotg->lx_state = DWC2_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) gusbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) /* ULPI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) /* Suspend the Phy Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) pcgcctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) pcgcctl |= PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) dwc2_writel(hsotg, pcgcctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) gpwrdn |= GPWRDN_PMUACTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) /* UTMI+ Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) gpwrdn |= GPWRDN_PMUACTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) pcgcctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) pcgcctl |= PCGCTL_STOPPCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) dwc2_writel(hsotg, pcgcctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) /* Enable interrupts from wake up logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) gpwrdn |= GPWRDN_PMUINTSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) /* Unmask host mode interrupts in GPWRDN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) gpwrdn |= GPWRDN_DISCONN_DET_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) gpwrdn |= GPWRDN_LNSTSCHG_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) gpwrdn |= GPWRDN_STS_CHGINT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) /* Enable Power Down Clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) gpwrdn |= GPWRDN_PWRDNCLMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) /* Switch off VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) gpwrdn |= GPWRDN_PWRDNSWTCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) hsotg->hibernated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) hsotg->bus_suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) dev_dbg(hsotg->dev, "Host hibernation completed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) * dwc2_host_exit_hibernation()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) * @rem_wakeup: indicates whether resume is initiated by Device or Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) * @param reset: indicates whether resume is initiated by Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) * Return: non-zero if failed to enter to hibernation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) * This function is for exiting from Host mode hibernation by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) int reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) u32 gpwrdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) u32 hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) struct dwc2_gregs_backup *gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) struct dwc2_hregs_backup *hr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) gr = &hsotg->gr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) hr = &hsotg->hr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) "%s: called with rem_wakeup = %d reset = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) __func__, rem_wakeup, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) hsotg->hibernated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) * This step is not described in functional spec but if not wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) * this delay, mismatch interrupts occurred because just after restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) * core is in Device mode(gintsts.curmode == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) /* Clear all pending interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) /* De-assert Restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) gpwrdn &= ~GPWRDN_RESTORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) /* Restore GUSBCFG, HCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) dwc2_writel(hsotg, hr->hcfg, HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) /* De-assert Wakeup Logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) gpwrdn &= ~GPWRDN_PMUACTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) hprt0 = hr->hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) hprt0 |= HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) hprt0 &= ~HPRT0_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) hprt0 &= ~HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) hprt0 = hr->hprt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) hprt0 |= HPRT0_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) hprt0 &= ~HPRT0_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) hprt0 &= ~HPRT0_SUSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) hprt0 |= HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) /* Wait for Resume time and then program HPRT again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) mdelay(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) hprt0 &= ~HPRT0_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) hprt0 |= HPRT0_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) /* Wait for Resume time and then program HPRT again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) hprt0 &= ~HPRT0_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) /* Clear all interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) hprt0 |= HPRT0_CONNDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) hprt0 |= HPRT0_ENACHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) hprt0 &= ~HPRT0_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) dwc2_writel(hsotg, hprt0, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) hprt0 = dwc2_readl(hsotg, HPRT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) /* Clear all pending interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) /* Restore global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) ret = dwc2_restore_global_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) dev_err(hsotg->dev, "%s: failed to restore registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) /* Restore host registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) ret = dwc2_restore_host_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) dev_err(hsotg->dev, "%s: failed to restore host registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) if (rem_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) dwc2_hcd_rem_wakeup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) * Change "port_connect_status_change" flag to re-enumerate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) * because after exit from hibernation port connection status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) * is not detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) hsotg->flags.b.port_connect_status_change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) hsotg->hibernated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) hsotg->bus_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) /* If the controller isn't allowed to wakeup then we can power off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) if (!device_may_wakeup(dwc2->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) * We don't want to power off the PHY if something under the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) * root hub has wakeup enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) if (usb_wakeup_enabled_descendants(root_hub))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) /* No reason to keep the PHY powered, so allow poweroff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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