^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * S3C USB2.0 High-speed / OtG driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_data/s3c-hsotg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/usb/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/usb/composite.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* conversion functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return container_of(req, struct dwc2_hsotg_req, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return container_of(ep, struct dwc2_hsotg_ep, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return container_of(gadget, struct dwc2_hsotg, gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 ep_index, u32 dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return hsotg->eps_in[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return hsotg->eps_out[ep_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* forward declaration of functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * using_dma - return the DMA status of the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @hsotg: The driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Return true if we're using DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Currently, we have the DMA support code worked into everywhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * that needs it, but the AMBA DMA implementation in the hardware can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * only DMA from 32bit aligned addresses. This means that gadgets such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * as the CDC Ethernet cannot work as they often pass packets which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * not 32bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Unfortunately the choice to use DMA or not is global to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * and seems to be only settable when the controller is being put through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * a core reset. This means we either need to fix the gadgets to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * account of DMA alignment, or add bounce buffers (yuerk).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * g_using_dma is set depending on dts flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline bool using_dma(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return hsotg->params.g_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * using_desc_dma - return the descriptor DMA status of the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @hsotg: The driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Return true if we're using descriptor DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return hsotg->params.g_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * dwc2_hsotg_read_frameno - read current frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @hsotg: The device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Return the current frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 dsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dsts = dwc2_readl(hsotg, DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dsts &= DSTS_SOFFN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dsts >>= DSTS_SOFFN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return dsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @hs_ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * If an overrun occurs it will wrap the value and set the frame_overrun flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 limit = DSTS_SOFFN_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (hsotg->gadget.speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) limit >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hs_ep->target_frame += hs_ep->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (hs_ep->target_frame > limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) hs_ep->frame_overrun = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hs_ep->target_frame &= limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else if (current_frame <= hs_ep->target_frame) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hs_ep->frame_overrun = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @hs_ep: The endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * This function used in service interval based scheduling flow to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * descriptor frame number filed value. For service interval mode frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * number in descriptor should point to last (u)frame in the interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 limit = DSTS_SOFFN_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (hsotg->gadget.speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) limit >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (hs_ep->target_frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hs_ep->target_frame -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hs_ep->target_frame = limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @ints: A bitmask of the interrupts to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 new_gsintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) new_gsintmsk = gsintmsk | ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (new_gsintmsk != gsintmsk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @ints: A bitmask of the interrupts to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 new_gsintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) new_gsintmsk = gsintmsk & ~ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (new_gsintmsk != gsintmsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @ep: The endpoint index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @dir_in: True if direction is in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @en: The enable value, true to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Set or clear the mask for an individual endpoint's interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int ep, unsigned int dir_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 bit = 1 << ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 daint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bit <<= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) daint = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) daint |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) daint &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dwc2_writel(hsotg, daint, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (hsotg->hw_params.en_multiple_tx_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* In dedicated FIFO mode we need count of IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return hsotg->hw_params.num_dev_in_eps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* In shared FIFO mode we need count of Periodic IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return hsotg->hw_params.num_dev_perio_in_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * device mode TX FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int tx_addr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 np_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hsotg->params.g_np_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Get Endpoint Info Control block size in DWORDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tx_addr_max = hsotg->hw_params.total_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (tx_addr_max <= addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return tx_addr_max - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 gintsts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 gintmsk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) gintsts2 = dwc2_readl(hsotg, GINTSTS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) gintsts2 &= gintmsk2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * TX FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int tx_fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int tx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!tx_fifo_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return tx_fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return tx_fifo_depth / tx_fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @hsotg: The device instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 *txfsz = hsotg->params.g_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Reset fifo map if not correctly cleared during previous session */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WARN_ON(hsotg->fifo_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) hsotg->fifo_map = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* set RX/NPTX FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FIFOSIZE_STARTADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GNPTXFSIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * arange all the rest of the TX FIFOs, as some versions of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * block have overlapping default addresses. This also ensures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * that if the settings have been changed, then they are set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * known values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* start at the end of the GNPTXFSIZ, rounded up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Configure fifos sizes from provided configuration and assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * them to endpoints dynamically according to maxpacket size value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * given endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!txfsz[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) val = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "insufficient fifo memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) addr += txfsz[ep];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dwc2_writel(hsotg, val, DPTXFSIZN(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val = dwc2_readl(hsotg, DPTXFSIZN(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) addr << GDFIFOCFG_EPINFOBASE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GDFIFOCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * according to p428 of the design guide, we need to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * all fifos are flushed before continuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) GRSTCTL_RXFFLSH, GRSTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* wait until the fifos are both flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val = dwc2_readl(hsotg, GRSTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (--timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @ep: USB endpoint to allocate request for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @flags: Allocation flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Allocate a new USB request structure appropriate for the specified endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct dwc2_hsotg_req *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) req = kzalloc(sizeof(*req), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) INIT_LIST_HEAD(&req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return &req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * is_ep_periodic - return true if the endpoint is in periodic mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @hs_ep: The endpoint to query.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Returns true if the endpoint is in periodic mode, meaning it is being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * used for an Interrupt or ISO transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return hs_ep->periodic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @hs_ep: The endpoint for the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * @hs_req: The request being processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * of a request to ensure the buffer is ready for access by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct dwc2_hsotg_req *hs_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct usb_request *req = &hs_req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * for Control endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * This function will allocate 4 descriptor chains for EP 0: 2 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * Setup stage, per one for IN and OUT data/status transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) hsotg->setup_desc[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dmam_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &hsotg->setup_desc_dma[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!hsotg->setup_desc[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hsotg->setup_desc[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dmam_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) &hsotg->setup_desc_dma[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!hsotg->setup_desc[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) hsotg->ctrl_in_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dmam_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &hsotg->ctrl_in_desc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!hsotg->ctrl_in_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) hsotg->ctrl_out_desc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dmam_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &hsotg->ctrl_out_desc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!hsotg->ctrl_out_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @hsotg: The controller state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @hs_ep: The endpoint we're going to write for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @hs_req: The request to write data for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * This is called when the TxFIFO has some space in it to hold a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * transmission and we have something to give it. The actual setup of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * the data size is done elsewhere, so all we have to do is to actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * write the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * The return value is zero if there is more space (or nothing was done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * otherwise -ENOSPC is returned if the FIFO space was used up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * This routine is only needed for PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dwc2_hsotg_req *hs_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bool periodic = is_ep_periodic(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int buf_pos = hs_req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int to_write = hs_ep->size_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int can_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int pkt_round;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int max_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) to_write -= (buf_pos - hs_ep->last_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* if there's nothing to write, get out early */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (to_write == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (periodic && !hsotg->dedicated_fifos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int size_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * work out how much data was loaded so we can calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * how much data is left in the fifo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * if shared fifo, we cannot write anything until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * previous data has been completely sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (hs_ep->fifo_load != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __func__, size_left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* how much of the data has moved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) size_done = hs_ep->size_loaded - size_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* how much data is left in the fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) can_write = hs_ep->fifo_load - size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __func__, can_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) can_write = hs_ep->fifo_size - can_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __func__, can_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (can_write <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) can_write = dwc2_readl(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) DTXFSTS(hs_ep->fifo_index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) can_write &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) can_write *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "%s: no queue slots available (0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) __func__, gnptxsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) can_write *= 4; /* fifo size is in 32bit quantities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) __func__, gnptxsts, can_write, to_write, max_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * limit to 512 bytes of data, it seems at least on the non-periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * FIFO, requests of >512 cause the endpoint to get stuck with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * fragment of the end of the transfer in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (can_write > 512 && !periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) can_write = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * limit the write to one max-packet size worth of data, but allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * the transfer to return that it did not run out of fifo space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * doing it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (to_write > max_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) to_write = max_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* it's needed only when we do not use dedicated fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!hsotg->dedicated_fifos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dwc2_hsotg_en_gsint(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) periodic ? GINTSTS_PTXFEMP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) GINTSTS_NPTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* see if we can write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (to_write > can_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) to_write = can_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pkt_round = to_write % max_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Round the write down to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * exact number of packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Note, we do not currently check to see if we can ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * write a full packet or not to the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (pkt_round)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) to_write -= pkt_round;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * enable correct FIFO interrupt to alert us when there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * is more room left.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* it's needed only when we do not use dedicated fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!hsotg->dedicated_fifos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dwc2_hsotg_en_gsint(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) periodic ? GINTSTS_PTXFEMP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) GINTSTS_NPTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) to_write, hs_req->req.length, can_write, buf_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (to_write <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) hs_req->req.actual = buf_pos + to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) hs_ep->total_data += to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hs_ep->fifo_load += to_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) to_write = DIV_ROUND_UP(to_write, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) data = hs_req->req.buf + buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return (to_write >= can_write) ? -ENOSPC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * get_ep_limit - get the maximum data legnth for this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * @hs_ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Return the maximum data that can be queued in one go on a given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * so that transfers that are too long can be split.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) unsigned int maxpkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (index != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) maxsize = 64 + 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (hs_ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) maxpkt = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* we made the constant loading easier above by using +1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) maxpkt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) maxsize--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * constrain by packet count if maxpkts*pktsize is greater
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * than the length register size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) maxsize = maxpkt * hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * DMA descriptor chain prepared for specific endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * @hs_ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * Return the maximum data that can be queued in one go on a given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * depending on its descriptor chain capacity so that transfers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * are too long can be split.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int is_isoc = hs_ep->isochronous;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 mps = hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (is_isoc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MAX_DMA_DESC_NUM_HS_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Interrupt OUT EP with mps not multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (hs_ep->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * @hs_ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * @mask: RX/TX bytes mask to be defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Returns maximum data payload for one descriptor after analyzing endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * characteristics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * DMA descriptor transfer bytes limit depends on EP type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * Control out - MPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * Isochronous - descriptor rx/tx bytes bitfield limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * have concatenations from various descriptors within one packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * to a single descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Selects corresponding mask for RX/TX bytes as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 mps = hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 desc_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!hs_ep->index && !dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) desc_size = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *mask = DEV_DMA_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) } else if (hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) desc_size = DEV_DMA_NBYTES_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *mask = DEV_DMA_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Round down desc_size to be mps multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) desc_size -= desc_size % mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Interrupt OUT EP with mps not multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (hs_ep->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) desc_size = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *mask = DEV_DMA_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct dwc2_dma_desc **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dma_addr_t dma_buff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) bool true_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 mps = hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 maxsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) hs_ep->desc_count = (len / maxsize) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ((len % maxsize) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) hs_ep->desc_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for (i = 0; i < hs_ep->desc_count; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (*desc)->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) << DEV_DMA_BUFF_STS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (len > maxsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!hs_ep->index && !dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) (*desc)->status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) maxsize << DEV_DMA_NBYTES_SHIFT & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) (*desc)->buf = dma_buff + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) len -= maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) offset += maxsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (true_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ((hs_ep->send_zlp && true_last) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) DEV_DMA_SHORT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (*desc)->status |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) len << DEV_DMA_NBYTES_SHIFT & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) (*desc)->buf = dma_buff + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) << DEV_DMA_BUFF_STS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) (*desc)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * @hs_ep: The endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * @ureq: Request to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * @offset: offset in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * @len: Length of the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * This function will iterate over descriptor chain and fill its entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * with corresponding information based on transfer data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dma_addr_t dma_buff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct usb_request *ureq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct dwc2_dma_desc *desc = hs_ep->desc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u8 desc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (hs_ep->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ureq = &hs_ep->req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* non-DMA sg buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!ureq || !ureq->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dma_buff, len, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* DMA sg buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sg_is_last(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) desc_count += hs_ep->desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hs_ep->desc_count = desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * @hs_ep: The isochronous endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * @dma_buff: usb requests dma buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * @len: usb request transfer length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Fills next free descriptor with the data of the arrived usb request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * frame info, sets Last and IOC bits increments next_desc. If filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * descriptor is not the first one, removes L bit from the previous descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma_addr_t dma_buff, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct dwc2_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u8 pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dwc2_gadget_get_desc_params(hs_ep, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) index = hs_ep->next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) desc = &hs_ep->desc_list[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Check if descriptor chain full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) DEV_DMA_BUFF_STS_HREADY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Clear L bit of previous desc if more than one entries in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (hs_ep->next_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) desc->buf = dma_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ((len << DEV_DMA_NBYTES_SHIFT) & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (hs_ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) DEV_DMA_ISOC_PID_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ((len % hs_ep->ep.maxpacket) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DEV_DMA_SHORT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ((hs_ep->target_frame <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DEV_DMA_ISOC_FRNUM_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DEV_DMA_ISOC_FRNUM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) desc->status &= ~DEV_DMA_BUFF_STS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Increment frame number by interval for IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (hs_ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* Update index of last configured entry in the chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) hs_ep->next_desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) hs_ep->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @hs_ep: The isochronous endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Prepare descriptor chain for isochronous endpoints. Afterwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * write DMA address to HW and enable the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct dwc2_hsotg_req *hs_req, *treq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u32 dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) u32 depctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct dwc2_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (list_empty(&hs_ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) hs_ep->target_frame = TARGET_FRAME_INITIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Initialize descriptor chain by Host Busy status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) desc = &hs_ep->desc_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) desc->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) desc->status |= (DEV_DMA_BUFF_STS_HBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) << DEV_DMA_BUFF_STS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) hs_ep->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dma_addr_t dma_addr = hs_req->req.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (hs_req->req.num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) WARN_ON(hs_req->req.num_sgs > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dma_addr = sg_dma_address(hs_req->req.sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) hs_req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) hs_ep->compl_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* write descriptor chain address to control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ctrl = dwc2_readl(hsotg, depctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dwc2_writel(hsotg, ctrl, depctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct dwc2_hsotg_req *hs_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * @hsotg: The controller state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * @hs_ep: The endpoint to process a request for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * @hs_req: The request to start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * @continuing: True if we are doing more for the current request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Start the given request running by setting the endpoint registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * appropriately, and writing any data to the FIFOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct dwc2_hsotg_req *hs_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bool continuing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct usb_request *ureq = &hs_req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 epctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u32 epsize_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 epsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned int packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) unsigned int maxreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) unsigned int dma_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (index != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (hs_ep->req && !continuing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) dev_err(hsotg->dev, "%s: active request\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) } else if (hs_ep->req != hs_req && continuing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "%s: continue different req\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) __func__, dwc2_readl(hsotg, epctrl_reg), index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) hs_ep->dir_in ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* If endpoint is stalled, we will restart request later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ctrl = dwc2_readl(hsotg, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (index && ctrl & DXEPCTL_STALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) length = ureq->length - ureq->actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ureq->length, ureq->actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (!using_desc_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) maxreq = get_ep_limit(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) maxreq = dwc2_gadget_get_chain_limit(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (length > maxreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int round = maxreq % hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) __func__, length, maxreq, round);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* round down to multiple of packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (round)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) maxreq -= round;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) length = maxreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) packets = 1; /* send one packet if length is zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (dir_in && index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) epsize = DXEPTSIZ_MC(packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) epsize = DXEPTSIZ_MC(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) epsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * zero length packet should be programmed on its own and should not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * be counted in DIEPTSIZ.PktCnt with other packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (dir_in && ureq->zero && !continuing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Test if zlp is actually required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if ((ureq->length >= hs_ep->ep.maxpacket) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) !(ureq->length % hs_ep->ep.maxpacket))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) hs_ep->send_zlp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) epsize |= DXEPTSIZ_PKTCNT(packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) epsize |= DXEPTSIZ_XFERSIZE(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) __func__, packets, length, ureq->length, epsize, epsize_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* store the request as the current one we're doing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) hs_ep->req = hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u32 mps = hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (!dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) length = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) else if (length % mps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) length += (mps - (length % mps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (continuing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) offset = ureq->actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Fill DDMA chain entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* write descriptor chain address to control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) __func__, (u32)hs_ep->desc_list_dma, dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* write size / packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) dwc2_writel(hsotg, epsize, epsize_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (using_dma(hsotg) && !continuing && (length != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * write DMA address to control register, buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * already synced by dwc2_hsotg_ep_queue().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dwc2_writel(hsotg, ureq->dma, dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) __func__, &ureq->dma, dma_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (hs_ep->interval == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (hs_ep->target_frame & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ctrl |= DXEPCTL_SETODDFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ctrl |= DXEPCTL_SETEVENFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ctrl |= DXEPCTL_CNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) hs_req->req.frame_number = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) hs_req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* For Setup request do not clear NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dwc2_writel(hsotg, ctrl, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * set these, it seems that DMA support increments past the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * of the packet buffer so we need to calculate the length from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * this information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) hs_ep->size_loaded = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hs_ep->last_load = ureq->actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (dir_in && !using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* set these anyway, we may need them for non-periodic in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) hs_ep->fifo_load = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * Note, trying to clear the NAK here causes problems with transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * on the S3C6400 ending up with the TXFIFO becoming full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* check ep is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) index, dwc2_readl(hsotg, epctrl_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) __func__, dwc2_readl(hsotg, epctrl_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* enable ep interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * dwc2_hsotg_map_dma - map the DMA memory being used for the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * @hs_ep: The endpoint the request is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * @req: The request being processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * We've been asked to queue a request, so ensure that the memory buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * is correctly setup for DMA. If we've been passed an extant DMA address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * then ensure the buffer has been synced to memory. If our buffer has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * DMA memory, then we map the memory and mark our request to allow us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * cleanup on completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) hs_ep->map_dir = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto dma_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dma_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) __func__, req->buf, req->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct dwc2_hsotg_req *hs_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) void *req_buf = hs_req->req.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* If dma is not being used or buffer is aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!using_dma(hsotg) || !((long)req_buf & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) WARN_ON(hs_req->saved_req_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) hs_ep->ep.name, req_buf, hs_req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!hs_req->req.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) hs_req->req.buf = req_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "%s: unable to allocate memory for bounce buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* Save actual buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) hs_req->saved_req_buf = req_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (hs_ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct dwc2_hsotg_req *hs_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* If dma is not being used or buffer was aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!using_dma(hsotg) || !hs_req->saved_req_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Copy data from bounce buffer on successful out transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (!hs_ep->dir_in && !hs_req->req.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) memcpy(hs_req->saved_req_buf, hs_req->req.buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) hs_req->req.actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Free bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) kfree(hs_req->req.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) hs_req->req.buf = hs_req->saved_req_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) hs_req->saved_req_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * dwc2_gadget_target_frame_elapsed - Checks target frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * @hs_ep: The driver endpoint to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * corresponding transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) u32 target_frame = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u32 current_frame = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) bool frame_overrun = hs_ep->frame_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) u16 limit = DSTS_SOFFN_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (hsotg->gadget.speed != USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) limit >>= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (!frame_overrun && current_frame >= target_frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (frame_overrun && current_frame >= target_frame &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ((current_frame - target_frame) < limit / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * @hsotg: The driver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * @hs_ep: the ep descriptor chain is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * Called to update EP0 structure's pointers depend on stage of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * control transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) switch (hsotg->ep0_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case DWC2_EP0_SETUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) case DWC2_EP0_STATUS_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) hs_ep->desc_list = hsotg->setup_desc[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) case DWC2_EP0_DATA_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case DWC2_EP0_STATUS_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) hs_ep->desc_list = hsotg->ctrl_in_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) case DWC2_EP0_DATA_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) hs_ep->desc_list = hsotg->ctrl_out_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) hsotg->ep0_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct dwc2_hsotg_req *hs_req = our_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct dwc2_hsotg *hs = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) bool first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 maxsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ep->name, req, req->length, req->buf, req->no_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) req->zero, req->short_not_ok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Prevent new request submission when controller is suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (hs->lx_state != DWC2_L0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_dbg(hs->dev, "%s: submit request only in active state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* initialise status of the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) INIT_LIST_HEAD(&hs_req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) req->actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) req->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* Don't queue ISOC request if length greater than mps*mc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (hs_ep->isochronous &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_err(hs->dev, "req length > maxpacket*mc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* In DDMA mode for ISOC's don't queue request if length greater
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * than descriptor limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (using_desc_dma(hs) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (hs_ep->dir_in && req->length > maxsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) req->length, maxsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) req->length, hs_ep->ep.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* if we're using DMA, sync the buffers as necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (using_dma(hs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* If using descriptor DMA configure EP0 descriptor chain pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (using_desc_dma(hs) && !hs_ep->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) first = list_empty(&hs_ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) list_add_tail(&hs_req->queue, &hs_ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * Handle DDMA isochronous transfers separately - just add new entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * to the descriptor chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * Transfer will be started once SW gets either one of NAK or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * OutTknEpDis interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (using_desc_dma(hs) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) dma_addr_t dma_addr = hs_req->req.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (hs_req->req.num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) WARN_ON(hs_req->req.num_sgs > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dma_addr = sg_dma_address(hs_req->req.sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) hs_req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* Change EP direction if status phase request is after data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) hs->ep0_state == DWC2_EP0_DATA_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) hs_ep->dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Update current frame number value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) hs->frame_number = dwc2_hsotg_read_frameno(hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Update current frame number value once more as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * changes here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) hs->frame_number = dwc2_hsotg_read_frameno(hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) } else if (hs_ep->isochronous && hs_ep->dir_in && !hs_ep->req &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) !(dwc2_readl(hs, GHWCFG2) & GHWCFG2_MULTI_PROC_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* Update current frame number value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) hs->frame_number = dwc2_hsotg_read_frameno(hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* Update current frame number value once more as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * changes here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) hs->frame_number = dwc2_hsotg_read_frameno(hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) dwc2_gadget_start_next_request(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct dwc2_hsotg *hs = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) spin_lock_irqsave(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) spin_unlock_irqrestore(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct dwc2_hsotg_req *hs_req = our_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) kfree(hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * dwc2_hsotg_complete_oursetup - setup completion callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * @ep: The endpoint the request was on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * @req: The request completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * Called on completion of any requests the driver itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * submitted that need cleaning up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dwc2_hsotg_ep_free_request(ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * ep_from_windex - convert control wIndex value to endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * @hsotg: The driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * @windex: The control request wIndex field (in host order).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * Convert the given wIndex into a pointer to an driver endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * structure, or return NULL if it is not a valid endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u32 windex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) int dir = (windex & USB_DIR_IN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) int idx = windex & 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (windex >= 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (idx > hsotg->num_of_eps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return index_to_ep(hsotg, idx, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * dwc2_hsotg_set_test_mode - Enable usb Test Modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) * @hsotg: The driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * @testmode: requested usb test mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) * Enable usb Test Mode requested by the Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) int dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) dctl &= ~DCTL_TSTCTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) switch (testmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) case USB_TEST_J:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case USB_TEST_K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) case USB_TEST_SE0_NAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) case USB_TEST_PACKET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case USB_TEST_FORCE_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dctl |= testmode << DCTL_TSTCTL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * dwc2_hsotg_send_reply - send reply to control request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * @ep: Endpoint 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * @buff: Buffer for request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * @length: Length of reply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) * Create a request and queue it on the given endpoint. This is useful as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * an internal method of sending replies to certain control requests, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct dwc2_hsotg_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) void *buff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct usb_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) hsotg->ep0_reply = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (!req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) req->buf = hsotg->ep0_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) req->length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * zero flag is for sending zlp in DATA IN stage. It has no impact on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * STATUS stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) req->zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) req->complete = dwc2_hsotg_complete_oursetup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) memcpy(req->buf, buff, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * dwc2_hsotg_process_req_status - process request GET_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * @ctrl: USB control request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct dwc2_hsotg_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) __le16 reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (!ep0->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) switch (ctrl->bRequestType & USB_RECIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) status = hsotg->gadget.is_selfpowered <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) USB_DEVICE_SELF_POWERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) status |= hsotg->remote_wakeup_allowed <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) USB_DEVICE_REMOTE_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) reply = cpu_to_le16(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) case USB_RECIP_INTERFACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* currently, the data result should be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) reply = cpu_to_le16(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) reply = cpu_to_le16(ep->halted ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (le16_to_cpu(ctrl->wLength) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * get_ep_head - return the first request on the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * @hs_ep: The controller endpoint to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * Get the first request on the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * dwc2_gadget_start_next_request - Starts next request from ep queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * @hs_ep: Endpoint structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * in its handler. Hence we need to unmask it here to be able to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * resynchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) if (!list_empty(&hs_ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) hs_req = get_ep_head(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (!hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * @ctrl: USB control request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct dwc2_hsotg_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) bool halted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) u32 recip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) u32 wValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u32 wIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) __func__, set ? "SET" : "CLEAR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) wValue = le16_to_cpu(ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) wIndex = le16_to_cpu(ctrl->wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) recip = ctrl->bRequestType & USB_RECIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) switch (recip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) case USB_RECIP_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) case USB_DEVICE_REMOTE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) hsotg->remote_wakeup_allowed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) hsotg->remote_wakeup_allowed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) case USB_DEVICE_TEST_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if ((wIndex & 0xff) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (!set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) hsotg->test_mode = wIndex >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) "%s: failed to send reply\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) case USB_RECIP_ENDPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ep = ep_from_windex(hsotg, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) __func__, wIndex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) switch (wValue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case USB_ENDPOINT_HALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) halted = ep->halted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "%s: failed to send reply\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * we have to complete all requests for ep if it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * halted, and the halt was cleared by CLEAR_FEATURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (!set && halted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) * If we have request in progress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * then complete it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (ep->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) hs_req = ep->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ep->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) list_del_init(&hs_req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (hs_req->req.complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) usb_gadget_giveback_request(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) &ep->ep, &hs_req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /* If we have pending request, then start it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (!ep->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dwc2_gadget_start_next_request(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * dwc2_hsotg_stall_ep0 - stall ep0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * Set stall for ep0 as response for setup request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * DxEPCTL_Stall will be cleared by EP once it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * taken effect, so no need to clear later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ctrl = dwc2_readl(hsotg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ctrl |= DXEPCTL_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ctrl |= DXEPCTL_CNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) dwc2_writel(hsotg, ctrl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ctrl, reg, dwc2_readl(hsotg, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * complete won't be called, so we enqueue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) * setup request here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * dwc2_hsotg_process_control - process a control request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * @ctrl: The control request received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * The controller has received the SETUP phase of a control request, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * needs to work out what to do next (and whether to pass it on to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * gadget driver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) struct usb_ctrlrequest *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u32 dcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ctrl->wIndex, ctrl->wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (ctrl->wLength == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ep0->dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) hsotg->ep0_state = DWC2_EP0_STATUS_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) } else if (ctrl->bRequestType & USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ep0->dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) hsotg->ep0_state = DWC2_EP0_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ep0->dir_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) hsotg->ep0_state = DWC2_EP0_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) switch (ctrl->bRequest) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) case USB_REQ_SET_ADDRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) hsotg->connected = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dcfg = dwc2_readl(hsotg, DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) dcfg &= ~DCFG_DEVADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) dcfg |= (le16_to_cpu(ctrl->wValue) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) dwc2_writel(hsotg, dcfg, DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) case USB_REQ_GET_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case USB_REQ_CLEAR_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) case USB_REQ_SET_FEATURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* as a fallback, try delivering it to the driver to deal with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (ret == 0 && hsotg->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) hsotg->delayed_status = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (ret == USB_GADGET_DELAYED_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) hsotg->delayed_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * the request is either unhandlable, or is not formatted correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * so respond with a STALL for the status stage to indicate failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dwc2_hsotg_stall_ep0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * dwc2_hsotg_complete_setup - completion of a setup transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * @ep: The endpoint the request was on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * @req: The request completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * Called on completion of any requests the driver itself submitted for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * EP0 setup packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (req->status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (req->actual == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) dwc2_hsotg_process_control(hsotg, req->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * Enqueue a request on EP0 if necessary to received any SETUP packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * received from the host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct usb_request *req = hsotg->ctrl_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct dwc2_hsotg_req *hs_req = our_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) req->zero = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) req->length = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) req->buf = hsotg->ctrl_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) req->complete = dwc2_hsotg_complete_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!list_empty(&hs_req->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) hsotg->eps_out[0]->dir_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) hsotg->eps_out[0]->send_zlp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) hsotg->ep0_state = DWC2_EP0_SETUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * Don't think there's much we can do other than watch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) * driver fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) u8 index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (hs_ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* Not specific buffer needed for ep0 ZLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dma_addr_t dma = hs_ep->desc_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (!index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) DXEPTSIZ_XFERSIZE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) epsiz_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ctrl = dwc2_readl(hsotg, epctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ctrl |= DXEPCTL_USBACTEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) dwc2_writel(hsotg, ctrl, epctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * dwc2_hsotg_complete_request - complete a request given to us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * @hs_ep: The endpoint the request was on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * @hs_req: The request to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * @result: The result code (0 => Ok, otherwise errno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * The given request has finished, so call the necessary completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * if it has one and then look to see if we can start a new request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * on the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) * Note, expects the ep to already be locked as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct dwc2_hsotg_req *hs_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (!hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) * only replace the status if we've not already set an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) * from a previous transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (hs_req->req.status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) hs_req->req.status = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (using_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) hs_ep->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) list_del_init(&hs_req->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) * call the complete request with the locks off, just in case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) * request tries to queue more work for this endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (hs_req->req.complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* In DDMA don't need to proceed to starting of next ISOC request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (using_desc_dma(hsotg) && hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * Look to see if there is anything else to do. Note, the completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * of the previous request may have caused a new request to be started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * so be careful when doing this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (!hs_ep->req && result >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) dwc2_gadget_start_next_request(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) * @hs_ep: The endpoint the request was on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) * Get first request from the ep queue, determine descriptor on which complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * happened. SW discovers which descriptor currently in use by HW, adjusts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * dma_address and calculates index of completed descriptor based on the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * of DEPDMA register. Update actual length of request, giveback to gadget.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) struct usb_request *ureq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) u32 desc_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* Process only descriptors with buffer status set to DMA done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) hs_req = get_ep_head(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (!hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ureq = &hs_req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /* Check completion status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) DEV_DMA_STS_SUCC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) DEV_DMA_ISOC_RX_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ureq->actual = ureq->length - ((desc_sts & mask) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) DEV_DMA_ISOC_NBYTES_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* Adjust actual len for ISOC Out if len is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) * not align of 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (!hs_ep->dir_in && ureq->length & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ureq->actual += 4 - (ureq->length & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /* Set actual frame number for completed transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ureq->frame_number =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) DEV_DMA_ISOC_FRNUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) hs_ep->compl_desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) hs_ep->compl_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * @hs_ep: The isochronous endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * interrupt. Reset target frame and next_desc to allow to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) * interrupt for OUT direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (!hs_ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dwc2_flush_rx_fifo(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) hs_ep->target_frame = TARGET_FRAME_INITIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) hs_ep->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) hs_ep->compl_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * @ep_idx: The endpoint index for the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) * @size: The size of data in the fifo, in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) * The FIFO status shows there is data to read from the FIFO for a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * endpoint, so sort out whether we need to read the data into a request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * that has been made for that endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct dwc2_hsotg_req *hs_req = hs_ep->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) int to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) int max_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) int read_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (!hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) int ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) __func__, size, ep_idx, epctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* dump the data from the FIFO, we've nothing we can do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) for (ptr = 0; ptr < size; ptr += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) to_read = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) read_ptr = hs_req->req.actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) max_req = hs_req->req.length - read_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) __func__, to_read, max_req, read_ptr, hs_req->req.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (to_read > max_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) * more data appeared than we where willing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) * to deal with in this request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* currently we don't deal this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) hs_ep->total_data += to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) hs_req->req.actual += to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) to_read = DIV_ROUND_UP(to_read, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) * note, we might over-write the buffer end by 3 bytes depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * alignment of the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) hs_req->req.buf + read_ptr, to_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) * @hsotg: The device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * @dir_in: If IN zlp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * Generate a zero-length IN packet request for terminating a SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * Note, since we don't write any data to the TxFIFO, then it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * currently believed that we do not need to wait for any space in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) * the TxFIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* eps_out[0] is used in both directions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) hsotg->eps_out[0]->dir_in = dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) * @hs_ep - The endpoint on which transfer went
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) * Iterate over endpoints descriptor chain and get info on bytes remained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) * in DMA descriptors after transfer has completed. Used for non isoc EPs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) unsigned int bytes_rem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) unsigned int bytes_rem_correction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) struct dwc2_dma_desc *desc = hs_ep->desc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) u32 mps = hs_ep->ep.maxpacket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* Interrupt OUT EP with mps not multiple of 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (hs_ep->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) bytes_rem_correction = 4 - (mps % 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) for (i = 0; i < hs_ep->desc_count; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) status = desc->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) bytes_rem += status & DEV_DMA_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) bytes_rem -= bytes_rem_correction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (status & DEV_DMA_STS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) dev_err(hsotg->dev, "descriptor %d closed with %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) i, status & DEV_DMA_STS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if (status & DEV_DMA_L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) return bytes_rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) * @hsotg: The device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) * @epnum: The endpoint received from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) * The RXFIFO has delivered an OutDone event, which means that the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * transfer for an OUT endpoint has been completed, either by a short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) * packet or by the finish of a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct dwc2_hsotg_req *hs_req = hs_ep->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) struct usb_request *req = &hs_req->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) if (!hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) dev_dbg(hsotg->dev, "zlp packet received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) if (using_desc_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) unsigned int size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * Calculate the size of the transfer by checking how much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * is left in the endpoint size register and then working it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) * out from the amount we loaded for the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) * We need to do this as DMA pointers are always 32bit aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * so may overshoot/undershoot the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) size_done = hs_ep->size_loaded - size_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) size_done += hs_ep->last_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) req->actual = size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /* if there is more request to do, schedule new transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (req->actual < req->length && size_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) if (req->actual < req->length && req->short_not_ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) __func__, req->actual, req->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) * todo - what should we return here? there's no one else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) * even bothering to check the status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /* DDMA IN status phase will start from StsPhseRcvd interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (!using_desc_dma(hsotg) && epnum == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) /* Move to STATUS IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (!hsotg->delayed_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) dwc2_hsotg_ep0_zlp(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /* Set actual frame number for completed transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) req->frame_number = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) * dwc2_hsotg_handle_rx - RX FIFO has data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) * @hsotg: The device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) * The IRQ handler has detected that the RX FIFO has some data in it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) * that requires processing, so find out what is in there and do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) * appropriate read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) * The RXFIFO is a true FIFO, the packets coming out are still in packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) * chunks, so if you have x packets received on an endpoint you'll get x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) * FIFO events delivered, each with a packet's worth of data in it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) * When using DMA, we should not be processing events from the RXFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * as the actual data should be sent to the memory directly and we turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) * on the completion interrupts to get notifications of transfer completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) u32 epnum, status, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) WARN_ON(using_dma(hsotg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) epnum = grxstsr & GRXSTS_EPNUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) status = grxstsr & GRXSTS_PKTSTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) size = grxstsr & GRXSTS_BYTECNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) size >>= GRXSTS_BYTECNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) __func__, grxstsr, size, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) case GRXSTS_PKTSTS_GLOBALOUTNAK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) case GRXSTS_PKTSTS_OUTDONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) dwc2_hsotg_read_frameno(hsotg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (!using_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) dwc2_hsotg_handle_outdone(hsotg, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) case GRXSTS_PKTSTS_SETUPDONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) dwc2_hsotg_read_frameno(hsotg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) dwc2_readl(hsotg, DOEPCTL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) * Call dwc2_hsotg_handle_outdone here if it was not called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (hsotg->ep0_state == DWC2_EP0_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dwc2_hsotg_handle_outdone(hsotg, epnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) case GRXSTS_PKTSTS_OUTRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) dwc2_hsotg_rx_data(hsotg, epnum, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) case GRXSTS_PKTSTS_SETUPRX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dwc2_hsotg_read_frameno(hsotg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) dwc2_readl(hsotg, DOEPCTL(0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) dwc2_hsotg_rx_data(hsotg, epnum, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) dev_warn(hsotg->dev, "%s: unknown status %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) __func__, grxstsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) dwc2_hsotg_dump(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) * dwc2_hsotg_ep0_mps - turn max packet size into register setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) * @mps: The maximum packet size in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) switch (mps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) return D0EPCTL_MPS_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) return D0EPCTL_MPS_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return D0EPCTL_MPS_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) return D0EPCTL_MPS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /* bad max packet size, warn and return invalid result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) return (u32)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) * @hsotg: The driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) * @ep: The index number of the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) * @mps: The maximum packet size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) * @mc: The multicount value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) * @dir_in: True if direction is in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) * Configure the maximum packet size for the given endpoint, updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) * the hardware control registers to reflect this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) unsigned int ep, unsigned int mps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) unsigned int mc, unsigned int dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) struct dwc2_hsotg_ep *hs_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) hs_ep = index_to_ep(hsotg, ep, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (!hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (ep == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) u32 mps_bytes = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* EP0 is a special case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) mps = dwc2_hsotg_ep0_mps(mps_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) if (mps > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) goto bad_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) hs_ep->ep.maxpacket = mps_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) hs_ep->mc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (mps > 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) goto bad_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) hs_ep->mc = mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (mc > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) goto bad_mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) hs_ep->ep.maxpacket = mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) reg = dwc2_readl(hsotg, DIEPCTL(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) reg &= ~DXEPCTL_MPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) reg |= mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) dwc2_writel(hsotg, reg, DIEPCTL(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) reg = dwc2_readl(hsotg, DOEPCTL(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) reg &= ~DXEPCTL_MPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) reg |= mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) dwc2_writel(hsotg, reg, DOEPCTL(ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) bad_mps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) * dwc2_hsotg_txfifo_flush - flush Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * @hsotg: The driver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * @idx: The index for the endpoint (0..15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) GRSTCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) /* wait until the fifo is flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) * dwc2_hsotg_trytx - check to see if anything needs transmitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) * @hsotg: The driver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) * @hs_ep: The driver endpoint to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) * Check to see if there is a request that has data to send, and if so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) * make an attempt to write data into the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) struct dwc2_hsotg_req *hs_req = hs_ep->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (!hs_ep->dir_in || !hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) * if request is not enqueued, we disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) * for endpoints, excepting ep0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) if (hs_ep->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) hs_ep->dir_in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (hs_req->req.actual < hs_req->req.length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) hs_ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) * dwc2_hsotg_complete_in - complete IN transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) * @hs_ep: The endpoint that has just completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) * An IN transfer has been completed, update the transfer's state and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) * call the relevant completion routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) struct dwc2_hsotg_req *hs_req = hs_ep->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) int size_left, size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (!hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) dev_dbg(hsotg->dev, "XferCompl but no req\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* Finish ZLP handling for IN EP0 transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) dev_dbg(hsotg->dev, "zlp packet sent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) * While send zlp for DWC2_EP0_STATUS_IN EP direction was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) * changed to IN. Change back to complete OUT transfer request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) hs_ep->dir_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (hsotg->test_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) dev_dbg(hsotg->dev, "Invalid Test #%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) hsotg->test_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) dwc2_hsotg_stall_ep0(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * Calculate the size of the transfer by checking how much is left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * in the endpoint size register and then working it out from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * the amount we loaded for the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) * We do this even for DMA, as the transfer may have incremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) * past the end of the buffer (DMA transfers are always 32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) * aligned).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (size_left < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) dev_err(hsotg->dev, "error parsing DDMA results %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) size_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) size_done = hs_ep->size_loaded - size_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) size_done += hs_ep->last_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) if (hs_req->req.actual != size_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) __func__, hs_req->req.actual, size_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) hs_req->req.actual = size_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if (!size_left && hs_req->req.actual < hs_req->req.length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (hs_ep->send_zlp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) hs_ep->send_zlp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) if (!using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dwc2_hsotg_program_zlp(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) /* transfer will be completed on next complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) /* Move to STATUS OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) dwc2_hsotg_ep0_zlp(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) /* Set actual frame number for completed transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) hs_req->req.frame_number = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) * @idx: Index of ep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) * @dir_in: Endpoint direction 1-in 0-out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) * Reads for endpoint with given index and direction, by masking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) * epint_reg with coresponding mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) unsigned int idx, int dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) u32 ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) u32 diepempmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) mask = dwc2_readl(hsotg, epmsk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) mask |= DXEPINT_SETUP_RCVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) ints = dwc2_readl(hsotg, epint_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) ints &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) return ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) * @hs_ep: The endpoint on which interrupt is asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) * This interrupt indicates that the endpoint has been disabled per the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) * application's request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) * in case of ISOC completes current request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) * For ISOC-OUT endpoints completes expired requests. If there is remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) * request starts it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) unsigned char idx = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) int dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) int epctl = dwc2_readl(hsotg, epctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) int dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) dctl |= DCTL_CGNPINNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) if (dctl & DCTL_GOUTNAKSTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dctl |= DCTL_CGOUTNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) if (!hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) if (list_empty(&hs_ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) __func__, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) hs_req = get_ep_head(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) if (hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) hs_req->req.frame_number = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) hs_req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) -ENODATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) /* Update current frame number value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) } while (dwc2_gadget_target_frame_elapsed(hs_ep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) * @ep: The endpoint on which interrupt is asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) * This is starting point for ISOC-OUT transfer, synchronization done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) * first out token received from host while corresponding EP is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) * Device does not know initial frame in which out token will come. For this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) * getting this interrupt SW starts calculation for next transfer frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) struct dwc2_hsotg *hsotg = ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) int dir_in = ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) if (dir_in || !ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) if (ep->target_frame == TARGET_FRAME_INITIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* Start first ISO Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) ep->target_frame = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) dwc2_gadget_start_isoc_ddma(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (ep->target_frame == TARGET_FRAME_INITIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) ep->target_frame = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) if (ep->interval > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) if (ep->target_frame & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) ctrl |= DXEPCTL_SETODDFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) ctrl |= DXEPCTL_SETEVENFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) while (dwc2_gadget_target_frame_elapsed(ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) hs_req = get_ep_head(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) if (hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) hs_req->req.frame_number = ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) hs_req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) dwc2_gadget_incr_frame_num(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) /* Update current frame number value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) if (!ep->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) dwc2_gadget_start_next_request(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) struct dwc2_hsotg_ep *hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) * dwc2_gadget_handle_nak - handle NAK interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) * @hs_ep: The endpoint on which interrupt is asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) * This is starting point for ISOC-IN transfer, synchronization done with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) * first IN token received from host while corresponding EP is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) * Device does not know when first one token will arrive from host. On first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) * sent in response to that as there was no data in FIFO. SW is basing on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * interrupt to obtain frame in which token has come and then based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) * interval calculates next frame for transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) struct dwc2_hsotg_req *hs_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (!dir_in || !hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) hs_ep->target_frame = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* In service interval mode target_frame must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) * be set to last (u)frame of the service interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) if (hsotg->params.service_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) /* Set target_frame to the first (u)frame of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * the service interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) hs_ep->target_frame &= ~hs_ep->interval + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) /* Set target_frame to the last (u)frame of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * the service interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) dwc2_gadget_dec_frame_num_by_one(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) dwc2_gadget_start_isoc_ddma(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) hs_ep->target_frame = hsotg->frame_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (hs_ep->interval > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * Disable nak interrupt when we have got the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * isoc in token. This can avoid nak interrupt storm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) * on the Rockchip platforms which don't support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * "OTG_MULTI_PROC_INTRPT", and all device endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) * share the same nak mask and interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) if (!(dwc2_readl(hsotg, GHWCFG2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) GHWCFG2_MULTI_PROC_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) mask = dwc2_readl(hsotg, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) mask &= ~DIEPMSK_NAKMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) dwc2_writel(hsotg, mask, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) ctrl = dwc2_readl(hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) DIEPCTL(hs_ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) if (hs_ep->target_frame & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) ctrl |= DXEPCTL_SETODDFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) ctrl |= DXEPCTL_SETEVENFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if (using_desc_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) if (ctrl & DXEPCTL_EPENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) hs_req = get_ep_head(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (hs_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) hs_req->req.frame_number = hs_ep->target_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) hs_req->req.actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) dwc2_gadget_incr_frame_num(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) /* Update current frame number value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (!hs_ep->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dwc2_gadget_start_next_request(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) * dwc2_hsotg_epint - handle an in/out endpoint interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) * @hsotg: The driver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) * @idx: The index for the endpoint (0..15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) * @dir_in: Set if this is an IN endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) * Process and clear any interrupt pending for an individual endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) int dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) u32 ints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) /* Clear endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) dwc2_writel(hsotg, ints, epint_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (!hs_ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) __func__, idx, dir_in ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) __func__, idx, dir_in ? "in" : "out", ints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* Don't process XferCompl interrupt if it is a setup packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) ints &= ~DXEPINT_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) * stage and xfercomplete was generated without SETUP phase done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) * interrupt. SW should parse received setup packet only after host's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) * exit from setup phase of control transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) ints &= ~DXEPINT_XFERCOMPL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) if (ints & DXEPINT_XFERCOMPL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) __func__, dwc2_readl(hsotg, epctl_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) dwc2_readl(hsotg, epsiz_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) /* In DDMA handle isochronous requests separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (using_desc_dma(hsotg) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) dwc2_gadget_complete_isoc_request_ddma(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) } else if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) * We get OutDone from the FIFO, so we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * need to look at completing IN requests here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * if operating slave mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) dwc2_hsotg_complete_in(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) if (idx == 0 && !hs_ep->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) } else if (using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) * We're using DMA, we need to fire an OutDone here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) * as we ignore the RXFIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) dwc2_hsotg_handle_outdone(hsotg, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (ints & DXEPINT_EPDISBLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) dwc2_gadget_handle_ep_disabled(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) if (ints & DXEPINT_OUTTKNEPDIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if (ints & DXEPINT_NAKINTRPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) dwc2_gadget_handle_nak(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) if (ints & DXEPINT_AHBERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) if (using_dma(hsotg) && idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) * this is the notification we've received a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) * setup packet. In non-DMA mode we'd get this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) * from the RXFIFO, instead we need to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) * the setup here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) dwc2_hsotg_handle_outdone(hsotg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (ints & DXEPINT_STSPHSERCVD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) /* Safety check EP0 state when STSPHSERCVD asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) /* Move to STATUS IN for DDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) if (!hsotg->delayed_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) dwc2_hsotg_ep0_zlp(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* In case of 3 stage Control Write with delayed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) * status, when Status IN transfer started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) * before STSPHSERCVD asserted, NAKSTS bit not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) * cleared by CNAK in dwc2_hsotg_start_req()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) * function. Clear now NAKSTS to allow complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) dwc2_set_bit(hsotg, DIEPCTL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) DXEPCTL_CNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if (ints & DXEPINT_BACK2BACKSETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) if (ints & DXEPINT_BNAINTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) if (hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) dwc2_gadget_handle_isoc_bna(hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) if (dir_in && !hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /* not sure if this is important, but we'll clear it anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if (ints & DXEPINT_INTKNTXFEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) /* this probably means something bad is happening */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) if (ints & DXEPINT_INTKNEPMIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) /* FIFO has space or is empty (see GAHBCFG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) if (hsotg->dedicated_fifos &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) ints & DXEPINT_TXFEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) if (!using_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) dwc2_hsotg_trytx(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) * Handle updating the device settings after the enumeration phase has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) * been completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) u32 dsts = dwc2_readl(hsotg, DSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) int ep0_mps = 0, ep_mps = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) * This should signal the finish of the enumeration phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) * of the USB handshaking, so we should now know what rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) * we connected at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) * note, since we're limited by the size of transfer on EP0, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) * it seems IN transfers must be a even number of packets we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) * not advertise a 64byte MPS on EP0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* catch both EnumSpd_FS and EnumSpd_FS48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) case DSTS_ENUMSPD_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) case DSTS_ENUMSPD_FS48:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) hsotg->gadget.speed = USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) ep0_mps = EP0_MPS_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) ep_mps = 1023;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) case DSTS_ENUMSPD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) hsotg->gadget.speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) ep0_mps = EP0_MPS_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) ep_mps = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) case DSTS_ENUMSPD_LS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) hsotg->gadget.speed = USB_SPEED_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) ep0_mps = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) ep_mps = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) * note, we don't actually support LS in this driver at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) * moment, and the documentation seems to imply that it isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) * supported by the PHYs on some of the devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) dev_info(hsotg->dev, "new device is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) usb_speed_string(hsotg->gadget.speed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) * we should now know the maximum packet size for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) * endpoint, so set the endpoints to a default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) if (ep0_mps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* Initialize ep0 for both in and out directions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) for (i = 1; i < hsotg->num_of_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) if (hsotg->eps_in[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) if (hsotg->eps_out[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) /* ensure after enumeration our EP0 is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) dwc2_readl(hsotg, DIEPCTL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) dwc2_readl(hsotg, DOEPCTL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) * kill_all_requests - remove all requests from the endpoint's queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) * @ep: The endpoint the requests may be on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) * @result: The result code to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) * Go through the requests on the given endpoint and mark them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) * completed with the given result code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) static void kill_all_requests(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) struct dwc2_hsotg_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) int result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) ep->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) while (!list_empty(&ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) struct dwc2_hsotg_req *req = get_ep_head(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) dwc2_hsotg_complete_request(hsotg, ep, req, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (!hsotg->dedicated_fifos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) if (size < ep->fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) * dwc2_hsotg_disconnect - disconnect service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) * The device has been disconnected. Remove all current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) * transactions and signal the gadget driver that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) * has happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) unsigned int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) if (!hsotg->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) hsotg->connected = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) hsotg->test_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) /* all endpoints should be shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) for (ep = 0; ep < hsotg->num_of_eps; ep++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) if (hsotg->eps_in[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) kill_all_requests(hsotg, hsotg->eps_in[ep],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (hsotg->eps_out[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) kill_all_requests(hsotg, hsotg->eps_out[ep],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) call_gadget(hsotg, disconnect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) hsotg->lx_state = DWC2_L3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) * @hsotg: The device state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) * @periodic: True if this is a periodic FIFO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) struct dwc2_hsotg_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) int epno, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) /* look through for any more data to transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) for (epno = 0; epno < hsotg->num_of_eps; epno++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) ep = index_to_ep(hsotg, epno, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) if (!ep->dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) if ((periodic && !ep->periodic) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) (!periodic && ep->periodic))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) ret = dwc2_hsotg_trytx(hsotg, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) /* IRQ flags which will trigger a retry around the IRQ loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) GINTSTS_PTXFEMP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) GINTSTS_RXFLVL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) * dwc2_hsotg_core_init - issue softreset to the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) * @hsotg: The device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) * @is_usb_reset: Usb resetting flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) * Issue a soft reset to the core, and await the core finishing it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) bool is_usb_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) u32 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) u32 usbcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) u32 dcfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) /* Kill any ep0 requests as controller will be reinitialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) if (!is_usb_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) if (dwc2_core_reset(hsotg, true))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) /* all endpoints should be shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) for (ep = 1; ep < hsotg->num_of_eps; ep++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) if (hsotg->eps_in[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) if (hsotg->eps_out[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) * we must now enable ep0 ready for host detection and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) * set configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) /* keep other bits untouched (so e.g. forced modes are not lost) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) usbcfg = dwc2_readl(hsotg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) usbcfg |= GUSBCFG_TOUTCAL(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) /* remove the HNP/SRP and set the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) dwc2_writel(hsotg, usbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) dwc2_phy_init(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) dwc2_hsotg_init_fifo(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) if (!is_usb_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) dcfg |= DCFG_EPMISCNT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) switch (hsotg->params.speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) case DWC2_SPEED_PARAM_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) dcfg |= DCFG_DEVSPD_LS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) case DWC2_SPEED_PARAM_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) dcfg |= DCFG_DEVSPD_FS48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) dcfg |= DCFG_DEVSPD_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) dcfg |= DCFG_DEVSPD_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) if (hsotg->params.ipg_isoc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) dcfg |= DCFG_IPG_ISOC_SUPPORDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) dwc2_writel(hsotg, dcfg, DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) /* Clear any pending OTG interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) dwc2_writel(hsotg, 0xffffffff, GOTGINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) /* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) GINTSTS_USBRST | GINTSTS_RESETDET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) GINTSTS_ENUMDONE | GINTSTS_OTGINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) GINTSTS_USBSUSP | GINTSTS_WKUPINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) GINTSTS_LPMTRANRCVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) if (!using_desc_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) if (!hsotg->params.external_id_pin_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) intmsk |= GINTSTS_CONIDSTSCHNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) dwc2_writel(hsotg, intmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) if (using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) hsotg->params.ahbcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) /* Set DDMA mode support in the core if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) if (using_desc_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) (GAHBCFG_NP_TXF_EMP_LVL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) GAHBCFG_P_TXF_EMP_LVL) : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) GAHBCFG_GLBL_INTR_EN, GAHBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) * when we have no data to transfer. Otherwise we get being flooded by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) * don't need XferCompl, we get that from RXFIFO in slave mode. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) * DMA mode we may need this and StsPhseRcvd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) DOEPMSK_STSPHSERCVDMSK) : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) DOEPMSK_SETUPMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) /* Enable BNA interrupt for DDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) /* Enable Service Interval mode if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (using_desc_dma(hsotg) && hsotg->params.service_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) dwc2_writel(hsotg, 0, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) dwc2_readl(hsotg, DIEPCTL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) dwc2_readl(hsotg, DOEPCTL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) /* enable in and out endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) * Enable the RXFIFO when in slave mode, as this is how we collect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) * the data. In DMA mode, we get events from the FIFO but also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) * things we cannot process, so do not use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) if (!using_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) /* Enable interrupts for EP0 in and out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) if (!is_usb_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) udelay(10); /* see openiboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) * DxEPCTL_USBActEp says RO in manual, but seems to be set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) * writing to the EPCTL register..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) /* set to read 1 8byte packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) DXEPCTL_CNAK | DXEPCTL_EPENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) DXEPCTL_USBACTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) DOEPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /* enable, but don't activate EP0in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) DXEPCTL_USBACTEP, DIEPCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* clear global NAKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) if (!is_usb_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) val |= DCTL_SFTDISCON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) dwc2_set_bit(hsotg, DCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) /* configure the core to support LPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) dwc2_gadget_init_lpm(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /* program GREFCLK register if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) if (using_desc_dma(hsotg) && hsotg->params.service_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) dwc2_gadget_program_ref_clk(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) /* must be at-least 3ms to allow bus to see disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) mdelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) dwc2_hsotg_enqueue_setup(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) dwc2_readl(hsotg, DIEPCTL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) dwc2_readl(hsotg, DOEPCTL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) /* set the soft-disconnect bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) /* remove the soft-disconnect and let's go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) * @hsotg: The device state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) * This interrupt indicates one of the following conditions occurred while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * transmitting an ISOC transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) * - Corrupted IN Token for ISOC EP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) * - Packet not complete in FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) * The following actions will be taken:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) * - Determine the EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) struct dwc2_hsotg_ep *hs_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) u32 epctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) u32 daintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) daintmsk = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) for (idx = 1; idx < hsotg->num_of_eps; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) hs_ep = hsotg->eps_in[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) /* Proceed only unmasked ISOC EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) if ((epctrl & DXEPCTL_EPENA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) epctrl |= DXEPCTL_SNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) epctrl |= DXEPCTL_EPDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) * @hsotg: The device state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) * This interrupt indicates one of the following conditions occurred while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) * transmitting an ISOC transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) * - Corrupted OUT Token for ISOC EP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) * - Packet not complete in FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) * The following actions will be taken:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) * - Determine the EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) u32 gintsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) u32 daintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) u32 epctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) struct dwc2_hsotg_ep *hs_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) daintmsk = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) daintmsk >>= DAINT_OUTEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) for (idx = 1; idx < hsotg->num_of_eps; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) hs_ep = hsotg->eps_out[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) /* Proceed only unmasked ISOC EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) if ((epctrl & DXEPCTL_EPENA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) dwc2_gadget_target_frame_elapsed(hs_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) /* Unmask GOUTNAKEFF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) gintmsk |= GINTSTS_GOUTNAKEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) gintsts = dwc2_readl(hsotg, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) * dwc2_hsotg_irq - handle device interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) * @irq: The IRQ number triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) * @pw: The pw value when registered the handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) struct dwc2_hsotg *hsotg = pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) int retry_count = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) u32 gintsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) if (!dwc2_is_device_mode(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) spin_lock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) irq_retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) gintsts = dwc2_readl(hsotg, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) gintsts &= gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) if (gintsts & GINTSTS_RESETDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) /* This event must be used only if controller is suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) if (hsotg->lx_state == DWC2_L2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) dwc2_exit_partial_power_down(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) u32 connected = hsotg->connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) dwc2_readl(hsotg, GNPTXSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) /* Report disconnection if it is not already done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) dwc2_hsotg_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) /* Reset device address to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) if (usb_status & GOTGCTL_BSESVLD && connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) dwc2_hsotg_core_init_disconnected(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if (gintsts & GINTSTS_ENUMDONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) dwc2_hsotg_irq_enumdone(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) u32 daint = dwc2_readl(hsotg, DAINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) u32 daint_out, daint_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) daint &= daintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) daint_out = daint >> DAINT_OUTEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) for (ep = 0; ep < hsotg->num_of_eps && daint_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) ep++, daint_out >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) if (daint_out & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) dwc2_hsotg_epint(hsotg, ep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) for (ep = 0; ep < hsotg->num_of_eps && daint_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) ep++, daint_in >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) if (daint_in & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) dwc2_hsotg_epint(hsotg, ep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) /* check both FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) if (gintsts & GINTSTS_NPTXFEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) dev_dbg(hsotg->dev, "NPTxFEmp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) * Disable the interrupt to stop it happening again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) * unless one of these endpoint routines decides that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) * it needs re-enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) dwc2_hsotg_irq_fifoempty(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) if (gintsts & GINTSTS_PTXFEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) dev_dbg(hsotg->dev, "PTxFEmp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) /* See note in GINTSTS_NPTxFEmp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) dwc2_hsotg_irq_fifoempty(hsotg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) if (gintsts & GINTSTS_RXFLVL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) * we need to retry dwc2_hsotg_handle_rx if this is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) * set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) dwc2_hsotg_handle_rx(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) if (gintsts & GINTSTS_ERLYSUSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) * these next two seem to crop-up occasionally causing the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) * to shutdown the USB transfer, so try clearing them and logging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) * the occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) if (gintsts & GINTSTS_GOUTNAKEFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) u32 epctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) u32 gintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) u32 daintmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) struct dwc2_hsotg_ep *hs_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) daintmsk = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) daintmsk >>= DAINT_OUTEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) /* Mask this interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) gintmsk = dwc2_readl(hsotg, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) gintmsk &= ~GINTSTS_GOUTNAKEFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) dwc2_writel(hsotg, gintmsk, GINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) for (idx = 1; idx < hsotg->num_of_eps; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) hs_ep = hsotg->eps_out[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) /* Proceed only unmasked ISOC EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) if (BIT(idx) & ~daintmsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) //ISOC Ep's only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) epctrl |= DXEPCTL_SNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) epctrl |= DXEPCTL_EPDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) //Non-ISOC EP's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) if (hs_ep->halted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) if (!(epctrl & DXEPCTL_EPENA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) epctrl |= DXEPCTL_EPENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) epctrl |= DXEPCTL_EPDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) epctrl |= DXEPCTL_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) if (gintsts & GINTSTS_GINNAKEFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) dev_info(hsotg->dev, "GINNakEff triggered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) dwc2_hsotg_dump(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) if (gintsts & GINTSTS_INCOMPL_SOIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) dwc2_gadget_handle_incomplete_isoc_in(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) if (gintsts & GINTSTS_INCOMPL_SOOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) dwc2_gadget_handle_incomplete_isoc_out(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) * if we've had fifo events, we should try and go around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) * loop again to see if there's any point in returning yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) goto irq_retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) /* Check WKUP_ALERT interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) if (hsotg->params.service_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) dwc2_gadget_wkup_alert_handler(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) spin_unlock(&hsotg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) struct dwc2_hsotg_ep *hs_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) u32 epctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) u32 epint_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) DOEPCTL(hs_ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) DOEPINT(hs_ep->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) hs_ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) if (hs_ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) if (hsotg->dedicated_fifos || hs_ep->periodic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) /* Wait for Nak effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) DXEPINT_INEPNAKEFF, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) "%s: timeout DIEPINT.NAKEFF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) /* Wait for Nak effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) GINTSTS_GINNAKEFF, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) "%s: timeout GINTSTS.GINNAKEFF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) /* Mask GINTSTS_GOUTNAKEFF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) if (!using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) /* Wait for GINTSTS_RXFLVL interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) GINTSTS_RXFLVL, 100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) * Pop GLOBAL OUT NAK status packet from RxFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) * to assert GOUTNAKEFF interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) dwc2_readl(hsotg, GRXSTSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) /* Wait for global nak to take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) GINTSTS_GOUTNAKEFF, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) /* Disable ep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) /* Wait for ep to be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) dev_warn(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) "%s: timeout DOEPCTL.EPDisable\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) /* Clear EPDISBLD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) if (hs_ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) unsigned short fifo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) if (hsotg->dedicated_fifos || hs_ep->periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) fifo_index = hs_ep->fifo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) fifo_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) /* Flush TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) dwc2_flush_tx_fifo(hsotg, fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) if (!hsotg->dedicated_fifos && !hs_ep->periodic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) /* Remove global NAKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) * dwc2_hsotg_ep_enable - enable the given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) * @ep: The USB endpint to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) * @desc: The USB endpoint descriptor to configure with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) * This is called from the USB gadget code's usb_ep_enable().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) unsigned int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) u32 epctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) u32 epctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) u32 mps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) u32 mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) unsigned int dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) unsigned int i, val, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) unsigned char ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) int desc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) desc->wMaxPacketSize, desc->bInterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) /* not to be called for EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) if (dir_in != hs_ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) mps = usb_endpoint_maxp(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) mc = usb_endpoint_maxp_mult(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) /* ISOC IN in DDMA supported bInterval up to 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) dir_in && desc->bInterval > 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) /* High bandwidth ISOC OUT in DDMA not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) !dir_in && mc > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) epctrl = dwc2_readl(hsotg, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) __func__, epctrl, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) desc_num = MAX_DMA_DESC_NUM_GENERIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) /* Allocate DMA descriptor chain for non-ctrl endpoints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) desc_num * sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) &hs_ep->desc_list_dma, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) if (!hs_ep->desc_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) epctrl |= DXEPCTL_MPS(mps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) * mark the endpoint as active, otherwise the core may ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) * transactions entirely for this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) epctrl |= DXEPCTL_USBACTEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) /* update the endpoint state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) /* default, set to non-periodic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) hs_ep->isochronous = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) hs_ep->periodic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) hs_ep->halted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) hs_ep->interval = desc->bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) switch (ep_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) epctrl |= DXEPCTL_EPTYPE_ISO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) epctrl |= DXEPCTL_SETEVENFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) hs_ep->isochronous = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) hs_ep->interval = 1 << (desc->bInterval - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) hs_ep->target_frame = TARGET_FRAME_INITIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) hs_ep->next_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) hs_ep->compl_desc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) if (dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) hs_ep->periodic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) mask = dwc2_readl(hsotg, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) mask |= DIEPMSK_NAKMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) dwc2_writel(hsotg, mask, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) epctrl |= DXEPCTL_SNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) mask = dwc2_readl(hsotg, DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) mask |= DOEPMSK_OUTTKNEPDISMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) dwc2_writel(hsotg, mask, DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) epctrl |= DXEPCTL_EPTYPE_BULK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) hs_ep->periodic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) if (hsotg->gadget.speed == USB_SPEED_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) hs_ep->interval = 1 << (desc->bInterval - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) epctrl |= DXEPCTL_EPTYPE_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) * if the hardware has dedicated fifos, we must give each IN EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) * a unique tx-fifo even if it is non-periodic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) if (dir_in && hsotg->dedicated_fifos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) u32 fifo_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) u32 fifo_size = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) size = hs_ep->ep.maxpacket * hs_ep->mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) for (i = 1; i <= fifo_count; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) if (hsotg->fifo_map & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) val = dwc2_readl(hsotg, DPTXFSIZN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) if (val < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) /* Search for smallest acceptable fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) if (val < fifo_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) fifo_size = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) fifo_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) if (!fifo_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) dev_err(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) "%s: No suitable fifo found\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) hsotg->fifo_map |= 1 << fifo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) epctrl |= DXEPCTL_TXFNUM(fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) hs_ep->fifo_index = fifo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) hs_ep->fifo_size = fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) /* for non control endpoints, set PID to D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) if (index && !hs_ep->isochronous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) epctrl |= DXEPCTL_SETD0PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) /* WA for Full speed ISOC IN in DDMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) * By Clear NAK status of EP, core will send ZLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) * to IN token and assert NAK interrupt relying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) * on TxFIFO status only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) if (hsotg->gadget.speed == USB_SPEED_FULL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) hs_ep->isochronous && dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) /* The WA applies only to core versions from 2.72a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * to 4.00a (including both). Also for FS_IOT_1.00a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) * and HS_IOT_1.00a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) gsnpsid <= DWC2_CORE_REV_4_00a) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) gsnpsid == DWC2_FS_IOT_REV_1_00a ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) gsnpsid == DWC2_HS_IOT_REV_1_00a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) epctrl |= DXEPCTL_CNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) __func__, epctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) dwc2_writel(hsotg, epctrl, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) __func__, dwc2_readl(hsotg, epctrl_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) /* enable the endpoint interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) error2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) dmam_free_coherent(hsotg->dev, desc_num *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) sizeof(struct dwc2_dma_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) hs_ep->desc_list, hs_ep->desc_list_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) hs_ep->desc_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) * dwc2_hsotg_ep_disable - disable given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) * @ep: The endpoint to disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) int dir_in = hs_ep->dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) u32 epctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) if (ep == &hsotg->eps_out[0]->ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) ctrl = dwc2_readl(hsotg, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) if (ctrl & DXEPCTL_EPENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) ctrl &= ~DXEPCTL_EPENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) ctrl &= ~DXEPCTL_USBACTEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) ctrl |= DXEPCTL_SNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) dwc2_writel(hsotg, ctrl, epctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) /* disable endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) /* terminate all requests with shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) hs_ep->fifo_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) hs_ep->fifo_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) struct dwc2_hsotg *hsotg = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) ret = dwc2_hsotg_ep_disable(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) * on_list - check request is on the given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) * @ep: The endpoint to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) * @test: The request to test if it is on the endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) struct dwc2_hsotg_req *req, *treq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) list_for_each_entry_safe(req, treq, &ep->queue, queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) if (req == test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) * dwc2_hsotg_ep_dequeue - dequeue given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) * @ep: The endpoint to dequeue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) * @req: The request to be removed from a queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) struct dwc2_hsotg_req *hs_req = our_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) struct dwc2_hsotg *hs = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) spin_lock_irqsave(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) if (!on_list(hs_ep, hs_req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) spin_unlock_irqrestore(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) /* Dequeue already started request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) if (req == &hs_ep->req->req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) spin_unlock_irqrestore(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) * @ep: The endpoint to set halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) * @value: Set or unset the halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) * the endpoint is busy processing requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) * We need to stall the endpoint immediately if request comes from set_feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) * protocol command handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) struct dwc2_hsotg *hs = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) int index = hs_ep->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) u32 epreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) u32 epctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) u32 xfertype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) if (index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) dwc2_hsotg_stall_ep0(hs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) dev_warn(hs->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) "%s: can't clear halt on ep0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) if (hs_ep->isochronous) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) if (!now && value && !list_empty(&hs_ep->queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) if (hs_ep->dir_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) epreg = DIEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) epctl = dwc2_readl(hs, epreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) if (epctl & DXEPCTL_EPENA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) epctl |= DXEPCTL_EPDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) epctl &= ~DXEPCTL_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) xfertype = epctl & DXEPCTL_EPTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) if (xfertype == DXEPCTL_EPTYPE_BULK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) epctl |= DXEPCTL_SETD0PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) dwc2_writel(hs, epctl, epreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) epreg = DOEPCTL(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) epctl = dwc2_readl(hs, epreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) /* Unmask GOUTNAKEFF interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) // STALL bit will be set in GOUTNAKEFF interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) epctl &= ~DXEPCTL_STALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) xfertype = epctl & DXEPCTL_EPTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) if (xfertype == DXEPCTL_EPTYPE_BULK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) xfertype == DXEPCTL_EPTYPE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) epctl |= DXEPCTL_SETD0PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) dwc2_writel(hs, epctl, epreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) hs_ep->halted = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) * @ep: The endpoint to set halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) * @value: Set or unset the halt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) struct dwc2_hsotg *hs = hs_ep->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) spin_lock_irqsave(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) ret = dwc2_hsotg_ep_sethalt(ep, value, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) spin_unlock_irqrestore(&hs->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) .enable = dwc2_hsotg_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) .disable = dwc2_hsotg_ep_disable_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) .alloc_request = dwc2_hsotg_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) .free_request = dwc2_hsotg_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) .queue = dwc2_hsotg_ep_queue_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) .dequeue = dwc2_hsotg_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) .set_halt = dwc2_hsotg_ep_sethalt_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) /* note, don't believe we have any call for the fifo routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) * dwc2_hsotg_init - initialize the usb core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) * @hsotg: The driver state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) /* unmask subset of endpoint interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) dwc2_writel(hsotg, 0, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) /* Be in disconnected state until gadget is registered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) /* setup fifos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) dwc2_readl(hsotg, GRXFSIZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) dwc2_readl(hsotg, GNPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) dwc2_hsotg_init_fifo(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) if (using_dma(hsotg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) * dwc2_hsotg_udc_start - prepare the udc for work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) * @driver: The usb gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) * Perform initialization to prepare udc device and driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) * to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) if (!hsotg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) pr_err("%s: called with no device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) if (!driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) dev_err(hsotg->dev, "%s: no driver\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) if (driver->max_speed < USB_SPEED_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) dev_err(hsotg->dev, "%s: bad speed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) if (!driver->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) WARN_ON(hsotg->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) driver->driver.bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) hsotg->driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) hsotg->gadget.dev.of_node = hsotg->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) hsotg->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) ret = dwc2_lowlevel_hw_enable(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) if (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) if (!hsotg->ll_phy_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) ret = dwc2_lowlevel_phy_enable(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) if (!IS_ERR_OR_NULL(hsotg->uphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) if (dwc2_hw_is_device(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) dwc2_hsotg_init(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) dwc2_hsotg_core_init_disconnected(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) hsotg->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) gadget->sg_supported = using_desc_dma(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) hsotg->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) * dwc2_hsotg_udc_stop - stop the udc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) * Stop udc hw block and stay tunned for future transmissions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) if (!hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) /* all endpoints should be shutdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) for (ep = 1; ep < hsotg->num_of_eps; ep++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) if (hsotg->eps_in[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) if (hsotg->eps_out[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) hsotg->driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) hsotg->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) hsotg->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) if (!IS_ERR_OR_NULL(hsotg->uphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) otg_set_peripheral(hsotg->uphy->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) dwc2_lowlevel_hw_disable(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) if (hsotg->dr_mode == USB_DR_MODE_OTG && dwc2_is_device_mode(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) if (hsotg->ll_phy_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) dwc2_lowlevel_phy_disable(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) * dwc2_hsotg_gadget_getframe - read the frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) * Read the {micro} frame number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) return dwc2_hsotg_read_frameno(to_hsotg(gadget));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) * @is_selfpowered: Whether the device is self-powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) * Set if the device is self or bus powered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) int is_selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) gadget->is_selfpowered = !!is_selfpowered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) * dwc2_hsotg_pullup - connect/disconnect the USB PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) * @is_on: Current state of the USB PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) * Connect/Disconnect the USB PHY pullup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) hsotg->op_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) /* Don't modify pullup state while in host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) hsotg->enabled = is_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) hsotg->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) dwc2_hsotg_core_init_disconnected(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) /* Enable ACG feature in device mode,if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) dwc2_enable_acg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) dwc2_hsotg_core_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) dwc2_hsotg_core_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) dwc2_hsotg_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) hsotg->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) hsotg->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) * If controller is hibernated, it must exit from power_down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) * before being initialized / de-initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) if (hsotg->lx_state == DWC2_L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) dwc2_exit_partial_power_down(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) if (is_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) hsotg->op_state = OTG_STATE_B_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) dwc2_hsotg_core_init_disconnected(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) if (hsotg->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) /* Enable ACG feature in device mode,if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) dwc2_enable_acg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) dwc2_hsotg_core_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) dwc2_hsotg_core_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) dwc2_hsotg_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) * dwc2_hsotg_vbus_draw - report bMaxPower field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) * @gadget: The usb gadget state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) * @mA: Amount of current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) * Report how much power the device may consume to the phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) struct dwc2_hsotg *hsotg = to_hsotg(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) if (IS_ERR_OR_NULL(hsotg->uphy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) return usb_phy_set_power(hsotg->uphy, mA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) .get_frame = dwc2_hsotg_gadget_getframe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) .set_selfpowered = dwc2_hsotg_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) .udc_start = dwc2_hsotg_udc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) .udc_stop = dwc2_hsotg_udc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) .pullup = dwc2_hsotg_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) .vbus_session = dwc2_hsotg_vbus_session,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) .vbus_draw = dwc2_hsotg_vbus_draw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) * dwc2_hsotg_initep - initialise a single endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) * @hsotg: The device state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) * @hs_ep: The endpoint to be initialised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) * @epnum: The endpoint number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) * @dir_in: True if direction is in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) * Initialise the given endpoint (as part of the probe and device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) * creation) to give to the gadget driver. Setup the endpoint name, any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) * direction information and other state that may be required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) struct dwc2_hsotg_ep *hs_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) int epnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) bool dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) char *dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) if (epnum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) dir = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) else if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) dir = "in";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) dir = "out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) hs_ep->dir_in = dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) hs_ep->index = epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) INIT_LIST_HEAD(&hs_ep->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) INIT_LIST_HEAD(&hs_ep->ep.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) /* add to the list of endpoints known by the gadget driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) if (epnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) hs_ep->parent = hsotg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) hs_ep->ep.name = hs_ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) usb_ep_set_maxpacket_limit(&hs_ep->ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) epnum ? 1024 : EP0_MPS_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) if (epnum == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) hs_ep->ep.caps.type_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) hs_ep->ep.caps.type_iso = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) hs_ep->ep.caps.type_bulk = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) hs_ep->ep.caps.type_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) hs_ep->ep.caps.dir_in = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) hs_ep->ep.caps.dir_out = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) * if we're using dma, we need to set the next-endpoint pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) * to be something valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) if (using_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) if (dir_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) dwc2_writel(hsotg, next, DIEPCTL(epnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) dwc2_writel(hsotg, next, DOEPCTL(epnum));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) * dwc2_hsotg_hw_cfg - read HW configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) * Read the USB core HW configuration registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) u32 ep_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) /* check hardware configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) /* Add ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) hsotg->num_of_eps++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) sizeof(struct dwc2_hsotg_ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) if (!hsotg->eps_in[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) /* Same dwc2_hsotg_ep is used in both directions for ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) hsotg->eps_out[0] = hsotg->eps_in[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) cfg = hsotg->hw_params.dev_ep_dirs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) ep_type = cfg & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) /* Direction in or both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) if (!(ep_type & 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) if (!hsotg->eps_in[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) /* Direction out or both */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) if (!(ep_type & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) if (!hsotg->eps_out[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) hsotg->num_of_eps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) hsotg->dedicated_fifos ? "dedicated" : "shared",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) hsotg->fifo_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) * dwc2_hsotg_dump - dump state of the udc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) struct device *dev = hsotg->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) dwc2_readl(hsotg, DIEPMSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) /* show periodic fifo settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) for (idx = 1; idx < hsotg->num_of_eps; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) val = dwc2_readl(hsotg, DPTXFSIZN(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) val >> FIFOSIZE_DEPTH_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) val & FIFOSIZE_STARTADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) for (idx = 0; idx < hsotg->num_of_eps; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) dwc2_readl(hsotg, DIEPCTL(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) dwc2_readl(hsotg, DIEPTSIZ(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) dwc2_readl(hsotg, DIEPDMA(idx)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) val = dwc2_readl(hsotg, DOEPCTL(idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) idx, dwc2_readl(hsotg, DOEPCTL(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) dwc2_readl(hsotg, DOEPTSIZ(idx)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) dwc2_readl(hsotg, DOEPDMA(idx)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) * dwc2_gadget_init - init function for gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) struct device *dev = hsotg->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) int epnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) /* Dump fifo information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) hsotg->params.g_np_tx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) hsotg->gadget.max_speed = USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) hsotg->gadget.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) hsotg->remote_wakeup_allowed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) if (hsotg->params.lpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) hsotg->gadget.lpm_capable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) if (hsotg->dr_mode == USB_DR_MODE_OTG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) hsotg->gadget.is_otg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) hsotg->op_state = OTG_STATE_B_PERIPHERAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) ret = dwc2_hsotg_hw_cfg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) if (!hsotg->ctrl_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) if (!hsotg->ep0_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) if (using_desc_dma(hsotg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) IRQF_SHARED, dev_name(hsotg->dev), hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) dev_err(dev, "cannot claim IRQ for gadget\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) /* hsotg->num_of_eps holds number of EPs other than ep0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) if (hsotg->num_of_eps == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) dev_err(dev, "wrong number of EPs (zero)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) /* setup endpoint information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) INIT_LIST_HEAD(&hsotg->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) /* allocate EP0 request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) if (!hsotg->ctrl_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) dev_err(dev, "failed to allocate ctrl req\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) /* initialise the endpoints now the core has been initialised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) if (hsotg->eps_in[epnum])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) epnum, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) if (hsotg->eps_out[epnum])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) epnum, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) dwc2_hsotg_dump(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) * dwc2_hsotg_remove - remove function for hsotg driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) usb_del_gadget_udc(&hsotg->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) if (hsotg->lx_state != DWC2_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) if (hsotg->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) dev_info(hsotg->dev, "suspending usb gadget %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) hsotg->driver->driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) if (hsotg->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) dwc2_hsotg_core_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) dwc2_hsotg_disconnect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) hsotg->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) for (ep = 1; ep < hsotg->num_of_eps; ep++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) if (hsotg->eps_in[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) if (hsotg->eps_out[ep])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) if (hsotg->lx_state == DWC2_L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) if (hsotg->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) dev_info(hsotg->dev, "resuming usb gadget %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) hsotg->driver->driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) spin_lock_irqsave(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) dwc2_hsotg_core_init_disconnected(hsotg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) if (hsotg->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) /* Enable ACG feature in device mode,if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) dwc2_enable_acg(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) dwc2_hsotg_core_connect(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) spin_unlock_irqrestore(&hsotg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) * dwc2_backup_device_registers() - Backup controller device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) * When suspending usb bus, registers needs to be backuped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) * if controller power is disabled once suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) struct dwc2_dregs_backup *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) dev_dbg(hsotg->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) /* Backup dev regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) dr = &hsotg->dr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) dr->dcfg = dwc2_readl(hsotg, DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) dr->dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) for (i = 0; i < hsotg->num_of_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) /* Backup IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) /* Ensure DATA PID is correctly configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) if (dr->diepctl[i] & DXEPCTL_DPID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) dr->diepctl[i] |= DXEPCTL_SETD1PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) dr->diepctl[i] |= DXEPCTL_SETD0PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) /* Backup OUT EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) /* Ensure DATA PID is correctly configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) if (dr->doepctl[i] & DXEPCTL_DPID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) dr->doepctl[i] |= DXEPCTL_SETD1PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) dr->doepctl[i] |= DXEPCTL_SETD0PID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) dr->valid = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) * dwc2_restore_device_registers() - Restore controller device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) * When resuming usb bus, device registers needs to be restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) * if controller power were disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) * Return: 0 if successful, negative error code otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) struct dwc2_dregs_backup *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) dev_dbg(hsotg->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) /* Restore dev regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) dr = &hsotg->dr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) if (!dr->valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) dev_err(hsotg->dev, "%s: no device registers to restore\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) dr->valid = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) if (!remote_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) dwc2_writel(hsotg, dr->dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) for (i = 0; i < hsotg->num_of_eps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) /* Restore IN EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /** WA for enabled EPx's IN in DDMA mode. On entering to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) * hibernation wrong value read and saved from DIEPDMAx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) * as result BNA interrupt asserted on hibernation exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) * by restoring from saved area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) if (hsotg->params.g_dma_desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) (dr->diepctl[i] & DXEPCTL_EPENA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) /* Restore OUT EPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) /* WA for enabled EPx's OUT in DDMA mode. On entering to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) * hibernation wrong value read and saved from DOEPDMAx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) * as result BNA interrupt asserted on hibernation exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) * by restoring from saved area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) if (hsotg->params.g_dma_desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) (dr->doepctl[i] & DXEPCTL_EPENA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) if (!hsotg->params.lpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) dwc2_writel(hsotg, val, GLPMCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) /* Unmask WKUP_ALERT Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) if (hsotg->params.service_interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) * @hsotg: Programming view of DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) val |= GREFCLK_REF_CLK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) val |= hsotg->params.sof_cnt_wkup_alert <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) dwc2_writel(hsotg, val, GREFCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) * Return non-zero if failed to enter to hibernation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) u32 gpwrdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) /* Change to L2(suspend) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) hsotg->lx_state = DWC2_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) dev_dbg(hsotg->dev, "Start of hibernation completed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) ret = dwc2_backup_global_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) dev_err(hsotg->dev, "%s: failed to backup global registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) ret = dwc2_backup_device_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) dev_err(hsotg->dev, "%s: failed to backup device registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) gpwrdn = GPWRDN_PWRDNRSTN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) gpwrdn |= GPWRDN_PMUACTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) /* Set flag to indicate that we are in hibernation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) hsotg->hibernated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) /* Enable interrupts from wake up logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) gpwrdn |= GPWRDN_PMUINTSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) /* Unmask device mode interrupts in GPWRDN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) gpwrdn |= GPWRDN_RST_DET_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) gpwrdn |= GPWRDN_LNSTSCHG_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) gpwrdn |= GPWRDN_STS_CHGINT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) /* Enable Power Down Clamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) gpwrdn |= GPWRDN_PWRDNCLMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) /* Switch off VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) gpwrdn |= GPWRDN_PWRDNSWTCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) /* Save gpwrdn register for further usage if stschng interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) dev_dbg(hsotg->dev, "Hibernation completed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) * dwc2_gadget_exit_hibernation()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) * This function is for exiting from Device mode hibernation by host initiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) * resume/reset and device initiated remote-wakeup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) * @hsotg: Programming view of the DWC_otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) * @rem_wakeup: indicates whether resume is initiated by Device or Host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) * @reset: indicates whether resume is initiated by Reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) * Return non-zero if failed to exit from hibernation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) int rem_wakeup, int reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) u32 pcgcctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) u32 gpwrdn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) u32 dctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) struct dwc2_gregs_backup *gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) struct dwc2_dregs_backup *dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) gr = &hsotg->gr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) dr = &hsotg->dr_backup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) if (!hsotg->hibernated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) dev_dbg(hsotg->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) "%s: called with rem_wakeup = %d reset = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) __func__, rem_wakeup, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (!reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) /* Clear all pending interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) /* De-assert Restore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) gpwrdn &= ~GPWRDN_RESTORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) if (!rem_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) pcgcctl = dwc2_readl(hsotg, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) dwc2_writel(hsotg, pcgcctl, PCGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) /* Restore GUSBCFG, DCFG and DCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) dwc2_writel(hsotg, dr->dcfg, DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) dwc2_writel(hsotg, dr->dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) /* De-assert Wakeup Logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) gpwrdn = dwc2_readl(hsotg, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) gpwrdn &= ~GPWRDN_PMUACTV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) dwc2_writel(hsotg, gpwrdn, GPWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) if (rem_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) /* Start Remote Wakeup Signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) /* Set Device programming done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) dctl |= DCTL_PWRONPRGDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) /* Wait for interrupts which must be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) /* Clear all pending interupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) dwc2_writel(hsotg, 0xffffffff, GINTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) /* Restore global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) ret = dwc2_restore_global_registers(hsotg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) dev_err(hsotg->dev, "%s: failed to restore registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) /* Restore device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) dev_err(hsotg->dev, "%s: failed to restore device registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) if (rem_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) dctl = dwc2_readl(hsotg, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) dctl &= ~DCTL_RMTWKUPSIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) dwc2_writel(hsotg, dctl, DCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) hsotg->hibernated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) hsotg->lx_state = DWC2_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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