Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Includes for cdc-acm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Mainly take from usbnet's cdc-ether part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * CMSPAR, some architectures can't have space and mark parity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifndef CMSPAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CMSPAR			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Major and minor numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ACM_TTY_MAJOR		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ACM_TTY_MINORS		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ACM_MINOR_INVALID	ACM_TTY_MINORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define USB_RT_ACM		(USB_TYPE_CLASS | USB_RECIP_INTERFACE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * Output control lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ACM_CTRL_DTR		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ACM_CTRL_RTS		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Input control lines and line errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ACM_CTRL_DCD		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define ACM_CTRL_DSR		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ACM_CTRL_BRK		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ACM_CTRL_RI		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ACM_CTRL_FRAMING	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ACM_CTRL_PARITY		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define ACM_CTRL_OVERRUN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * Internal driver structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * The only reason to have several buffers is to accommodate assumptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * in line disciplines. They ask for empty space amount, receive our URB size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * and proceed to issue several 1-character writes, assuming they will fit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * The very first write takes a complete URB. Fortunately, this only happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * when processing onlcr, so we only need 2 buffers. These values must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * powers of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ACM_NW  16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ACM_NR  16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct acm_wb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	dma_addr_t dmah;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct urb		*urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct acm		*instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	bool use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct acm_rb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int			size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned char		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dma_addr_t		dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int			index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct acm		*instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct acm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct usb_device *dev;				/* the corresponding usb device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct usb_interface *control;			/* control interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct usb_interface *data;			/* data interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned in, out;				/* i/o pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct tty_port port;			 	/* our tty port data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct urb *ctrlurb;				/* urbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 *ctrl_buffer;				/* buffers of urbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dma_addr_t ctrl_dma;				/* dma handles of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u8 *country_codes;				/* country codes from device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned int country_code_size;			/* size of this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int country_rel_date;			/* release date of version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct acm_wb wb[ACM_NW];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long read_urbs_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct urb *read_urbs[ACM_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct acm_rb read_buffers[ACM_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int rx_buflimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	spinlock_t read_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 *notification_buffer;			/* to reassemble fragmented notifications */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int nb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned int nb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int transmitting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	spinlock_t write_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bool disconnected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #		define EVENT_TTY_WAKEUP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #		define EVENT_RX_STALL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #		define ACM_THROTTLED	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #		define ACM_ERROR_DELAY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long urbs_in_error_delay;		/* these need to be restarted after a delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct usb_cdc_line_coding line;		/* bits, stop, parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct delayed_work dwork;		        /* work queue entry for various purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int ctrlin;				/* input control lines (DCD, DSR, RI, break, overruns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int ctrlout;				/* output control lines (DTR, RTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct async_icount iocount;			/* counters for control line changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct async_icount oldcount;			/* for comparison of counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	wait_queue_head_t wioctl;			/* for ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int writesize;				/* max packet size for the output bulk endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned int readsize,ctrlsize;			/* buffer sizes for freeing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int minor;				/* acm minor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned char clocal;				/* termios CLOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned int ctrl_caps;				/* control capabilities from the class specific header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned int susp_count;			/* number of suspended interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned int combined_interfaces:1;		/* control and data collapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u8 bInterval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct usb_anchor delayed;			/* writes queued for a device about to be woken */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned long quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* constants describing various quirks and errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NO_UNION_NORMAL			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SINGLE_RX_URB			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NO_CAP_LINE			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IGNORE_DEVICE			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QUIRK_CONTROL_LINE_STATE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLEAR_HALT_CONDITIONS		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SEND_ZERO_PACKET		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DISABLE_ECHO			BIT(7)