^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Jun Li
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file mainly handles OTG fsm, it includes OTG fsm operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * for HNP and SRP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * TODO List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - ADP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - OTG test device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/usb/chipidea.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "bits.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "otg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "otg_fsm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Add for otg: interact with user space app */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) a_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned size, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) next = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) size -= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) next += t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return PAGE_SIZE - size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) a_bus_req_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mutex_lock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (buf[0] == '0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ci->fsm.a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) } else if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* If a_bus_drop is TRUE, a_bus_req can't be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ci->fsm.a_bus_drop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ci->fsm.a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ci->gadget.host_request_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static DEVICE_ATTR_RW(a_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) a_bus_drop_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned size, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) next = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) size -= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) next += t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return PAGE_SIZE - size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) a_bus_drop_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mutex_lock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (buf[0] == '0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ci->fsm.a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ci->fsm.a_bus_drop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ci->fsm.a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static DEVICE_ATTR_RW(a_bus_drop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) b_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) char *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned size, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) next = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) size -= t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) next += t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PAGE_SIZE - size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) b_bus_req_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mutex_lock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (buf[0] == '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ci->fsm.b_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else if (buf[0] == '1') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ci->fsm.b_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ci->gadget.host_request_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static DEVICE_ATTR_RW(b_bus_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) a_clr_err_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (count > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mutex_lock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (buf[0] == '1')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ci->fsm.a_clr_err = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mutex_unlock(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static DEVICE_ATTR_WO(a_clr_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct attribute *inputs_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &dev_attr_a_bus_req.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &dev_attr_a_bus_drop.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &dev_attr_b_bus_req.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &dev_attr_a_clr_err.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct attribute_group inputs_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "inputs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .attrs = inputs_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Keep this list in the same order as timers indexed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static unsigned otg_timer_ms[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TA_WAIT_VRISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) TA_WAIT_VFALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TA_WAIT_BCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TA_AIDL_BDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) TB_ASE0_BRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TA_BIDL_ADIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TB_AIDL_BDIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) TB_SE0_SRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TB_SRP_FAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) TB_DATA_PLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) TB_SSEND_SRP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Add timer to active timer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void ci_otg_add_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long flags, timer_sec, timer_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (t >= NUM_OTG_FSM_TIMERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irqsave(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) timer_sec = otg_timer_ms[t] / MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) timer_nsec = (otg_timer_ms[t] % MSEC_PER_SEC) * NSEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ci->hr_timeouts[t] = ktime_add(ktime_get(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ktime_set(timer_sec, timer_nsec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ci->enabled_otg_timer_bits |= (1 << t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if ((ci->next_otg_timer == NUM_OTG_FSM_TIMERS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ktime_after(ci->hr_timeouts[ci->next_otg_timer],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ci->hr_timeouts[t])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ci->next_otg_timer = t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ci->hr_timeouts[t], NSEC_PER_MSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) HRTIMER_MODE_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spin_unlock_irqrestore(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Remove timer from active timer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void ci_otg_del_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long flags, enabled_timer_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((t >= NUM_OTG_FSM_TIMERS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) !(ci->enabled_otg_timer_bits & (1 << t)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irqsave(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ci->enabled_otg_timer_bits &= ~(1 << t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ci->next_otg_timer == t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ci->enabled_otg_timer_bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* No enabled timers after delete it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hrtimer_cancel(&ci->otg_fsm_hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Find the next timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) enabled_timer_bits = ci->enabled_otg_timer_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for_each_set_bit(cur_timer, &enabled_timer_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) NUM_OTG_FSM_TIMERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if ((next_timer == NUM_OTG_FSM_TIMERS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ktime_before(ci->hr_timeouts[next_timer],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ci->hr_timeouts[cur_timer]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) next_timer = cur_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (next_timer != NUM_OTG_FSM_TIMERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ci->next_otg_timer = next_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ci->hr_timeouts[next_timer], NSEC_PER_MSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) HRTIMER_MODE_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_unlock_irqrestore(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* OTG FSM timer handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int a_wait_vrise_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ci->fsm.a_wait_vrise_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int a_wait_vfall_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ci->fsm.a_wait_vfall_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int a_wait_bcon_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ci->fsm.a_wait_bcon_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int a_aidl_bdis_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ci->fsm.a_aidl_bdis_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int b_ase0_brst_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ci->fsm.b_ase0_brst_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int a_bidl_adis_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ci->fsm.a_bidl_adis_tmout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int b_aidl_bdis_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ci->fsm.a_bus_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int b_se0_srp_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ci->fsm.b_se0_srp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int b_srp_fail_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ci->fsm.b_srp_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int b_data_pls_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ci->fsm.b_srp_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ci->fsm.b_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ci->fsm.power_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ci->fsm.power_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) hw_write_otgsc(ci, OTGSC_HABA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pm_runtime_put(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int b_ssend_srp_tmout(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ci->fsm.b_ssend_srp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* only vbus fall below B_sess_vld in b_idle state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ci->fsm.otg->state == OTG_STATE_B_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Keep this list in the same order as timers indexed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int (*otg_timer_handlers[])(struct ci_hdrc *) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) a_wait_vrise_tmout, /* A_WAIT_VRISE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) a_wait_vfall_tmout, /* A_WAIT_VFALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) a_wait_bcon_tmout, /* A_WAIT_BCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) a_aidl_bdis_tmout, /* A_AIDL_BDIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) b_ase0_brst_tmout, /* B_ASE0_BRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) a_bidl_adis_tmout, /* A_BIDL_ADIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) b_aidl_bdis_tmout, /* B_AIDL_BDIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) b_se0_srp_tmout, /* B_SE0_SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) b_srp_fail_tmout, /* B_SRP_FAIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) NULL, /* A_WAIT_ENUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) b_data_pls_tmout, /* B_DATA_PLS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) b_ssend_srp_tmout, /* B_SSEND_SRP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Enable the next nearest enabled timer if have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static enum hrtimer_restart ci_otg_hrtimer_func(struct hrtimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ci_hdrc *ci = container_of(t, struct ci_hdrc, otg_fsm_hrtimer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ktime_t now, *timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long enabled_timer_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock_irqsave(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enabled_timer_bits = ci->enabled_otg_timer_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) now = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for_each_set_bit(cur_timer, &enabled_timer_bits, NUM_OTG_FSM_TIMERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ktime_compare(now, ci->hr_timeouts[cur_timer]) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ci->enabled_otg_timer_bits &= ~(1 << cur_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (otg_timer_handlers[cur_timer])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = otg_timer_handlers[cur_timer](ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if ((next_timer == NUM_OTG_FSM_TIMERS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ktime_before(ci->hr_timeouts[cur_timer],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ci->hr_timeouts[next_timer]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) next_timer = cur_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Enable the next nearest timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (next_timer < NUM_OTG_FSM_TIMERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) timeout = &ci->hr_timeouts[next_timer];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, *timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NSEC_PER_MSEC, HRTIMER_MODE_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ci->next_otg_timer = next_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_unlock_irqrestore(&ci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Initialize timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int ci_otg_init_timers(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) hrtimer_init(&ci->otg_fsm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ci->otg_fsm_hrtimer.function = ci_otg_hrtimer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* -------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Operations that will be called from OTG Finite State Machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* -------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (t < NUM_OTG_FSM_TIMERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ci_otg_add_timer(ci, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (t < NUM_OTG_FSM_TIMERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ci_otg_del_timer(ci, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * A-device drive vbus: turn on vbus regulator and enable port power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Data pulse irq should be disabled while vbus is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Enable power power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PORTSC_PP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ci->platdata->reg_vbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = regulator_enable(ci->platdata->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(ci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "Failed to enable vbus regulator, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Disable data pulse irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hw_write_otgsc(ci, OTGSC_DPIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fsm->a_srp_det = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) fsm->power_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ci->platdata->reg_vbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) regulator_disable(ci->platdata->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fsm->a_bus_drop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fsm->a_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Control data line by Run Stop bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void ci_otg_loc_conn(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Generate SOF by host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * In host mode, controller will automatically send SOF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Suspend will block the data on the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * This is controlled through usbcore by usb autosuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * so the usb device class driver need support autosuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * otherwise the bus suspend will not happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void ci_otg_loc_sof(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct usb_device *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!fsm->otg->host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) udev = usb_hub_find_child(fsm->otg->host->root_hub, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!udev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) usb_disable_autosuspend(udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_set_autosuspend_delay(&udev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) usb_enable_autosuspend(udev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Start SRP pulsing by data-line pulsing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * no v-bus pulsing followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void ci_otg_start_pulse(struct otg_fsm *fsm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Hardware Assistant Data pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_get(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ci_otg_add_timer(ci, B_DATA_PLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int ci_otg_start_host(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ci_role_stop(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ci_role_start(ci, CI_ROLE_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ci_role_stop(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ci_role_start(ci, CI_ROLE_GADGET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int ci_otg_start_gadget(struct otg_fsm *fsm, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) usb_gadget_vbus_connect(&ci->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) usb_gadget_vbus_disconnect(&ci->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct otg_fsm_ops ci_otg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .drv_vbus = ci_otg_drv_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .loc_conn = ci_otg_loc_conn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .loc_sof = ci_otg_loc_sof,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .start_pulse = ci_otg_start_pulse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .add_timer = ci_otg_fsm_add_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .del_timer = ci_otg_fsm_del_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .start_host = ci_otg_start_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .start_gadget = ci_otg_start_gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int ci_otg_fsm_work(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Don't do fsm transition for B device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * when there is no gadget class driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ci->fsm.id && !(ci->driver) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ci->fsm.otg->state < OTG_STATE_A_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pm_runtime_get_sync(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (otg_statemachine(&ci->fsm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ci->fsm.otg->state == OTG_STATE_A_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Further state change for cases:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * a_idle to b_idle; or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * a_idle to a_wait_vrise due to ID change(1->0), so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * B-dev becomes A-dev can try to start new session
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * consequently; or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * a_idle to a_wait_vrise when power up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if ((ci->fsm.id) || (ci->id_event) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) (ci->fsm.power_up)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Enable data pulse irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PORTSC_PP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ci->id_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ci->id_event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ci->fsm.b_sess_vld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ci->fsm.power_up = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Further transite to b_periphearl state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * when register gadget driver with vbus on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pm_runtime_mark_last_busy(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pm_runtime_put_autosuspend(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pm_runtime_put_sync(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Update fsm variables in each state if catching expected interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * called by otg fsm isr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void ci_otg_fsm_event(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 intr_sts, otg_bsess_vld, port_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct otg_fsm *fsm = &ci->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) intr_sts = hw_read_intr_status(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) switch (ci->fsm.otg->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case OTG_STATE_A_WAIT_BCON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) fsm->b_conn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fsm->a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case OTG_STATE_B_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fsm->b_sess_vld = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case OTG_STATE_B_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ci_otg_add_timer(ci, B_AIDL_BDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else if (intr_sts & USBi_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ci_otg_del_timer(ci, B_AIDL_BDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (fsm->a_bus_suspend == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fsm->a_bus_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case OTG_STATE_B_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if ((intr_sts & USBi_PCI) && !port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) fsm->a_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) fsm->b_bus_req = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case OTG_STATE_A_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (intr_sts & USBi_SLI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fsm->b_bus_suspend = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Init a timer to know how long this suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * will continue, if time out, indicates B no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * wants to be host role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ci_otg_add_timer(ci, A_BIDL_ADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (intr_sts & USBi_URI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ci_otg_del_timer(ci, A_BIDL_ADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (intr_sts & USBi_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (fsm->b_bus_suspend == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ci_otg_del_timer(ci, A_BIDL_ADIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) fsm->b_bus_suspend = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case OTG_STATE_A_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if ((intr_sts & USBi_PCI) && !port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) fsm->b_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* if gadget driver is binded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ci->driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* A device to be peripheral mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ci->gadget.is_a_peripheral = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case OTG_STATE_A_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if ((intr_sts & USBi_PCI) && !port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) fsm->b_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case OTG_STATE_B_WAIT_ACON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if ((intr_sts & USBi_PCI) && port_conn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) fsm->a_conn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * ci_otg_irq - otg fsm related irq handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * and also update otg fsm variable by monitoring usb host and udc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * state change interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * @ci: ci_hdrc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) irqreturn_t retval = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 otgsc, otg_int_src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct otg_fsm *fsm = &ci->fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) otgsc = hw_read_otgsc(ci, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fsm->id = (otgsc & OTGSC_ID) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (otg_int_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (otg_int_src & OTGSC_DPIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) fsm->a_srp_det = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) fsm->a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } else if (otg_int_src & OTGSC_IDIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (fsm->id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fsm->a_bus_drop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fsm->a_bus_req = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ci->id_event = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else if (otg_int_src & OTGSC_BSVIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (otgsc & OTGSC_BSV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fsm->b_sess_vld = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ci_otg_del_timer(ci, B_SSEND_SRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ci_otg_del_timer(ci, B_SRP_FAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fsm->b_ssend_srp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) fsm->b_sess_vld = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (fsm->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ci_otg_add_timer(ci, B_SSEND_SRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else if (otg_int_src & OTGSC_AVVIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (otgsc & OTGSC_AVV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fsm->a_vbus_vld = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fsm->a_vbus_vld = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fsm->b_conn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ci_otg_fsm_event(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ci_otg_queue_work(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ci->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ci->otg.phy = ci->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ci->otg.usb_phy = ci->usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ci->otg.gadget = &ci->gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ci->fsm.otg = &ci->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ci->fsm.power_up = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ci->fsm.otg->state = OTG_STATE_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ci->fsm.ops = &ci_otg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ci->gadget.hnp_polling_support = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ci->fsm.host_req_flag = devm_kzalloc(ci->dev, 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!ci->fsm.host_req_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_init(&ci->fsm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) retval = ci_otg_init_timers(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_err(ci->dev, "Couldn't init OTG timers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ci->enabled_otg_timer_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_dbg(ci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "Can't register sysfs attr group: %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Enable A vbus valid irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (ci->fsm.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ci->fsm.b_ssend_srp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ci->fsm.b_sess_vld =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Enable BSV irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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