^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Peter Chen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DRIVERS_USB_CHIPIDEA_OTG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DRIVERS_USB_CHIPIDEA_OTG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int ci_hdrc_otg_init(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) void ci_hdrc_otg_destroy(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum ci_role ci_otg_role(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void ci_handle_vbus_change(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static inline void ci_otg_queue_work(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) disable_irq_nosync(ci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) if (queue_work(ci->wq, &ci->work) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enable_irq(ci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif /* __DRIVERS_USB_CHIPIDEA_OTG_H */