Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * otg.c - ChipIdea USB IP core OTG driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Peter Chen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * are also included.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/usb/chipidea.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "bits.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "otg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "otg_fsm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * hw_read_otgsc returns otgsc register bits value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct ci_hdrc_cable *cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 val = hw_read(ci, OP_OTGSC, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	 * If using extcon framework for VBUS and/or ID signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	 * detection overwrite OTGSC register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	cable = &ci->platdata->vbus_extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (!IS_ERR(cable->edev) || ci->role_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		if (cable->changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			val |= OTGSC_BSVIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			val &= ~OTGSC_BSVIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		if (cable->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			val |= OTGSC_BSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			val &= ~OTGSC_BSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		if (cable->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 			val |= OTGSC_BSVIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			val &= ~OTGSC_BSVIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	cable = &ci->platdata->id_extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (!IS_ERR(cable->edev) || ci->role_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		if (cable->changed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			val |= OTGSC_IDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			val &= ~OTGSC_IDIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		if (cable->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			val &= ~OTGSC_ID; /* host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			val |= OTGSC_ID; /* device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (cable->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			val |= OTGSC_IDIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			val &= ~OTGSC_IDIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * hw_write_otgsc updates target bits of OTGSC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @data: to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct ci_hdrc_cable *cable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	cable = &ci->platdata->vbus_extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (!IS_ERR(cable->edev) || ci->role_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (data & mask & OTGSC_BSVIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			cable->changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Don't enable vbus interrupt if using external notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		if (data & mask & OTGSC_BSVIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			cable->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			data &= ~OTGSC_BSVIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		} else if (mask & OTGSC_BSVIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			cable->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	cable = &ci->platdata->id_extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (!IS_ERR(cable->edev) || ci->role_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (data & mask & OTGSC_IDIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			cable->changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		/* Don't enable id interrupt if using external notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if (data & mask & OTGSC_IDIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			cable->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			data &= ~OTGSC_IDIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		} else if (mask & OTGSC_IDIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			cable->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * ci_otg_role - pick role based on ID pin state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) enum ci_role ci_otg_role(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		? CI_ROLE_GADGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		: CI_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void ci_handle_vbus_change(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (!ci->is_otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (hw_read_otgsc(ci, OTGSC_BSV) && !ci->vbus_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		usb_gadget_vbus_connect(&ci->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else if (!hw_read_otgsc(ci, OTGSC_BSV) && ci->vbus_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		usb_gadget_vbus_disconnect(&ci->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * When we switch to device mode, the vbus value should be lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * than OTGSC_BSV before connecting to host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * This function returns an error code if timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int hw_wait_vbus_lower_bsv(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned long elapse = jiffies + msecs_to_jiffies(5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 mask = OTGSC_BSV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	while (hw_read_otgsc(ci, mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (time_after(jiffies, elapse)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			dev_err(ci->dev, "timeout waiting for %08x in OTGSC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void ci_handle_id_switch(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	enum ci_role role = ci_otg_role(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (role != ci->role) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_dbg(ci->dev, "switching from %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			ci_role(ci)->name, ci->roles[role]->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		if (ci->vbus_active && ci->role == CI_ROLE_GADGET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			 * vbus disconnect event is lost due to role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			 * switch occurs during system suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			usb_gadget_vbus_disconnect(&ci->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		ci_role_stop(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (role == CI_ROLE_GADGET &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				IS_ERR(ci->platdata->vbus_extcon.edev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			 * Wait vbus lower than OTGSC_BSV before connecting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			 * to host. If connecting status is from an external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			 * connector instead of register, we don't need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			 * care vbus on the board, since it will not affect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			 * external connector status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			hw_wait_vbus_lower_bsv(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		ci_role_start(ci, role);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		/* vbus change may have already occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		if (role == CI_ROLE_GADGET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			ci_handle_vbus_change(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * ci_otg_work - perform otg (vbus/id) event handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * @work: work struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void ci_otg_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		enable_irq(ci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	pm_runtime_get_sync(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ci->id_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		ci->id_event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		ci_handle_id_switch(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ci->b_sess_valid_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		ci->b_sess_valid_event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ci_handle_vbus_change(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	pm_runtime_put_sync(ci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	enable_irq(ci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * ci_hdrc_otg_init - initialize otg struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int ci_hdrc_otg_init(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	INIT_WORK(&ci->work, ci_otg_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ci->wq = create_freezable_workqueue("ci_otg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (!ci->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(ci->dev, "can't create workqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ci_otg_is_fsm_mode(ci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return ci_hdrc_otg_fsm_init(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * ci_hdrc_otg_destroy - destroy otg struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ci->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		flush_workqueue(ci->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		destroy_workqueue(ci->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Disable all OTG irq and clear status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 						OTGSC_INT_STATUS_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (ci_otg_is_fsm_mode(ci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		ci_hdrc_otg_fsm_remove(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }