Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * host.c - ChipIdea USB host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2012 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Alexander Shishkin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/usb/hcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/usb/chipidea.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "../host/ehci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "bits.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "host.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static struct hc_driver __read_mostly ci_ehci_hc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static int (*orig_bus_suspend)(struct usb_hcd *hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct ehci_ci_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct regulator *reg_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct ehci_ci_priv *priv = (struct ehci_ci_priv *)ehci->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct device *dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (priv->reg_vbus && enable != priv->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		if (port > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				"Not support multi-port regulator control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			ret = regulator_enable(priv->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			ret = regulator_disable(priv->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				"Failed to %s vbus regulator, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				enable ? "enable" : "disable", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		priv->enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (enable && (ci->platdata->phy_mode == USBPHY_INTERFACE_MODE_HSIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		 * Marvell 28nm HSIC PHY requires forcing the port to HS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		 * As HSIC is always HS, this should be safe for others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		hw_port_test_set(ci, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		hw_port_test_set(ci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static int ehci_ci_reset(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct device *dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	ret = ehci_setup(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ehci->need_io_watchdog = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (ci->platdata->notify_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		ret = ci->platdata->notify_event(ci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				CI_HDRC_CONTROLLER_RESET_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ci_platform_configure(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct ehci_driver_overrides ehci_ci_overrides = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.extra_priv_size = sizeof(struct ehci_ci_priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.port_power	 = ehci_ci_portpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.reset		 = ehci_ci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static irqreturn_t host_irq(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return usb_hcd_irq(ci->irq, ci->hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int host_start(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct ehci_hcd *ehci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct ehci_ci_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (usb_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	hcd = __usb_create_hcd(&ci_ehci_hc_driver, ci->dev->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			       ci->dev, dev_name(ci->dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (!hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	dev_set_drvdata(ci->dev, ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	hcd->rsrc_start = ci->hw_bank.phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	hcd->rsrc_len = ci->hw_bank.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	hcd->regs = ci->hw_bank.abs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	hcd->has_tt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	hcd->power_budget = ci->platdata->power_budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	hcd->tpl_support = ci->platdata->tpl_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ci->phy || ci->usb_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		hcd->skip_phy_initialization = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (ci->usb_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			hcd->usb_phy = ci->usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ehci->caps = ci->hw_bank.cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ehci->has_hostpc = ci->hw_bank.lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ehci->imx28_write_fix = ci->imx28_write_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	priv = (struct ehci_ci_priv *)ehci->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	priv->reg_vbus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			ret = regulator_enable(ci->platdata->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				dev_err(ci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				"Failed to enable vbus regulator, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 									ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				goto put_hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			priv->reg_vbus = ci->platdata->reg_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ci->platdata->pins_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pinctrl_select_state(ci->platdata->pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				     ci->platdata->pins_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = usb_add_hcd(hcd, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto disable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		struct usb_otg *otg = &ci->otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		ci->hcd = hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (ci_otg_is_fsm_mode(ci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			otg->host = &hcd->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			hcd->self.otg_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (ci->platdata->notify_event &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			(ci->platdata->flags & CI_HDRC_IMX_IS_HSIC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			ci->platdata->notify_event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				(ci, CI_HDRC_IMX_HSIC_ACTIVE_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) disable_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			(ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		regulator_disable(ci->platdata->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) put_hcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void host_stop(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct usb_hcd *hcd = ci->hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (hcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (ci->platdata->notify_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			ci->platdata->notify_event(ci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				CI_HDRC_CONTROLLER_STOPPED_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		usb_remove_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ci->role = CI_ROLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		synchronize_irq(ci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		usb_put_hcd(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			(ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				regulator_disable(ci->platdata->reg_vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ci->hcd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	ci->otg.host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (ci->platdata->pins_host && ci->platdata->pins_default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		pinctrl_select_state(ci->platdata->pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				     ci->platdata->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void ci_hdrc_host_destroy(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ci->role == CI_ROLE_HOST && ci->hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		host_stop(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* The below code is based on tegra ehci driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ci_ehci_hub_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct usb_hcd	*hcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u16		typeReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u16		wValue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	u16		wIndex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	char		*buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u16		wLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned int	ports = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 __iomem	*status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u32		temp, port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned long	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int		retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct device *dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	port_index = wIndex & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	port_index -= (port_index > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	status_reg = &ehci->regs->port_status[port_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	spin_lock_irqsave(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (!wIndex || wIndex > ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			retval = -EPIPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		temp |= PORT_WKDISC_E | PORT_WKOC_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 * If a transaction is in progress, there may be a delay in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 * suspending the port. Poll until the port is suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			PORT_SUSPEND, 5000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			ehci_err(ehci, "timeout waiting for SUSPEND\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			if (ci->platdata->notify_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				ci->platdata->notify_event(ci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 					CI_HDRC_IMX_HSIC_SUSPEND_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			temp = ehci_readl(ehci, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			temp &= ~(PORT_WKDISC_E | PORT_WKCONN_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			ehci_writel(ehci, temp, status_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		set_bit(port_index, &ehci->suspended_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * After resume has finished, it needs do some post resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 * operation for some SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	else if (typeReq == ClearPortFeature &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		wValue == USB_PORT_FEAT_C_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		/* Make sure the resume has finished, it should be finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 25000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			ehci_err(ehci, "timeout waiting for resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* Handle the hub control events here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	spin_unlock_irqrestore(&ehci->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct device *dev = hcd->self.controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct ci_hdrc *ci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int ret = orig_bus_suspend(hcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	port = HCS_N_PORTS(ehci->hcs_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	while (port--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		u32 __iomem *reg = &ehci->regs->port_status[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		u32 portsc = ehci_readl(ehci, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		if (portsc & PORT_CONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			 * For chipidea, the resume signal will be ended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			 * automatically, so for remote wakeup case, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			 * usbcmd.rs may not be set before the resume has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			 * ended if other resume paths consumes too much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			 * time (~24ms), in that case, the SOF will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			 * send out within 3ms after resume ends, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			 * high speed device will enter full speed mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			tmp = ehci_readl(ehci, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			tmp |= CMD_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			ehci_writel(ehci, tmp, &ehci->regs->command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			 * It needs a short delay between set RS bit and PHCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			usleep_range(150, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			 * Need to clear WKCN and WKOC for imx HSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			 * otherwise, there will be wakeup event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				tmp = ehci_readl(ehci, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				tmp &= ~(PORT_WKDISC_E | PORT_WKCONN_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				ehci_writel(ehci, tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ci_hdrc_host_init(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct ci_role_driver *rdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_HC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (!rdrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	rdrv->start	= host_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	rdrv->stop	= host_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	rdrv->irq	= host_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	rdrv->name	= "host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ci->roles[CI_ROLE_HOST] = rdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void ci_hdrc_host_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	ehci_init_driver(&ci_ehci_hc_driver, &ehci_ci_overrides);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ci_ehci_hc_driver.hub_control = ci_ehci_hub_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }