^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ci.h - common structures, functions, and macros of the ChipIdea driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: David Lopo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DRIVERS_USB_CHIPIDEA_CI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/usb/otg-fsm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb/role.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ulpi/interface.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * DEFINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TD_PAGE_COUNT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ENDPT_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Identification Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ID_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ID_HWGENERAL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ID_HWHOST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ID_HWDEVICE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ID_HWTXBUF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ID_HWRXBUF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ID_SBUSCFG 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* register indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum ci_hw_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CAP_CAPLENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CAP_HCCPARAMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CAP_DCCPARAMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CAP_TESTMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CAP_LAST = CAP_TESTMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) OP_USBCMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) OP_USBSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) OP_USBINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) OP_DEVICEADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) OP_ENDPTLISTADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OP_TTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OP_BURSTSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) OP_ULPI_VIEWPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) OP_PORTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OP_DEVLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OP_OTGSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OP_USBMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OP_ENDPTSETUPSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OP_ENDPTPRIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OP_ENDPTFLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OP_ENDPTSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OP_ENDPTCOMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OP_ENDPTCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* endptctrl1..15 follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * STRUCTURES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * struct ci_hw_ep - endpoint representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @ep: endpoint structure for gadget drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @dir: endpoint direction (TX/RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @num: endpoint number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @type: endpoint type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @name: string description of the endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @qh: queue head for this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @wedge: is the endpoint wedged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @ci: pointer to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @lock: pointer to controller's spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @td_pool: pointer to controller's TD pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct ci_hw_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct usb_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ci_hw_qh *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } qh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int wedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* global resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ci_hdrc *ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dma_pool *td_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct td_node *pending_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum ci_role {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CI_ROLE_HOST = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CI_ROLE_GADGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CI_ROLE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum ci_revision {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CI_REVISION_1X = 10, /* Revision 1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CI_REVISION_20 = 20, /* Revision 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CI_REVISION_21, /* Revision 2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CI_REVISION_22, /* Revision 2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CI_REVISION_23, /* Revision 2.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CI_REVISION_24, /* Revision 2.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CI_REVISION_25, /* Revision 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CI_REVISION_25_PLUS, /* Revision above than 2.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * struct ci_role_driver - host/gadget role driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @start: start this role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @stop: stop this role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @irq: irq handler for this role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @name: role name string (host/gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ci_role_driver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int (*start)(struct ci_hdrc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void (*stop)(struct ci_hdrc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irqreturn_t (*irq)(struct ci_hdrc *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * struct hw_bank - hardware register mapping representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @lpm: set if the device is LPM capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @phys: physical address of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @abs: absolute address of the beginning of register window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @cap: capability registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @op: operational registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @size: size of the register window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @regmap: register lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct hw_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) resource_size_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *abs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void __iomem *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *regmap[OP_LAST + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * struct ci_hdrc - chipidea device representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @dev: pointer to parent device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @lock: access synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @hw_bank: hardware register mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @irq: IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @roles: array of supported roles for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @role: current role
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @is_otg: if the device is otg-capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @fsm: otg finite state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @otg_fsm_hrtimer: hrtimer for otg fsm timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @hr_timeouts: time out list for active otg fsm timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @enabled_otg_timer_bits: bits of enabled otg timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @next_otg_timer: next nearest enabled timer to be expired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @work: work for role changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @wq: workqueue thread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @qh_pool: allocation pool for queue heads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @td_pool: allocation pool for transfer descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @gadget: device side representation for peripheral controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @driver: gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @resume_state: save the state of gadget suspend from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @hw_ep_max: total number of endpoints supported by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @ci_hw_ep: array of endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @ep0_dir: ep0 direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @ep0out: pointer to ep0 OUT endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @ep0in: pointer to ep0 IN endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @status: ep0 status request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @setaddr: if we should set the address on status completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @address: usb address received from the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @remote_wakeup: host-enabled remote wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @suspended: suspended by host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @test_mode: the selected test mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @platdata: platform specific information supplied by parent device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @vbus_active: is VBUS active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @ulpi: pointer to ULPI device, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @ulpi_ops: ULPI read/write ops for this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @phy: pointer to PHY, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @hcd: pointer to usb_hcd for ehci host driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @debugfs: root dentry for this controller in debugfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @id_event: indicates there is an id event, and handled at ci_otg_work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @b_sess_valid_event: indicates there is a vbus event, and handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * at ci_otg_work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @supports_runtime_pm: if runtime pm is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @in_lpm: if the core in low power mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @wakeup_int: if wakeup interrupt occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @rev: The revision number for controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct ci_hdrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct hw_bank hw_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ci_role_driver *roles[CI_ROLE_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum ci_role role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool is_otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct usb_otg otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct otg_fsm fsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct hrtimer otg_fsm_hrtimer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned enabled_otg_timer_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enum otg_fsm_timer next_otg_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct usb_role_switch *role_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct workqueue_struct *wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct dma_pool *qh_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct dma_pool *td_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct usb_gadget_driver *driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum usb_device_state resume_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned hw_ep_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 ep0_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct ci_hw_ep *ep0out, *ep0in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct usb_request *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool setaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 remote_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 test_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ci_hdrc_platform_data *platdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int vbus_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ulpi *ulpi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct ulpi_ops ulpi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* old usb_phy interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct usb_phy *usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct usb_hcd *hcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bool id_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool b_sess_valid_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool imx28_write_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool supports_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool in_lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bool wakeup_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) enum ci_revision rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return ci->roles[ci->role];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (role >= CI_ROLE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!ci->roles[role])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = ci->roles[role]->start(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ci->role = role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline void ci_role_stop(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum ci_role role = ci->role;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (role == CI_ROLE_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ci->role = CI_ROLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ci->roles[role]->stop(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ci->role == CI_ROLE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return USB_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else if (ci->role == CI_ROLE_GADGET && ci->vbus_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return USB_ROLE_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return USB_ROLE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline enum ci_role usb_role_to_ci_role(enum usb_role role)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (role == USB_ROLE_HOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return CI_ROLE_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else if (role == USB_ROLE_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return CI_ROLE_GADGET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return CI_ROLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * hw_read_id_reg: reads from a identification register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @offset: offset from the beginning of identification registers region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * This function returns register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ioread32(ci->hw_bank.abs + offset) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * hw_write_id_reg: writes to a identification register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @offset: offset from the beginning of identification registers region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @data: new value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (~mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) | (data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) iowrite32(data, ci->hw_bank.abs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * hw_read: reads from a hw register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @reg: register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * This function returns register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ioread32(ci->hw_bank.regmap[reg]) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_SOC_IMX28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline void __hw_write(struct ci_hdrc *ci, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ci->imx28_write_fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) imx28_ci_writel(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * hw_write: writes to a hw register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @reg: register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @data: new value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (~mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) | (data & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __hw_write(ci, data, ci->hw_bank.regmap[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * hw_test_and_clear: tests & clears a hw register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @reg: register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * This function returns register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) __hw_write(ci, val, ci->hw_bank.regmap[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * hw_test_and_write: tests & writes a hw register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @ci: the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @reg: register index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @mask: bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @data: new value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * This function returns register contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 mask, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 val = hw_read(ci, reg, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) hw_write(ci, reg, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return (val & mask) >> __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * ci_otg_is_fsm_mode: runtime check if otg controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * is in otg fsm mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @ci: chipidea device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #ifdef CONFIG_USB_OTG_FSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) otg_caps->hnp_support || otg_caps->adp_support);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ci_ulpi_init(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) void ci_ulpi_exit(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ci_ulpi_resume(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 hw_read_intr_enable(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 hw_read_intr_status(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int hw_device_reset(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 hw_port_test_get(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void hw_phymode_configure(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void ci_platform_configure(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void dbg_create_files(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void dbg_remove_files(struct ci_hdrc *ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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