^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bits.h - register bits of the ChipIdea USB IP core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: David Lopo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DRIVERS_USB_CHIPIDEA_BITS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/usb/ehci_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * For 1.x revision, bit24 - bit31 are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * For 2.x revision, bit25 - bit28 are 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TAG (0x1F << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REVISION (0xF << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VERSION (0xF << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CIVERSION (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* SBUSCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AHBBRST_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* HCCPARAMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HCCPARAMS_LEN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* DCCPARAMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DCCPARAMS_DEN (0x1F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DCCPARAMS_DC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DCCPARAMS_HC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* TESTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TESTMODE_FORCE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* USBCMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USBCMD_RS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBCMD_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBCMD_SUTW BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USBCMD_ATDTW BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* USBSTS & USBINTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBi_UI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBi_UEI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USBi_PCI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USBi_URI BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USBi_SLI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* DEVICEADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEVICEADDR_USBADRA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DEVICEADDR_USBADR (0x7FUL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* TTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TTCTRL_TTHA_MASK (0x7fUL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Set non-zero value for internal TT Hub address representation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TTCTRL_TTHA (0x7fUL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* BURSTSIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX_BURST_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TX_BURST_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PORTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PORTSC_CCS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PORTSC_CSC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PORTSC_PEC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PORTSC_OCC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PORTSC_FPR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PORTSC_SUSP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PORTSC_HSP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PORTSC_PP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PORTSC_PTC (0x0FUL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PORTSC_WKCN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* PTS and PTW for non lpm version only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PORTSC_PFSC BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PORTSC_PTS(d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PORTSC_PTW BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PORTSC_STS BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PORTSC_W1C_BITS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* DEVLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DEVLC_PFSC BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DEVLC_PSPD (0x03UL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DEVLC_PSPD_HS (0x02UL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DEVLC_PTW BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DEVLC_STS BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DEVLC_PTS(d) (u32)(((d) & 0x7) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Encoding for DEVLC_PTS and PORTSC_PTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PTS_UTMI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PTS_ULPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PTS_SERIAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PTS_HSIC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* OTGSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OTGSC_IDPU BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OTGSC_HADP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OTGSC_HABA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OTGSC_ID BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OTGSC_AVV BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OTGSC_ASV BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OTGSC_BSV BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OTGSC_BSE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OTGSC_IDIS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OTGSC_AVVIS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OTGSC_ASVIS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OTGSC_BSVIS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OTGSC_BSEIS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OTGSC_1MSIS BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OTGSC_DPIS BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OTGSC_IDIE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OTGSC_AVVIE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OTGSC_ASVIE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OTGSC_BSVIE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OTGSC_BSEIE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OTGSC_1MSIE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OTGSC_DPIE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OTGSC_INT_EN_BITS (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | OTGSC_DPIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OTGSC_INT_STATUS_BITS (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) | OTGSC_DPIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* USBMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USBMODE_CM (0x03UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define USBMODE_CM_DC (0x02UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USBMODE_SLOM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USBMODE_CI_SDIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ENDPTCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ENDPTCTRL_RXS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ENDPTCTRL_RXT (0x03UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ENDPTCTRL_RXE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ENDPTCTRL_TXS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ENDPTCTRL_TXT (0x03UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ENDPTCTRL_TXE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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