^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * USBSS device controller driver header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2019 Cadence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Pawel Laszczak <pawell@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Pawel Jez <pjez@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Peter Chen <peter.chen@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __LINUX_CDNS3_GADGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __LINUX_CDNS3_GADGET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * USBSS-DEV register interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This corresponds to the USBSS Device Controller Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * struct cdns3_usb_regs - device controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @usb_conf: Global Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @usb_sts: Global Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @usb_cmd: Global Command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @usb_itpn: ITP/SOF number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @usb_lpm: Global Command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @usb_ien: USB Interrupt Enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @usb_ists: USB Interrupt Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @ep_sel: Endpoint Select.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @ep_traddr: Endpoint Transfer Ring Address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @ep_cfg: Endpoint Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @ep_cmd: Endpoint Command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @ep_sts: Endpoint Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @ep_sts_sid: Endpoint Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @ep_sts_en: Endpoint Status Enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @drbl: Doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @ep_ien: EP Interrupt Enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @ep_ists: EP Interrupt Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @usb_pwr: Global Power Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @usb_conf2: Global Configuration 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @usb_cap1: Capability 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @usb_cap2: Capability 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @usb_cap3: Capability 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @usb_cap4: Capability 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @usb_cap5: Capability 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @usb_cap6: Capability 6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @usb_cpkt1: Custom Packet 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @usb_cpkt2: Custom Packet 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @usb_cpkt3: Custom Packet 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @ep_dma_ext_addr: Upper address for DMA operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @buf_addr: Address for On-chip Buffer operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @buf_data: Data for On-chip Buffer operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @buf_ctrl: On-chip Buffer Access Control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @dtrans: DMA Transfer Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @tdl_from_trb: Source of TD Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @tdl_beh: TDL Behavior Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @ep_tdl: Endpoint TDL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @tdl_beh2: TDL Behavior 2 Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @dma_adv_td: DMA Advance TD Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @reserved1: Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @cfg_regs: Configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @reserved2: Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @dma_axi_ctrl: AXI Control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @dma_axi_id: AXI ID register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @dma_axi_cap: AXI Capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @dma_axi_ctrl0: AXI Control 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @dma_axi_ctrl1: AXI Control 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct cdns3_usb_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __le32 usb_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __le32 usb_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __le32 usb_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le32 usb_itpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __le32 usb_lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 usb_ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __le32 usb_ists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __le32 ep_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __le32 ep_traddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __le32 ep_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __le32 ep_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __le32 ep_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 ep_sts_sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 ep_sts_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __le32 drbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __le32 ep_ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __le32 ep_ists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __le32 usb_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __le32 usb_conf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le32 usb_cap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __le32 usb_cap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __le32 usb_cap3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __le32 usb_cap4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __le32 usb_cap5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __le32 usb_cap6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __le32 usb_cpkt1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __le32 usb_cpkt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __le32 usb_cpkt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le32 ep_dma_ext_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __le32 buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __le32 buf_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __le32 buf_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __le32 dtrans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __le32 tdl_from_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __le32 tdl_beh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __le32 ep_tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __le32 tdl_beh2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __le32 dma_adv_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __le32 reserved1[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __le32 cfg_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __le32 dbg_link1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __le32 dbg_link2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __le32 cfg_regs[74];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __le32 reserved2[51];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __le32 dma_axi_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __le32 dma_axi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __le32 dma_axi_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __le32 dma_axi_ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __le32 dma_axi_ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* USB_CONF - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Reset USB device configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USB_CONF_CFGRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Set Configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define USB_CONF_CFGSET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Disconnect USB device in SuperSpeed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USB_CONF_USB3DIS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Disconnect USB device in HS/FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USB_CONF_USB2DIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Little Endian access - default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USB_CONF_LENDIAN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Big Endian access. Driver assume that byte order for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * SFRs access always is as Little Endian so this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USB_CONF_BENDIAN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Device software reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USB_CONF_SWRST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USB_CONF_DSING BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USB_CONF_DMULT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* DMA clock turn-off enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USB_CONF_DMAOFFEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* DMA clock turn-off disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USB_CONF_DMAOFFDS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Clear Force Full Speed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USB_CONF_CFORCE_FS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Set Force Full Speed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USB_CONF_SFORCE_FS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Device enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USB_CONF_DEVEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Device disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USB_CONF_DEVDS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* L1 LPM state entry enable (used in HS/FS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USB_CONF_L1EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* L1 LPM state entry disable (used in HS/FS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USB_CONF_L1DS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* USB 2.0 clock gate disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USB_CONF_CLK2OFFEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* USB 2.0 clock gate enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USB_CONF_CLK2OFFDS BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* L0 LPM state entry request (used in HS/FS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define USB_CONF_LGO_L0 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* USB 3.0 clock gate disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define USB_CONF_CLK3OFFEN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* USB 3.0 clock gate enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USB_CONF_CLK3OFFDS BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Bit 23 is reserved*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* U1 state entry enable (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USB_CONF_U1EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* U1 state entry disable (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define USB_CONF_U1DS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* U2 state entry enable (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USB_CONF_U2EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* U2 state entry disable (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USB_CONF_U2DS BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* U0 state entry request (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define USB_CONF_LGO_U0 BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* U1 state entry request (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define USB_CONF_LGO_U1 BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* U2 state entry request (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define USB_CONF_LGO_U2 BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* SS.Inactive state entry request (used in SS mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define USB_CONF_LGO_SSINACT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* USB_STS - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Configuration status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * 1 - device is in the configured state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * 0 - device is not configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define USB_STS_CFGSTS_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * On-chip memory overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 0 - On-chip memory status OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 1 - On-chip memory overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define USB_STS_OV_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * SuperSpeed connection status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 0 - USB in SuperSpeed mode disconnected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 1 - USB in SuperSpeed mode connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define USB_STS_USB3CONS_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * DMA transfer configuration status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 0 - single request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * 1 - multiple TRB chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Supported only for controller version < DEV_VER_V3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define USB_STS_DTRANS_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Device speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 0 - Undefined (value after reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 1 - Low speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 2 - Full speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * 3 - High speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 4 - Super speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define USB_STS_USBSPEED_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define USB_STS_LS (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define USB_STS_FS (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define USB_STS_HS (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define USB_STS_SS (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Endianness for SFR access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * 0 - Little Endian order (default after hardware reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * 1 - Big Endian order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define USB_STS_ENDIAN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * HS/FS clock turn-off status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * 0 - hsfs clock is always on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * (default after hardware reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define USB_STS_CLK2OFF_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * PCLK clock turn-off status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * 0 - pclk clock is always on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * 1 - pclk clock turn-off in U3 (SS mode) is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * (default after hardware reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define USB_STS_CLK3OFF_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Controller in reset state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 0 - Internal reset is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * 1 - Internal reset is not active and controller is fully operational.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define USB_STS_IN_RST_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Status of the "TDL calculation basing on TRB" feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * 0 - disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * 1 - enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Supported only for DEV_VER_V2 controller version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define USB_STS_TDL_TRB_ENABLED BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Device enable Status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * 1 - USB device is enabled (VBUS input is connected to the internal logic).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define USB_STS_DEVS_MASK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Address status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 0 - USB device is default state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * 1 - USB device is at least in address state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define USB_STS_ADDRESSED_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * L1 LPM state enable status (used in HS/FS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * 0 - Entering to L1 LPM state disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * 1 - Entering to L1 LPM state enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define USB_STS_L1ENS_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Internal VBUS connection status (used both in HS/FS and SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * 0 - internal VBUS is not detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * 1 - internal VBUS is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define USB_STS_VBUSS_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * HS/FS LPM state (used in FS/HS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * 0 - L0 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * 1 - L1 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * 2 - L2 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * 3 - L3 State
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define USB_STS_LPMST_MASK GENMASK(19, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Disable HS status (used in FS/HS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * 0 - the disconnect bit for HS/FS mode is set .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * 1 - the disconnect bit for HS/FS mode is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define USB_STS_USB2CONS_MASK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * HS/FS mode connection status (used in FS/HS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * 1 - High Speed operations in USB2.0 (FS/HS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define USB_STS_DISABLE_HS_MASK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * U1 state enable status (used in SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * 0 - Entering to U1 state disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 1 - Entering to U1 state enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define USB_STS_U1ENS_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * U2 state enable status (used in SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * 0 - Entering to U2 state disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * 1 - Entering to U2 state enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define USB_STS_U2ENS_MASK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * SuperSpeed link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define USB_STS_LST_MASK GENMASK(29, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * DMA clock turn-off status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * 0 - DMA clock is always on (default after hardware reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define USB_STS_DMAOFF_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * SFR Endian status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 0 - Little Endian order (default after hardware reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 1 - Big Endian order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define USB_STS_ENDIAN2_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* USB_CMD - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Set Function Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define USB_CMD_SET_ADDR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Function Address This field is saved to the device only when the field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * SET_ADDR is set '1 ' during write to USB_CMD register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Software is responsible for entering the address of the device during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * SET_ADDRESS request service. This field should be set immediately after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * the SETUP packet is decoded, and prior to confirmation of the status phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define USB_CMD_FADDR_MASK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Send Function Wake Device Notification TP (used only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define USB_CMD_SDNFW BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Set Test Mode (used only in HS/FS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define USB_CMD_STMODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Test mode selector (used only in HS/FS mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Send Latency Tolerance Message Device Notification TP (used only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * in SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define USB_CMD_SDNLTM BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Send Custom Transaction Packet (used only in SS mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define USB_CMD_SPKT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * (used only in SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* USB_ITPN - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * ITP(SS) / SOF (HS/FS) number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * In SS mode this field represent number of last ITP received from host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * In HS/FS mode this field represent number of last SOF received from host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define USB_ITPN_MASK GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define USB_ITPN(p) ((p) & USB_ITPN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* USB_LPM - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Host Initiated Resume Duration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define USB_LPM_HIRD_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Remote Wakeup Enable (bRemoteWake). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define USB_LPM_BRW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* USB_IEN - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* SS connection interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define USB_IEN_CONIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* SS disconnection interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define USB_IEN_DISIEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* USB SS warm reset interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define USB_IEN_UWRESIEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* USB SS hot reset interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define USB_IEN_UHRESIEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* SS link U3 state enter interrupt enable (suspend).*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define USB_IEN_U3ENTIEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* SS link U3 state exit interrupt enable (wakeup). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define USB_IEN_U3EXTIEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* SS link U2 state enter interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define USB_IEN_U2ENTIEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* SS link U2 state exit interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define USB_IEN_U2EXTIEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* SS link U1 state enter interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define USB_IEN_U1ENTIEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* SS link U1 state exit interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define USB_IEN_U1EXTIEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* ITP/SOF packet detected interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define USB_IEN_ITPIEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Wakeup interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define USB_IEN_WAKEIEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Send Custom Packet interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define USB_IEN_SPKTIEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* HS/FS mode connection interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define USB_IEN_CON2IEN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* HS/FS mode disconnection interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define USB_IEN_DIS2IEN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* USB reset (HS/FS mode) interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define USB_IEN_U2RESIEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* LPM L2 state enter interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define USB_IEN_L2ENTIEN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* LPM L2 state exit interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define USB_IEN_L2EXTIEN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* LPM L1 state enter interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define USB_IEN_L1ENTIEN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* LPM L1 state exit interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define USB_IEN_L1EXTIEN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Configuration reset interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define USB_IEN_CFGRESIEN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Start of the USB SS warm reset interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define USB_IEN_UWRESSIEN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* End of the USB SS warm reset interrupt enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define USB_IEN_UWRESEIEN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* USB_ISTS - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* SS Connection detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define USB_ISTS_CONI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* SS Disconnection detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define USB_ISTS_DISI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* UUSB warm reset detectede. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define USB_ISTS_UWRESI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* USB hot reset detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define USB_ISTS_UHRESI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* U3 link state enter detected (suspend).*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define USB_ISTS_U3ENTI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* U3 link state exit detected (wakeup). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define USB_ISTS_U3EXTI BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* U2 link state enter detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define USB_ISTS_U2ENTI BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* U2 link state exit detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define USB_ISTS_U2EXTI BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* U1 link state enter detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define USB_ISTS_U1ENTI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* U1 link state exit detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define USB_ISTS_U1EXTI BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* ITP/SOF packet detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define USB_ISTS_ITPI BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Wakeup detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define USB_ISTS_WAKEI BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Send Custom Packet detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define USB_ISTS_SPKTI BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* HS/FS mode connection detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define USB_ISTS_CON2I BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* HS/FS mode disconnection detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define USB_ISTS_DIS2I BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* USB reset (HS/FS mode) detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define USB_ISTS_U2RESI BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* LPM L2 state enter detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define USB_ISTS_L2ENTI BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* LPM L2 state exit detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define USB_ISTS_L2EXTI BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* LPM L1 state enter detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define USB_ISTS_L1ENTI BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* LPM L1 state exit detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define USB_ISTS_L1EXTI BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* USB configuration reset detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define USB_ISTS_CFGRESI BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Start of the USB warm reset detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define USB_ISTS_UWRESSI BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* End of the USB warm reset detected.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define USB_ISTS_UWRESEI BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* USB_SEL - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define EP_SEL_EPNO_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Endpoint number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Endpoint direction bit - 0 - OUT, 1 - IN. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define EP_SEL_DIR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define select_ep_out (EP_SEL_EPNO(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* EP_TRADDR - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Transfer Ring address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define EP_TRADDR_TRADDR(p) ((p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* EP_CFG - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Endpoint enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define EP_CFG_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Endpoint type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * 1 - isochronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * 2 - bulk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * 3 - interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Stream support enable (only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define EP_CFG_STREAM_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* TDL check (only in SS mode for BULK EP). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define EP_CFG_TDL_CHK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* SID check (only in SS mode for BULK OUT EP). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define EP_CFG_SID_CHK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* DMA transfer endianness. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define EP_CFG_EPENDIAN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Max burst size (used only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* ISO max burst. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define EP_CFG_MULT_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* ISO max burst. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Max number of buffered packets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* EP_CMD - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Endpoint reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define EP_CMD_EPRST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Endpoint STALL set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define EP_CMD_SSTALL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Endpoint STALL clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define EP_CMD_CSTALL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Send ERDY TP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define EP_CMD_ERDY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Request complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define EP_CMD_REQ_CMPL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Transfer descriptor ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define EP_CMD_DRDY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Data flush. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define EP_CMD_DFLUSH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Transfer Descriptor Length write (used only for Bulk Stream capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * endpoints in SS mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Bit Removed from DEV_VER_V3 controller version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define EP_CMD_STDL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * Bits Removed from DEV_VER_V3 controller version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define EP_CMD_TDL_MASK GENMASK(15, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define EP_CMD_TDL_MAX (EP_CMD_TDL_MASK >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* ERDY Stream ID value (used in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* EP_STS - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Setup transfer complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define EP_STS_SETUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Endpoint STALL status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define EP_STS_STALL(p) ((p) & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Interrupt On Complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define EP_STS_IOC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Interrupt on Short Packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define EP_STS_ISP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Transfer descriptor missing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define EP_STS_DESCMIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Stream Rejected (used only in SS mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define EP_STS_STREAMR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define EP_STS_MD_EXIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* TRB error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define EP_STS_TRBERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Not ready (used only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define EP_STS_NRDY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* DMA busy bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define EP_STS_DBUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Endpoint Buffer Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Current Cycle Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define EP_STS_CCS(p) ((p) & BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Prime (used only in SS mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define EP_STS_PRIME BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Stream error (used only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define EP_STS_SIDERR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* OUT size mismatch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define EP_STS_OUTSMM BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* ISO transmission error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define EP_STS_ISOERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Host Packet Pending (only for SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define EP_STS_HOSTPP(p) ((p) & BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define EP_STS_SPSMST_MASK GENMASK(18, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Interrupt On Transfer complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define EP_STS_IOT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* OUT queue endpoint number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* OUT queue valid flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define EP_STS_OUTQ_VAL_MASK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* SETUP WAIT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define EP_STS_STPWAIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* EP_STS_SID - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Stream ID (used only in SS mode). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define EP_STS_SID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* EP_STS_EN - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* SETUP interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define EP_STS_EN_SETUPEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* OUT transfer missing descriptor enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define EP_STS_EN_DESCMISEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Stream Rejected enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define EP_STS_EN_STREAMREN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Move Data Exit enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define EP_STS_EN_MD_EXITEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* TRB enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define EP_STS_EN_TRBERREN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* NRDY enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define EP_STS_EN_NRDYEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Prime enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define EP_STS_EN_PRIMEEEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Stream error enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define EP_STS_EN_SIDERREN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* OUT size mismatch enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define EP_STS_EN_OUTSMMEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* ISO transmission error enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define EP_STS_EN_ISOERREN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Interrupt on Transmission complete enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define EP_STS_EN_IOTEN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Setup Wait interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define EP_STS_EN_STPWAITEN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* DRBL- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define DB_VALUE_BY_INDEX(index) (1 << (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define DB_VALUE_EP0_OUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define DB_VALUE_EP0_IN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* EP_IEN - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define EP_IEN(index) (1 << (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define EP_IEN_EP_OUT0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define EP_IEN_EP_IN0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* EP_ISTS - bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define EP_ISTS(index) (1 << (index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define EP_ISTS_EP_OUT0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define EP_ISTS_EP_IN0 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* USB_PWR- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*Power Shut Off capability enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define PUSB_PWR_PSO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*Power Shut Off capability disable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PUSB_PWR_PSO_DS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Enables turning-off Reference Clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * This bit is optional and implemented only when support for OTG is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * implemented (indicated by OTG_READY bit set to '1').
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * is completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* This bit informs if Fast Registers Access is enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Fast Registers Access Enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define PUSB_PWR_FST_REG_ACCESS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* USB_CONF2- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Writing 1 disables TDL calculation basing on TRB feature in controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * for DMULT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * Bit supported only for DEV_VER_V2 version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define USB_CONF2_DIS_TDL_TRB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Writing 1 enables TDL calculation basing on TRB feature in controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * for DMULT mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Bit supported only for DEV_VER_V2 version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define USB_CONF2_EN_TDL_TRB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* USB_CAP1- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * SFR Interface type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * These field reflects type of SFR interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * 0x0 - OCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * 0x1 - AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * 0x2 - PLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * 0x3 - AXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * 0x4-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * SFR Interface width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * These field reflects width of SFR interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * 0x0 - 8 bit interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * 0x1 - 16 bit interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * 0x2 - 32 bit interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * 0x3 - 64 bit interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * 0x4-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * DMA Interface type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * These field reflects type of DMA interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * 0x0 - OCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * 0x1 - AHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * 0x2 - PLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * 0x3 - AXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * 0x4-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * DMA Interface width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * These field reflects width of DMA interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * 0x0 - reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * 0x1 - reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * 0x2 - 32 bit interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * 0x3 - 64 bit interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * 0x4-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * USB3 PHY Interface type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * These field reflects type of USB3 PHY interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * 0x0 - USB PIPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * 0x1 - RMMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * 0x2-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * USB3 PHY Interface width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * These field reflects width of USB3 PHY interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * 0x0 - 8 bit PIPE interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * 0x1 - 16 bit PIPE interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * 0x2 - 32 bit PIPE interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * 0x3 - 64 bit PIPE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * 0x4-0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Note: When SSIC interface is implemented this field shows the width of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * internal PIPE interface. The RMMI interface is always 20bit wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define DEV_U3PHY_WIDTH_8(p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define DEV_U3PHY_WIDTH_16(p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DEV_U3PHY_WIDTH_32(p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define DEV_U3PHY_WIDTH_64(p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * USB2 PHY Interface enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * These field informs if USB2 PHY interface is implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * 0x0 - interface NOT implemented,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * 0x1 - interface implemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * USB2 PHY Interface type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * These field reflects type of USB2 PHY interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * 0x0 - UTMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * 0x1 - ULPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * USB2 PHY Interface width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * These field reflects width of USB2 PHY interface implemented:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * 0x0 - 8 bit interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * 0x1 - 16 bit interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Note: The ULPI interface is always 8bit wide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * OTG Ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * 0x0 - pure device mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * When set, indicates that controller supports automatic internal TDL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * Supported only for DEV_VER_V2 controller version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* USB_CAP2- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * The actual size of the connected On-chip RAM memory in kB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * - 0 means 256 kB (max supported mem size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * - value other than 0 reflects the mem size in kB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Max supported mem size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * These field reflects width of on-chip RAM address bus width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * which determines max supported mem size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * 0x0-0x7 - reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * 0x8 - support for 4kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * 0x9 - support for 8kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * 0xA - support for 16kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * 0xB - support for 32kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * 0xC - support for 64kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * 0xD - support for 128kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * 0xE - support for 256kB mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * 0xF - reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* USB_CAP3- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* USB_CAP4- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* USB_CAP5- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* USB_CAP6- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* The USBSS-DEV Controller Internal build number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* The USBSS-DEV Controller version number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define DEV_VER_NXP_V1 0x00024502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DEV_VER_TI_V1 0x00024509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define DEV_VER_V2 0x0002450C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define DEV_VER_V3 0x0002450d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* DBG_LINK1- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * time required for decoding the received LFPS as an LFPS.U1_Exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * phytxelecidle deassertion when LFPS.U1_Exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Receiver termination detection sequence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * 0: it is possible that USBSS_DEV will terminate Farend receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * termination detection sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * 1: USBSS_DEV will not terminate Far-end receiver termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * detection sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * cleared. Writing '0' has no effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * cleared. Writing '0' has no effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * the RXDET_BREAK_DIS field value to the device. This bit is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * cleared. Writing '0' has no effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * the LFPS_GEN_PING field value to the device. This bit is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * cleared. Writing '0' has no effect."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* DMA_AXI_CTRL- bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* The mawprot pin configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* The marprot pin configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define DMA_AXI_CTRL_NON_SECURE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * USBSS-DEV DMA interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define TRBS_PER_SEGMENT 600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define ISO_MAX_INTERVAL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define MAX_TRB_LENGTH BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #if TRBS_PER_SEGMENT < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define TRBS_PER_STREAM_SEGMENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #if TRBS_PER_STREAM_SEGMENT < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *Only for ISOC endpoints - maximum number of TRBs is calculated as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * pow(2, bInterval-1) * number of usb requests. It is limitation made by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * driver to save memory. Controller must prepare TRB for each ITP even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * if bInterval > 1. It's the reason why driver needs so many TRBs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * isochronous endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * struct cdns3_trb - represent Transfer Descriptor block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * @buffer: pointer to buffer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * @length: length of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * @control: control flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * This structure describes transfer block serviced by DMA module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct cdns3_trb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) __le32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) __le32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define TRB_SIZE (sizeof(struct cdns3_trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define TRB_STREAM_RING_SIZE (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* TRB bit mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define TRB_TYPE_BITMASK GENMASK(15, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define TRB_TYPE(p) ((p) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* TRB type IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* bulk, interrupt, isoc , and control data stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define TRB_NORMAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* TRB for linking ring segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define TRB_LINK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Cycle bit - indicates TRB ownership by driver or hw*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define TRB_CYCLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * When set to '1', the device will toggle its interpretation of the Cycle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define TRB_TOGGLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * The controller will set it if OUTSMM (OUT size mismatch) is detected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * this bit is for normal TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define TRB_SMM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * processed while USB short packet was received. No more buffers defined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * the TD will be used. DMA will automatically advance to next TD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * - Shall be set to 1 by Controller when Short Packet condition for this TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * is detected independent if ISP is set or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define TRB_SP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* Interrupt on short packet*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define TRB_ISP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /*Setting this bit enables FIFO DMA operation mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define TRB_FIFO_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Set PCIe no snoop attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define TRB_CHAIN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define TRB_IOC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* stream ID bitmasks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define TRB_STREAM_ID(p) ((p) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Size of TD expressed in USB packets for HS/FS mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* transfer_len bitmasks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define TRB_LEN(p) ((p) & GENMASK(16, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Size of TD expressed in USB packets for SS mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* transfer_len bitmasks - bits 31:24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Data buffer pointer bitmasks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Driver numeric constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* Such declaration should be added to ch9.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define USB_DEVICE_MAX_ADDRESS 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Endpoint init values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define CDNS3_EP_MAX_PACKET_LIMIT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define CDNS3_EP_MAX_STREAMS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define CDNS3_EP0_MAX_PACKET_LIMIT 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* All endpoints including EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define CDNS3_ENDPOINTS_MAX_COUNT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define CDNS3_EP_ZLP_BUF_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define CDNS3_EP_BUF_SIZE 4 /* KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define CDNS3_EP_ISO_HS_MULT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define CDNS3_EP_ISO_SS_BURST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define CDNS3_MAX_NUM_DESCMISS_BUF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define CDNS3_WA2_NUM_BUFFERS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Used structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct cdns3_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * struct cdns3_endpoint - extended device side representation of USB endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * @endpoint: usb endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * @pending_req_list: list of requests queuing on transfer ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * @deferred_req_list: list of requests waiting for queuing on transfer ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * @wa2_descmiss_req_list: list of requests internally allocated by driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * @trb_pool: transfer ring - array of transaction buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * @trb_pool_dma: dma address of transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * @cdns3_dev: device associated with this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * @name: a human readable name e.g. ep1out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * @flags: specify the current state of endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * @descmis_req: internal transfer object used for getting data from on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * buffer. It can happen only if function driver doesn't send usb_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * object on time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * @dir: endpoint direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * @num: endpoint number (1 - 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * @interval: interval between packets used for ISOC endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * @free_trbs: number of free TRBs in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * @num_trbs: number of all TRBs in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * @alloc_ring_size: size of the allocated TRB ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * @pcs: producer cycle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * @ccs: consumer cycle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * @enqueue: enqueue index in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * @dequeue: dequeue index in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * @trb_burst_size: number of burst used in trb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct cdns3_endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct usb_ep endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct list_head pending_req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct list_head deferred_req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct list_head wa2_descmiss_req_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int wa2_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct cdns3_trb *trb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_addr_t trb_pool_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct cdns3_device *cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define EP_ENABLED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define EP_STALLED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define EP_STALL_PENDING BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define EP_WEDGE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define EP_TRANSFER_STARTED BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define EP_UPDATE_EP_TRBADDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define EP_PENDING_REQUEST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define EP_RING_FULL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define EP_CLAIMED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define EP_DEFERRED_DRDY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define EP_QUIRK_ISO_OUT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define EP_QUIRK_END_TRANSFER BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define EP_QUIRK_EXTRA_BUF_DET BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define EP_QUIRK_EXTRA_BUF_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define EP_TDLCHK_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define EP_CONFIGURED BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct cdns3_request *descmis_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u8 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u8 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) int free_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int alloc_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u8 pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u8 ccs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u8 trb_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) unsigned int wa1_set:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct cdns3_trb *wa1_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) unsigned int wa1_trb_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) unsigned int wa1_cycle_bit:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Stream related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned int use_streams:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned int prime_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) u32 ep_sts_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u16 last_stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) u16 pending_tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) unsigned int stream_sg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * @buf: aligned to 8 bytes data buffer. Buffer address used in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * TRB shall be aligned to 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * @dma: dma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * @size: size of buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * @in_use: inform if this buffer is associated with usb_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * @list: used to adding instance of this object to list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct cdns3_aligned_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) unsigned in_use:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * struct cdns3_request - extended device side representation of usb_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * object .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * @request: generic usb_request object describing single I/O request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * @priv_ep: extended representation of usb_ep object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * @trb: the first TRB association with this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * @start_trb: number of the first TRB in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * @end_trb: number of the last TRB in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * @aligned_buf: object holds information about aligned buffer associated whit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * @flags: flag specifying special usage of request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * @list: used by internally allocated request to add to wa2_descmiss_req_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * @finished_trb: number of trb has already finished per request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * @num_of_trb: how many trbs in this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct cdns3_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct usb_request request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct cdns3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int end_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct cdns3_aligned_buf *aligned_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define REQUEST_PENDING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define REQUEST_INTERNAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define REQUEST_INTERNAL_CH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define REQUEST_ZLP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define REQUEST_UNALIGNED BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int finished_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int num_of_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /*Stages used during enumeration process.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define CDNS3_SETUP_STAGE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define CDNS3_DATA_STAGE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define CDNS3_STATUS_STAGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * struct cdns3_device - represent USB device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * @dev: pointer to device structure associated whit this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * @sysdev: pointer to the DMA capable device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * @gadget: device side representation of the peripheral controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * @gadget_driver: pointer to the gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * @dev_ver: device controller version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * @lock: for synchronizing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * @regs: base address for device side registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * @setup_buf: used while processing usb control requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * @setup_dma: dma address for setup_buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * @zlp_buf - zlp buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * @ep0_stage: ep0 stage during enumeration process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * @ep0_data_dir: direction for control transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * @eps: array of pointers to all endpoints with exclusion ep0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * @aligned_buf_list: list of aligned buffers internally allocated by driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * @aligned_buf_wq: workqueue freeing no longer used aligned buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * @selected_ep: actually selected endpoint. It's used only to improve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * @u1_allowed: allow device transition to u1 state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * @u2_allowed: allow device transition to u2 state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * @is_selfpowered: device is self powered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * @setup_pending: setup packet is processing by gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * @hw_configured_flag: hardware endpoint configuration was set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * @wake_up_flag: allow device to remote up the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * @status_completion_no_call: indicate that driver is waiting for status s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * stage completion. It's used in deferred SET_CONFIGURATION request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * @onchip_buffers: number of available on-chip buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * @pending_status_wq: workqueue handling status stage for deferred requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * @pending_status_request: request for which status stage was deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct cdns3_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct device *sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct usb_gadget gadget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct usb_gadget_driver *gadget_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define CDNS_REVISION_V0 0x00024501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define CDNS_REVISION_V1 0x00024509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 dev_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* generic spin-lock for drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct cdns3_usb_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct usb_ctrlrequest *setup_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dma_addr_t setup_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) void *zlp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) u8 ep0_stage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int ep0_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct list_head aligned_buf_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct work_struct aligned_buf_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) u32 selected_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u16 isoch_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) unsigned wait_for_setup:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) unsigned u1_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) unsigned u2_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) unsigned is_selfpowered:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) unsigned setup_pending:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) unsigned hw_configured_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) unsigned wake_up_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned status_completion_no_call:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) unsigned using_streams:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) int out_mem_is_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct work_struct pending_status_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct usb_request *pending_status_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /*in KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) u16 onchip_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) u16 onchip_used_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct cdns3_trb *trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) void cdns3_pending_setup_status_handler(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct usb_request *cdns3_next_request(struct list_head *list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u8 cdns3_ep_addr_to_index(u8 ep_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) void cdns3_gadget_ep_free_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct usb_request *request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct cdns3_request *priv_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int cdns3_init_ep0(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct cdns3_endpoint *priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) void cdns3_ep0_config(struct cdns3_device *priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #endif /* __LINUX_CDNS3_GADGET */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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