^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence USBSS DRD Driver - gadget side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2019 Cadence Design Systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors: Pawel Jez <pjez@cadence.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Pawel Laszczak <pawell@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Peter Chen <peter.chen@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Work around 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * At some situations, the controller may get stale data address in TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * at below sequences:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 1. Controller read TRB includes data address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 2. Software updates TRBs includes data address and Cycle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 3. Controller read TRB which includes Cycle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 4. DMA run with stale data address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * To fix this problem, driver needs to make the first TRB in TD as invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * After preparing all TRBs driver needs to check the position of DMA and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * if the DMA point to the first just added TRB and doorbell is 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * then driver must defer making this TRB as valid. This TRB will be make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * as valid during adding next TRB only if DMA is stopped or at TRBERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Issue has been fixed in DEV_VER_V3 version of controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Work around 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Controller for OUT endpoints has shared on-chip buffers for all incoming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * in correct order. If the first packet in the buffer will not be handled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * then the following packets directed for other endpoints and functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * will be blocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Additionally the packets directed to one endpoint can block entire on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * buffers. In this case transfer to other endpoints also will blocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * To resolve this issue after raising the descriptor missing interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * driver prepares internal usb_request object and use it to arm DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The problematic situation was observed in case when endpoint has been enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * but no usb_request were queued. Driver try detects such endpoints and will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * use this workaround only for these endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Driver use limited number of buffer. This number can be set by macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * CDNS3_WA2_NUM_BUFFERS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Such blocking situation was observed on ACM gadget. For this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * host send OUT data packet but ACM function is not prepared for this packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * It's cause that buffer placed in on chip memory block transfer to other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * endpoints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Issue has been fixed in DEV_VER_V2 version of controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/usb/gadget.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "gadget-export.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include "gadget.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "drd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct usb_request *request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int cdns3_ep_run_stream_transfer(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct usb_request *request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * cdns3_clear_register_bit - clear bit in given register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @ptr: address of device controller register to be read and changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @mask: bits requested to clar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void cdns3_clear_register_bit(void __iomem *ptr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mask = readl(ptr) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(mask, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * cdns3_set_register_bit - set bit in given register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @ptr: address of device controller register to be read and changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @mask: bits requested to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void cdns3_set_register_bit(void __iomem *ptr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mask = readl(ptr) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(mask, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * cdns3_ep_addr_to_index - Macro converts endpoint address to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * index of endpoint object in cdns3_device.eps[] container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @ep_addr: endpoint address for which endpoint object is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 cdns3_ep_addr_to_index(u8 ep_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int cdns3_get_dma_pos(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int dma_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return dma_index / TRB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * cdns3_next_request - returns next request from list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @list: list containing requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Returns request or NULL if no requests in list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct usb_request *cdns3_next_request(struct list_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return list_first_entry_or_null(list, struct usb_request, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * cdns3_next_align_buf - returns next buffer from list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @list: list containing buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Returns buffer or NULL if no buffers in list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return list_first_entry_or_null(list, struct cdns3_aligned_buf, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * cdns3_next_priv_request - returns next request from list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @list: list containing requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Returns request or NULL if no requests in list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct cdns3_request *cdns3_next_priv_request(struct list_head *list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return list_first_entry_or_null(list, struct cdns3_request, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * select_ep - selects endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @ep: endpoint address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (priv_dev->selected_ep == ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) priv_dev->selected_ep = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(ep, &priv_dev->regs->ep_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * cdns3_get_tdl - gets current tdl for selected endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Before calling this function the appropriate endpoint must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * be selected by means of cdns3_select_ep function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int cdns3_get_tdl(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (priv_dev->dev_ver < DEV_VER_V3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return readl(&priv_dev->regs->ep_tdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct cdns3_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return priv_ep->trb_pool_dma + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int cdns3_ring_size(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) switch (priv_ep->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case USB_ENDPOINT_XFER_ISOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return TRB_ISO_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case USB_ENDPOINT_XFER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return TRB_CTRL_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (priv_ep->use_streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return TRB_STREAM_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return TRB_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (priv_ep->trb_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dma_free_coherent(priv_dev->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cdns3_ring_size(priv_ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) priv_ep->trb_pool, priv_ep->trb_pool_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) priv_ep->trb_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @priv_ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Function will return 0 on success or -ENOMEM on allocation error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ring_size = cdns3_ring_size(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int num_trbs = ring_size / TRB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct cdns3_trb *link_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (priv_ep->trb_pool && priv_ep->alloc_ring_size < ring_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cdns3_free_trb_pool(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!priv_ep->trb_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv_ep->trb_pool = dma_alloc_coherent(priv_dev->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &priv_ep->trb_pool_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GFP_DMA32 | GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!priv_ep->trb_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) priv_ep->alloc_ring_size = ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) memset(priv_ep->trb_pool, 0, ring_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) priv_ep->num_trbs = num_trbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!priv_ep->num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Initialize the last TRB as Link TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * For stream capable endpoints driver use single correct TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * The last trb has zeroed cycle bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) link_trb->control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) link_trb->buffer = cpu_to_le32(TRB_BUFFER(priv_ep->trb_pool_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) link_trb->control = cpu_to_le32(TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * cdns3_ep_stall_flush - Stalls and flushes selected endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @priv_ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Endpoint must be selected before call to this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) trace_cdns3_halt(priv_ep, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* wait for DFLUSH cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) !(val & EP_CMD_DFLUSH), 1, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) priv_ep->flags |= EP_STALLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) priv_ep->flags &= ~EP_STALL_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cdns3_allow_enable_l1(priv_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) priv_dev->hw_configured_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) priv_dev->onchip_used_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) priv_dev->out_mem_is_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) priv_dev->wait_for_setup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv_dev->using_streams = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (priv_dev->eps[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) priv_dev->eps[i]->flags &= ~EP_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * cdns3_ep_inc_trb - increment a trb index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @index: Pointer to the TRB index to increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @cs: Cycle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @trb_in_seg: number of TRBs in segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * The index should never point to the link TRB. After incrementing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * if it is point to the link TRB, wrap around to the beginning and revert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * cycle state bit The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * link TRB is always at the last TRB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (*index)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (*index == (trb_in_seg - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *cs ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * cdns3_ep_inc_enq - increment endpoint's enqueue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @priv_ep: The endpoint whose enqueue pointer we're incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) priv_ep->free_trbs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * cdns3_ep_inc_deq - increment endpoint's dequeue pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @priv_ep: The endpoint whose dequeue pointer we're incrementing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) priv_ep->free_trbs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int current_trb = priv_req->start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) while (current_trb != priv_req->end_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cdns3_ep_inc_deq(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) current_trb = priv_ep->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cdns3_ep_inc_deq(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * cdns3_allow_enable_l1 - enable/disable permits to transition to L1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * @priv_dev: Extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @enable: Enable/disable permit to transition to L1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * If bit USB_CONF_L1EN is set and device receive Extended Token packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * then controller answer with ACK handshake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * If bit USB_CONF_L1DS is set and device receive Extended Token packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * then controller answer with NYET handshake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reg = readl(&priv_dev->regs->usb_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (DEV_SUPERSPEED(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) else if (DEV_HIGHSPEED(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return USB_SPEED_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else if (DEV_FULLSPEED(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return USB_SPEED_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else if (DEV_LOWSPEED(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return USB_SPEED_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * cdns3_start_all_request - add to ring all request not started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @priv_dev: Extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @priv_ep: The endpoint for whom request will be started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Returns return ENOMEM if transfer ring i not enough TRBs to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * all requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int cdns3_start_all_request(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct usb_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 pending_empty = list_empty(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * If the last pending transfer is INTERNAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * OR streams are enabled for this endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * do NOT start new transfer till the last one is pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!pending_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) request = cdns3_next_request(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((priv_req->flags & REQUEST_INTERNAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (priv_ep->flags & EP_TDLCHK_EN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(priv_dev->dev, "Blocking external request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) while (!list_empty(&priv_ep->deferred_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) request = cdns3_next_request(&priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = cdns3_ep_run_transfer(priv_ep, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) priv_ep->stream_sg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = cdns3_ep_run_stream_transfer(priv_ep, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) list_del(&request->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) list_add_tail(&request->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (request->stream_id != 0 || (priv_ep->flags & EP_TDLCHK_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) priv_ep->flags &= ~EP_RING_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * driver try to detect whether endpoint need additional internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * buffer for unblocking on-chip FIFO buffer. This flag will be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * if before first DESCMISS interrupt the DMA will be armed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define cdns3_wa2_enable_detection(priv_dev, priv_ep, reg) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) (reg) |= EP_STS_EN_DESCMISEN; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void __cdns3_descmiss_copy_data(struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct usb_request *descmiss_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int length = request->actual + descmiss_req->actual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct scatterlist *s = request->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (length <= request->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) memcpy(&((u8 *)request->buf)[request->actual],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) descmiss_req->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) descmiss_req->actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) request->actual = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* It should never occures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) request->status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (length <= sg_dma_len(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) void *p = phys_to_virt(sg_dma_address(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) memcpy(&((u8 *)p)[request->actual],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) descmiss_req->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) descmiss_req->actual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) request->actual = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) request->status = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * cdns3_wa2_descmiss_copy_data copy data from internal requests to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * request queued by class driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @priv_ep: extended endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @request: request object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct usb_request *descmiss_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct cdns3_request *descmiss_priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int chunk_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) descmiss_priv_req =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) descmiss_req = &descmiss_priv_req->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* driver can't touch pending request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (descmiss_priv_req->flags & REQUEST_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) request->status = descmiss_req->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) __cdns3_descmiss_copy_data(request, descmiss_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) list_del_init(&descmiss_priv_req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) kfree(descmiss_req->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) --priv_ep->wa2_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!chunk_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct cdns3_request *priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) priv_req->flags & REQUEST_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct usb_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) req = cdns3_next_request(&priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) priv_ep->descmis_req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* unmap the gadget request before copying data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) usb_gadget_unmap_request_by_dev(priv_dev->sysdev, req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) priv_ep->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cdns3_wa2_descmiss_copy_data(priv_ep, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) req->length != req->actual) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* wait for next part of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* re-map the gadget request buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) usb_gadget_map_request_by_dev(priv_dev->sysdev, req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) usb_endpoint_dir_in(priv_ep->endpoint.desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (req->status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) req->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) list_del_init(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return &priv_req->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct cdns3_request *priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int deferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * If transfer was queued before DESCMISS appear than we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * can disable handling of DESCMISS interrupt. Driver assumes that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * can disable special treatment for this endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) reg = readl(&priv_dev->regs->ep_sts_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg &= ~EP_STS_EN_DESCMISEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) trace_cdns3_wa2(priv_ep, "workaround disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) writel(reg, &priv_dev->regs->ep_sts_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 pending_empty = list_empty(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * DESCMISS transfer has been finished, so data will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * directly copied from internal allocated usb_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (pending_empty && !descmiss_empty &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) !(priv_req->flags & REQUEST_INTERNAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cdns3_wa2_descmiss_copy_data(priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &priv_req->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) trace_cdns3_wa2(priv_ep, "get internal stored data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) list_add_tail(&priv_req->request.list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cdns3_gadget_giveback(priv_ep, priv_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) priv_req->request.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Intentionally driver returns positive value as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * correct value. It informs that transfer has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * been finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Driver will wait for completion DESCMISS transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * before starts new, not DESCMISS transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!pending_empty && !descmiss_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) trace_cdns3_wa2(priv_ep, "wait for pending transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) deferred = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (priv_req->flags & REQUEST_INTERNAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) list_add_tail(&priv_req->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u8 chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) chain = !!(priv_req->flags & REQUEST_INTERNAL_CH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) trace_cdns3_wa2(priv_ep, "removes eldest request");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) kfree(priv_req->request.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cdns3_gadget_ep_free_request(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) &priv_req->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) list_del_init(&priv_req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) --priv_ep->wa2_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * cdns3_wa2_descmissing_packet - handles descriptor missing event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @priv_ep: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * This function is used only for WA2. For more information see Work around 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct usb_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u8 pending_empty = list_empty(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* check for pending transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!pending_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) trace_cdns3_wa2(priv_ep, "Ignoring Descriptor missing IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) trace_cdns3_wa2(priv_ep, "Description Missing detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) trace_cdns3_wa2(priv_ep, "WA2 overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) cdns3_wa2_remove_old_request(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) priv_req->flags |= REQUEST_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* if this field is still assigned it indicate that transfer related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * with this request has not been finished yet. Driver in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * case simply allocate next request and assign flag REQUEST_INTERNAL_CH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * flag to previous one. It will indicate that current request is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * part of the previous one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (priv_ep->descmis_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) priv_ep->wa2_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!priv_req->request.buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) priv_ep->descmis_req = priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __cdns3_gadget_ep_queue(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) &priv_ep->descmis_req->request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(priv_ep->cdns3_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "Failed: No sufficient memory for DESCMIS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void cdns3_wa2_reset_tdl(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u16 tdl = EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (tdl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u16 reset_val = EP_CMD_TDL_MAX + 1 - tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void cdns3_wa2_check_outq_status(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 ep_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* select EP0-out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) cdns3_select_ep(priv_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ep_sts_reg = readl(&priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (EP_STS_OUTQ_VAL(ep_sts_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 outq_ep_num = EP_STS_OUTQ_NO(ep_sts_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct cdns3_endpoint *outq_ep = priv_dev->eps[outq_ep_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if ((outq_ep->flags & EP_ENABLED) && !(outq_ep->use_streams) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) outq_ep->type != USB_ENDPOINT_XFER_ISOC && outq_ep_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u8 pending_empty = list_empty(&outq_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if ((outq_ep->flags & EP_QUIRK_EXTRA_BUF_DET) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) (outq_ep->flags & EP_QUIRK_EXTRA_BUF_EN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) !pending_empty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 ep_sts_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 ep_cmd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) cdns3_select_ep(priv_dev, outq_ep->num |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) outq_ep->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ep_sts_en_reg = readl(&priv_dev->regs->ep_sts_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ep_cmd_reg = readl(&priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) outq_ep->flags |= EP_TDLCHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) EP_CFG_TDL_CHK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) cdns3_wa2_enable_detection(priv_dev, outq_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ep_sts_en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) writel(ep_sts_en_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) &priv_dev->regs->ep_sts_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* reset tdl value to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cdns3_wa2_reset_tdl(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * Memory barrier - Reset tdl before ringing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (EP_CMD_DRDY & ep_cmd_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) trace_cdns3_wa2(outq_ep, "Enabling WA2 skipping doorbell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) trace_cdns3_wa2(outq_ep, "Enabling WA2 ringing doorbell\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * ring doorbell to generate DESCMIS irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) writel(EP_CMD_DRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * cdns3_gadget_giveback - call struct usb_request's ->complete callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * @priv_ep: The endpoint to whom the request belongs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * @priv_req: The request we're giving back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * @status: completion code for the request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * Must be called with controller's lock held and interrupts disabled. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * function will unmap @req and call its ->complete() callback to notify upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * layers that it has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct cdns3_request *priv_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct usb_request *request = &priv_req->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) list_del_init(&request->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (request->status == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) request->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) usb_gadget_unmap_request_by_dev(priv_dev->sysdev, request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) priv_ep->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if ((priv_req->flags & REQUEST_UNALIGNED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) priv_ep->dir == USB_DIR_OUT && !request->status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) memcpy(request->buf, priv_req->aligned_buf->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) request->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* All TRBs have finished, clear the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) priv_req->finished_trb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) trace_cdns3_gadget_giveback(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (priv_dev->dev_ver < DEV_VER_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (request->complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_unlock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) usb_gadget_giveback_request(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) spin_lock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (request->buf == priv_dev->zlp_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Work around for stale data address in TRB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (priv_ep->wa1_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) trace_cdns3_wa1(priv_ep, "restore cycle bit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) priv_ep->wa1_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) priv_ep->wa1_trb_index = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (priv_ep->wa1_cycle_bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) priv_ep->wa1_trb->control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) priv_ep->wa1_trb->control | cpu_to_le32(0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) priv_ep->wa1_trb->control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) priv_ep->wa1_trb->control & cpu_to_le32(~0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static void cdns3_free_aligned_request_buf(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) aligned_buf_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct cdns3_aligned_buf *buf, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!buf->in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) list_del(&buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * Re-enable interrupts to free DMA capable memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * Driver can't free this memory with disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dma_free_coherent(priv_dev->sysdev, buf->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) buf->buf, buf->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct cdns3_aligned_buf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* check if buffer is aligned to 8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!((uintptr_t)priv_req->request.buf & 0x7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) buf = priv_req->aligned_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!buf || priv_req->request.length > buf->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) buf->size = priv_req->request.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) buf->buf = dma_alloc_coherent(priv_dev->sysdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) buf->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &buf->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!buf->buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (priv_req->aligned_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) trace_cdns3_free_aligned_request(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) priv_req->aligned_buf->in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) queue_work(system_freezable_wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) &priv_dev->aligned_buf_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) buf->in_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) priv_req->aligned_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) list_add_tail(&buf->list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) &priv_dev->aligned_buf_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (priv_ep->dir == USB_DIR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) memcpy(buf->buf, priv_req->request.buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) priv_req->request.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) priv_req->flags |= REQUEST_UNALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) trace_cdns3_prepare_aligned_request(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct cdns3_trb *trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!priv_ep->wa1_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (doorbell) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) priv_ep->wa1_set = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) priv_ep->wa1_trb = trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) priv_ep->wa1_trb_index = priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) trace_cdns3_wa1(priv_ep, "set guard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int dma_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u32 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!doorbell || dma_index != priv_ep->wa1_trb_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) cdns3_wa1_restore_cycle_bit(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int cdns3_ep_run_stream_transfer(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct cdns3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dma_addr_t trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) unsigned int sg_idx = priv_ep->stream_sg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) address = priv_ep->endpoint.desc->bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) priv_ep->flags |= EP_PENDING_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* must allocate buffer aligned to 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (priv_req->flags & REQUEST_UNALIGNED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) trb_dma = priv_req->aligned_buf->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) trb_dma = request->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* For stream capable endpoints driver use only single TD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) trb = priv_ep->trb_pool + priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) priv_req->start_trb = priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) priv_req->end_trb = priv_req->start_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) priv_req->trb = trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) cdns3_select_ep(priv_ep->cdns3_dev, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) control = TRB_TYPE(TRB_NORMAL) | TRB_CYCLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) TRB_STREAM_ID(priv_req->request.stream_id) | TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!request->num_sgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) length = request->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) trb->buffer = cpu_to_le32(TRB_BUFFER(request->sg[sg_idx].dma_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) length = request->sg[sg_idx].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) tdl = DIV_ROUND_UP(length, priv_ep->endpoint.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) trb->length = cpu_to_le32(TRB_BURST_LEN(16) | TRB_LEN(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * For DEV_VER_V2 controller version we have enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * USB_CONF2_EN_TDL_TRB in DMULT configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * This enables TDL calculation based on TRB, hence setting TDL in TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (priv_dev->dev_ver >= DEV_VER_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (priv_dev->gadget.speed == USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) trb->length |= cpu_to_le32(TRB_TDL_SS_SIZE(tdl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) priv_req->flags |= REQUEST_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) trb->control = cpu_to_le32(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * Memory barrier - Cycle Bit must be set before trb->length and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * trb->buffer fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* always first element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) &priv_dev->regs->ep_traddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!(priv_ep->flags & EP_STALLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) trace_cdns3_ring(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) priv_ep->prime_flag = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * Controller version DEV_VER_V2 tdl calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * is based on TRB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (priv_dev->dev_ver < DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) else if (priv_dev->dev_ver > DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) writel(tdl, &priv_dev->regs->ep_tdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) priv_ep->last_stream_id = priv_req->request.stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) writel(EP_CMD_ERDY_SID(priv_req->request.stream_id) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) EP_CMD_ERDY, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) trace_cdns3_doorbell_epx(priv_ep->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) readl(&priv_dev->regs->ep_traddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* WORKAROUND for transition to L0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) __cdns3_gadget_wakeup(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void cdns3_rearm_drdy_if_needed(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (priv_dev->dev_ver < DEV_VER_V3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (readl(&priv_dev->regs->ep_sts) & EP_STS_TRBERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) writel(EP_STS_TRBERR, &priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * @priv_ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * @request: request object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Returns zero on success or negative value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct cdns3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct cdns3_trb *link_trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dma_addr_t trb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u32 togle_pcs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int sg_iter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int num_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u16 total_tdl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct scatterlist *s = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) bool sg_supported = !!(request->num_mapped_sgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) num_trb = priv_ep->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) num_trb = sg_supported ? request->num_mapped_sgs : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (num_trb > priv_ep->free_trbs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) priv_ep->flags |= EP_RING_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) address = priv_ep->endpoint.desc->bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) priv_ep->flags |= EP_PENDING_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* must allocate buffer aligned to 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (priv_req->flags & REQUEST_UNALIGNED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) trb_dma = priv_req->aligned_buf->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) trb_dma = request->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) trb = priv_ep->trb_pool + priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) priv_req->start_trb = priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) priv_req->trb = trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) cdns3_select_ep(priv_ep->cdns3_dev, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* prepare ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int doorbell, dma_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 ch_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Driver can't update LINK TRB if it is current processed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (doorbell && dma_index == priv_ep->num_trbs - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) priv_ep->flags |= EP_DEFERRED_DRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /*updating C bt in Link TRB before starting DMA*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * For TRs size equal 2 enabling TRB_CHAIN for epXin causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * that DMA stuck at the LINK TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * On the other hand, removing TRB_CHAIN for longer TRs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * epXout cause that DMA stuck after handling LINK TRB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * To eliminate this strange behavioral driver set TRB_CHAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * bit only for TR size > 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) TRBS_PER_SEGMENT > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ch_bit = TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) link_trb->control = cpu_to_le32(((priv_ep->pcs) ? TRB_CYCLE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (priv_dev->dev_ver <= DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (sg_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) s = request->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* set incorrect Cycle Bit for first trb*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) control = priv_ep->pcs ? 0 : TRB_CYCLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) trb->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (priv_dev->dev_ver >= DEV_VER_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u16 td_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) td_size = DIV_ROUND_UP(request->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) priv_ep->endpoint.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (priv_dev->gadget.speed == USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) trb->length = TRB_TDL_SS_SIZE(td_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) control |= TRB_TDL_HS_SIZE(td_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* fill TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) control |= TRB_TYPE(TRB_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (sg_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) trb->buffer = cpu_to_le32(TRB_BUFFER(sg_dma_address(s)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) length = sg_dma_len(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) length = request->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (priv_ep->flags & EP_TDLCHK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) total_tdl += DIV_ROUND_UP(length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) priv_ep->endpoint.maxpacket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) trb->length |= cpu_to_le32(TRB_BURST_LEN(priv_ep->trb_burst_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) TRB_LEN(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pcs = priv_ep->pcs ? TRB_CYCLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * first trb should be prepared as last to avoid processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * transfer to early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (sg_iter != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) control |= pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) control |= TRB_IOC | TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* for last element in TD or in SG list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (sg_iter == (num_trb - 1) && sg_iter != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) control |= pcs | TRB_IOC | TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (sg_iter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) trb->control = cpu_to_le32(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) priv_req->trb->control = cpu_to_le32(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (sg_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) trb->control |= TRB_ISP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* Don't set chain bit for last TRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (sg_iter < num_trb - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) trb->control |= TRB_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) s = sg_next(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ++sg_iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) priv_req->end_trb = priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) cdns3_ep_inc_enq(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) trb = priv_ep->trb_pool + priv_ep->enqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) trb->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) } while (sg_iter < num_trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) trb = priv_req->trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) priv_req->flags |= REQUEST_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) priv_req->num_of_trb = num_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (sg_iter == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) trb->control |= cpu_to_le32(TRB_IOC | TRB_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (priv_dev->dev_ver < DEV_VER_V2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) (priv_ep->flags & EP_TDLCHK_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u16 tdl = total_tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u16 old_tdl = EP_CMD_TDL_GET(readl(&priv_dev->regs->ep_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (tdl > EP_CMD_TDL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) tdl = EP_CMD_TDL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) priv_ep->pending_tdl = total_tdl - EP_CMD_TDL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (old_tdl < tdl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) tdl -= old_tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * Memory barrier - cycle bit must be set before other filds in trb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* give the TD to the consumer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (togle_pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) trb->control = trb->control ^ cpu_to_le32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (priv_dev->dev_ver <= DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (num_trb > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) while (i < num_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) trace_cdns3_prepare_trb(priv_ep, trb + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (trb + i == link_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) trb = priv_ep->trb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) num_trb = num_trb - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * Memory barrier - Cycle Bit must be set before trb->length and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * trb->buffer fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * For DMULT mode we can set address to transfer ring only once after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * enabling endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * Until SW is not ready to handle the OUT transfer the ISO OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Endpoint should be disabled (EP_CFG.ENABLE = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * EP_CFG_ENABLE must be set before updating ep_traddr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) priv_ep->flags |= EP_QUIRK_ISO_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) EP_CFG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) priv_req->start_trb * TRB_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) &priv_dev->regs->ep_traddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) trace_cdns3_ring(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) cdns3_rearm_drdy_if_needed(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) trace_cdns3_doorbell_epx(priv_ep->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) readl(&priv_dev->regs->ep_traddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* WORKAROUND for transition to L0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) __cdns3_gadget_wakeup(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct usb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (priv_dev->hw_configured_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) cdns3_set_register_bit(&priv_dev->regs->usb_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) USB_CONF_U1EN | USB_CONF_U2EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) priv_dev->hw_configured_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (ep->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) cdns3_allow_enable_l1(priv_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * cdns3_trb_handled - check whether trb has been handled by DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * @priv_ep: extended endpoint object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * @priv_req: request object for checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * Endpoint must be selected before invoking this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * Returns false if request has not been handled by DMA, else returns true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * SR - start ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * ER - end ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * DQ = priv_ep->dequeue - dequeue position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * EQ = priv_ep->enqueue - enqueue position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * ST = priv_req->start_trb - index of first TRB in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * ET = priv_req->end_trb - index of last TRB in transfer ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) * CI = current_index - index of processed TRB by DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * As first step, we check if the TRB between the ST and ET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * Then, we check if cycle bit for index priv_ep->dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * some rules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * 1. priv_ep->dequeue never equals to current_index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * 2 priv_ep->enqueue never exceed priv_ep->dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * 3. exception: priv_ep->enqueue == priv_ep->dequeue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * and priv_ep->free_trbs is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * This case indicate that TR is full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * At below two cases, the request have been handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * Case 1 - priv_ep->dequeue < current_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * SR ... EQ ... DQ ... CI ... ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * SR ... DQ ... CI ... EQ ... ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * Case 2 - priv_ep->dequeue > current_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * This situation takes place when CI go through the LINK TRB at the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * transfer ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * SR ... CI ... EQ ... DQ ... ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static bool cdns3_trb_handled(struct cdns3_endpoint *priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct cdns3_request *priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct cdns3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int current_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) current_index = cdns3_get_dma_pos(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* current trb doesn't belong to this request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (priv_req->start_trb < priv_req->end_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (priv_ep->dequeue > priv_req->end_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (priv_ep->dequeue < priv_req->start_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if ((priv_req->start_trb > priv_req->end_trb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) (priv_ep->dequeue > priv_req->end_trb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) (priv_ep->dequeue < priv_req->start_trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if ((priv_req->start_trb == priv_req->end_trb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) (priv_ep->dequeue != priv_req->end_trb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) trb = &priv_ep->trb_pool[priv_ep->dequeue];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if ((le32_to_cpu(trb->control) & TRB_CYCLE) != priv_ep->ccs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (doorbell == 1 && current_index == priv_ep->dequeue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* The corner case for TRBS_PER_SEGMENT equal 2). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (priv_ep->enqueue == priv_ep->dequeue &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) priv_ep->free_trbs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) } else if (priv_ep->dequeue < current_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if ((current_index == (priv_ep->num_trbs - 1)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) !priv_ep->dequeue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) } else if (priv_ep->dequeue > current_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) trace_cdns3_request_handled(priv_req, current_index, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct usb_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct cdns3_trb *trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) bool request_handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) bool transfer_end = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) while (!list_empty(&priv_ep->pending_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) request = cdns3_next_request(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) trb = priv_ep->trb_pool + priv_ep->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* Request was dequeued and TRB was changed to TRB_LINK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (TRB_FIELD_TO_TYPE(le32_to_cpu(trb->control)) == TRB_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) trace_cdns3_complete_trb(priv_ep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) cdns3_move_deq_to_next_trb(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (!request->stream_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Re-select endpoint. It could be changed by other CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * during handling usb_gadget_giveback_request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) while (cdns3_trb_handled(priv_ep, priv_req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) priv_req->finished_trb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (priv_req->finished_trb >= priv_req->num_of_trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) request_handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) trb = priv_ep->trb_pool + priv_ep->dequeue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) trace_cdns3_complete_trb(priv_ep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!transfer_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) request->actual +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) TRB_LEN(le32_to_cpu(trb->length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (priv_req->num_of_trb > 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) le32_to_cpu(trb->control) & TRB_SMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) transfer_end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) cdns3_ep_inc_deq(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (request_handled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) cdns3_gadget_giveback(priv_ep, priv_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) request_handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) transfer_end = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) goto prepare_next_td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (priv_ep->type != USB_ENDPOINT_XFER_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) TRBS_PER_SEGMENT == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Re-select endpoint. It could be changed by other CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * during handling usb_gadget_giveback_request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) trb = priv_ep->trb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) trace_cdns3_complete_trb(priv_ep, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (trb != priv_req->trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dev_warn(priv_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) "request_trb=0x%p, queue_trb=0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) priv_req->trb, trb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) request->actual += TRB_LEN(le32_to_cpu(trb->length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (!request->num_sgs ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) (request->num_sgs == (priv_ep->stream_sg_idx + 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) priv_ep->stream_sg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) cdns3_gadget_giveback(priv_ep, priv_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) priv_ep->stream_sg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) cdns3_ep_run_stream_transfer(priv_ep, request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) priv_ep->flags &= ~EP_PENDING_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) prepare_next_td:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (!(priv_ep->flags & EP_STALLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) !(priv_ep->flags & EP_STALL_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) cdns3_wa1_restore_cycle_bit(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (rearm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) trace_cdns3_ring(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* Cycle Bit must be updated before arming DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) __cdns3_gadget_wakeup(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) trace_cdns3_doorbell_epx(priv_ep->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) readl(&priv_dev->regs->ep_traddr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static void cdns3_reprogram_tdl(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u16 tdl = priv_ep->pending_tdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (tdl > EP_CMD_TDL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) tdl = EP_CMD_TDL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) priv_ep->pending_tdl -= EP_CMD_TDL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) priv_ep->pending_tdl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) writel(EP_CMD_TDL_SET(tdl) | EP_CMD_STDL, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * @priv_ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * Returns 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) u32 ep_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct usb_request *deferred_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct usb_request *pending_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) u32 tdl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) trace_cdns3_epx_irq(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ep_sts_reg = readl(&priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) writel(ep_sts_reg, &priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if ((ep_sts_reg & EP_STS_PRIME) && priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) bool dbusy = !!(ep_sts_reg & EP_STS_DBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) tdl = cdns3_get_tdl(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * Continue the previous transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * There is some racing between ERDY and PRIME. The device send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * ERDY and almost in the same time Host send PRIME. It cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * that host ignore the ERDY packet and driver has to send it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (tdl && (dbusy || !EP_STS_BUFFEMPTY(ep_sts_reg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) EP_STS_HOSTPP(ep_sts_reg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) writel(EP_CMD_ERDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) EP_CMD_ERDY_SID(priv_ep->last_stream_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ep_sts_reg &= ~(EP_STS_MD_EXIT | EP_STS_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) priv_ep->prime_flag = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) pending_request = cdns3_next_request(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) deferred_request = cdns3_next_request(&priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (deferred_request && !pending_request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (ep_sts_reg & EP_STS_TRBERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (priv_ep->flags & EP_STALL_PENDING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) !(ep_sts_reg & EP_STS_DESCMIS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) priv_dev->dev_ver < DEV_VER_V2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) cdns3_ep_stall_flush(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * For isochronous transfer driver completes request on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * IOC or on TRBERR. IOC appears only when device receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * OUT data packet. If host disable stream or lost some packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * then the only way to finish all queued transfer is to do it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) * on TRBERR event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) !priv_ep->wa1_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (!priv_ep->dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u32 ep_cfg = readl(&priv_dev->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ep_cfg &= ~EP_CFG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) writel(ep_cfg, &priv_dev->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) cdns3_transfer_completed(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) } else if (!(priv_ep->flags & EP_STALLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) !(priv_ep->flags & EP_STALL_PENDING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (priv_ep->flags & EP_DEFERRED_DRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) priv_ep->flags &= ~EP_DEFERRED_DRDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) cdns3_rearm_transfer(priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) priv_ep->wa1_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) (ep_sts_reg & EP_STS_IOT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (ep_sts_reg & EP_STS_ISP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) priv_ep->flags |= EP_QUIRK_END_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) priv_ep->flags &= ~EP_QUIRK_END_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if ((ep_sts_reg & EP_STS_IOC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) (ep_sts_reg & EP_STS_ISP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) cdns3_transfer_completed(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) } else if ((priv_ep->flags & EP_TDLCHK_EN) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) priv_ep->pending_tdl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* handle IOT with pending tdl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) cdns3_reprogram_tdl(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) } else if (priv_ep->dir == USB_DIR_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) priv_ep->ep_sts_pending |= ep_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) } else if (ep_sts_reg & EP_STS_IOT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) cdns3_transfer_completed(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * MD_EXIT interrupt sets when stream capable endpoint exits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * from MOVE DATA state of Bulk IN/OUT stream protocol state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (priv_ep->dir == USB_DIR_OUT && (ep_sts_reg & EP_STS_MD_EXIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) (priv_ep->ep_sts_pending & EP_STS_IOT) && priv_ep->use_streams) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) priv_ep->ep_sts_pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) cdns3_transfer_completed(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * WA2: this condition should only be meet when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * In other cases this interrupt will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) !(priv_ep->flags & EP_STALLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) cdns3_wa2_descmissing_packet(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) priv_dev->gadget_driver->disconnect(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * @usb_ists: bitmap representation of device's reported interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * (usb_ists register value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u32 usb_ists)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) __must_hold(&priv_dev->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) int speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) trace_cdns3_usb_irq(priv_dev, usb_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (usb_ists & USB_ISTS_L1ENTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * WORKAROUND: CDNS3 controller has issue with hardware resuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) * from L1. To fix it, if any DMA transfer is pending driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) * must starts driving resume signal immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (readl(&priv_dev->regs->drbl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) __cdns3_gadget_wakeup(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* Connection detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) speed = cdns3_get_speed(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) priv_dev->gadget.speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) cdns3_ep0_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* Disconnection detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) spin_unlock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) cdns3_disconnect_gadget(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) spin_lock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) cdns3_hw_reset_eps_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (priv_dev->gadget_driver &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) priv_dev->gadget_driver->suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) spin_unlock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) priv_dev->gadget_driver->suspend(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) spin_lock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (priv_dev->gadget_driver &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) priv_dev->gadget_driver->resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) spin_unlock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) priv_dev->gadget_driver->resume(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) spin_lock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* reset*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (priv_dev->gadget_driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) spin_unlock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) usb_gadget_udc_reset(&priv_dev->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) priv_dev->gadget_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) spin_lock(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /*read again to check the actual speed*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) speed = cdns3_get_speed(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) priv_dev->gadget.speed = speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) cdns3_hw_reset_eps_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) cdns3_ep0_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) * cdns3_device_irq_handler- interrupt handler for device part of controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) * @irq: irq number for cdns3 core device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) * @data: structure of cdns3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * Returns IRQ_HANDLED or IRQ_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) struct cdns3_device *priv_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct cdns3 *cdns = dev_get_drvdata(priv_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (cdns->in_lpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* check USB device interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) reg = readl(&priv_dev->regs->usb_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* After masking interrupts the new interrupts won't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) * reported in usb_ists/ep_ists. In order to not lose some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) * of them driver disables only detected interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) * They will be enabled ASAP after clearing source of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * interrupt. This an unusual behavior only applies to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * usb_ists register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) reg = ~reg & readl(&priv_dev->regs->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* mask deferred interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) writel(reg, &priv_dev->regs->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* check endpoint interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) reg = readl(&priv_dev->regs->ep_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) writel(0, &priv_dev->regs->ep_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) * cdns3_device_thread_irq_handler- interrupt handler for device part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) * of controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * @irq: irq number for cdns3 core device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * @data: structure of cdns3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * Returns IRQ_HANDLED or IRQ_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) struct cdns3_device *priv_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) reg = readl(&priv_dev->regs->usb_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) writel(reg, &priv_dev->regs->usb_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) cdns3_check_usb_interrupt_proceed(priv_dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) reg = readl(&priv_dev->regs->ep_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* handle default endpoint OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (reg & EP_ISTS_EP_OUT0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* handle default endpoint IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (reg & EP_ISTS_EP_IN0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* check if interrupt from non default endpoint, if no exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) goto irqend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) for_each_set_bit(bit, ®,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) sizeof(u32) * BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (priv_dev->dev_ver < DEV_VER_V2 && priv_dev->using_streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) cdns3_wa2_check_outq_status(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) irqend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) writel(~0, &priv_dev->regs->ep_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) * The real reservation will occur during write to EP_CFG register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * this function is used to check if the 'size' reservation is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * @size: the size (KB) for EP would like to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * @is_in: endpoint direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * Return 0 if the required size can met or negative value on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) int size, int is_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) int remained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* 2KB are reserved for EP0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (is_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (remained < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) priv_dev->onchip_used_size += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) int required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * ALL OUT EPs are shared the same chunk onchip memory, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * driver checks if it already has assigned enough buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (priv_dev->out_mem_is_allocated >= size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) required = size - priv_dev->out_mem_is_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) if (required > remained)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) priv_dev->out_mem_is_allocated += required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) priv_dev->onchip_used_size += required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static void cdns3_configure_dmult(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (priv_dev->dev_ver <= DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) writel(USB_CONF_DMULT, ®s->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (priv_dev->dev_ver == DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) writel(USB_CONF2_EN_TDL_TRB, ®s->usb_conf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (priv_ep->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) mask = BIT(priv_ep->num + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) mask = BIT(priv_ep->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (priv_ep->type != USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) cdns3_set_register_bit(®s->tdl_from_trb, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) cdns3_set_register_bit(®s->tdl_beh, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) cdns3_set_register_bit(®s->tdl_beh2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) cdns3_set_register_bit(®s->dma_adv_td, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) cdns3_set_register_bit(®s->tdl_from_trb, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) cdns3_set_register_bit(®s->dtrans, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * cdns3_ep_config Configure hardware endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * @priv_ep: extended endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) * @enable: set EP_CFG_ENABLE bit in ep_cfg register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) u32 bEndpointAddress = priv_ep->num | priv_ep->dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) u32 max_packet_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) u8 maxburst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) u32 ep_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) u8 buffering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) u8 mult = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) buffering = CDNS3_EP_BUF_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) cdns3_configure_dmult(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) switch (priv_ep->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) case USB_ENDPOINT_XFER_INT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (priv_dev->dev_ver >= DEV_VER_V2 && !priv_ep->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ep_cfg |= EP_CFG_TDL_CHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) case USB_ENDPOINT_XFER_BULK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (priv_dev->dev_ver >= DEV_VER_V2 && !priv_ep->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ep_cfg |= EP_CFG_TDL_CHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) mult = CDNS3_EP_ISO_HS_MULT - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) buffering = mult + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) switch (priv_dev->gadget.speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) max_packet_size = is_iso_ep ? 1023 : 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) max_packet_size = is_iso_ep ? 1024 : 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* It's limitation that driver assumes in driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) mult = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) max_packet_size = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) maxburst = CDNS3_EP_ISO_SS_BURST - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) buffering = (mult + 1) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) (maxburst + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (priv_ep->interval > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) buffering++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) maxburst = CDNS3_EP_BUF_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* all other speed are not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (max_packet_size == 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) priv_ep->trb_burst_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) else if (max_packet_size >= 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) priv_ep->trb_burst_size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) priv_ep->trb_burst_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /* onchip buffer is only allocated before configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (!priv_dev->hw_configured_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) !!priv_ep->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ep_cfg |= EP_CFG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (priv_ep->use_streams && priv_dev->gadget.speed >= USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (priv_dev->dev_ver >= DEV_VER_V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) u32 mask = BIT(priv_ep->num + (priv_ep->dir ? 16 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * Stream capable endpoints are handled by using ep_tdl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) * register. Other endpoints use TDL from TRB feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) cdns3_clear_register_bit(&priv_dev->regs->tdl_from_trb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* Enable Stream Bit TDL chk and SID chk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ep_cfg |= EP_CFG_STREAM_EN | EP_CFG_TDL_CHK | EP_CFG_SID_CHK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) EP_CFG_MULT(mult) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) EP_CFG_BUFFERING(buffering) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) EP_CFG_MAXBURST(maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) cdns3_select_ep(priv_dev, bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) writel(ep_cfg, &priv_dev->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) priv_ep->flags |= EP_CONFIGURED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) priv_ep->name, ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* Find correct direction for HW endpoint according to description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) struct usb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) unsigned long num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* ep name pattern likes epXin or epXout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) char c[2] = {ep->name[2], '\0'};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ret = kstrtoul(c, 10, &num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (cdns3_ep_dir_is_correct(desc, priv_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (!(priv_ep->flags & EP_CLAIMED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) priv_ep->num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) return priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * Cadence IP has one limitation that all endpoints must be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * (Type & MaxPacketSize) before setting configuration through hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * register, it means we can't change endpoints configuration after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) * set_configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * This function set EP_CLAIMED flag which is added when the gadget driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * uses usb_ep_autoconfig to configure specific endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * When the udc driver receives set_configurion request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) * it goes through all claimed endpoints, and configure all endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) * At usb_ep_ops.enable/disable, we only enable and disable endpoint through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) * ep_cfg register which can be changed after set_configuration, and do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) * some software operation accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct usb_endpoint_descriptor *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct usb_ss_ep_comp_descriptor *comp_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) priv_ep = cdns3_find_available_ep(priv_dev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (IS_ERR(priv_ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) dev_err(priv_dev->dev, "no available ep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) priv_ep->endpoint.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) priv_ep->type = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) priv_ep->flags |= EP_CLAIMED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) return &priv_ep->endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * cdns3_gadget_ep_alloc_request Allocates request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * @ep: endpoint object associated with request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * @gfp_flags: gfp flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) * Returns allocated request address, NULL on allocation error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) priv_req = kzalloc(sizeof(*priv_req), gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (!priv_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) priv_req->priv_ep = priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) trace_cdns3_alloc_request(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) return &priv_req->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) * cdns3_gadget_ep_free_request Free memory occupied by request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * @ep: endpoint object associated with request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * @request: request to free memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) void cdns3_gadget_ep_free_request(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct cdns3_request *priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) if (priv_req->aligned_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) priv_req->aligned_buf->in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) trace_cdns3_free_request(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) kfree(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * cdns3_gadget_ep_enable Enable endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * @ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * @desc: endpoint descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static int cdns3_gadget_ep_enable(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) const struct usb_endpoint_descriptor *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) struct cdns3_device *priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) const struct usb_ss_ep_comp_descriptor *comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) u32 reg = EP_STS_EN_TRBERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) u32 bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) int enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) comp_desc = priv_ep->endpoint.comp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) dev_dbg(priv_dev->dev, "usbss: invalid parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (!desc->wMaxPacketSize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) if (dev_WARN_ONCE(priv_dev->dev, priv_ep->flags & EP_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "%s is already enabled\n", priv_ep->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) priv_ep->endpoint.desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) priv_ep->type = usb_endpoint_type(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (priv_ep->interval > ISO_MAX_INTERVAL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) dev_err(priv_dev->dev, "Driver is limited to %d period\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ISO_MAX_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) bEndpointAddress = priv_ep->num | priv_ep->dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) cdns3_select_ep(priv_dev, bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * For some versions of controller at some point during ISO OUT traffic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * DMA reads Transfer Ring for the EP which has never got doorbell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * This issue was detected only on simulation, but to avoid this issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) * driver add protection against it. To fix it driver enable ISO OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * endpoint before setting DRBL. This special treatment of ISO OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) * endpoints are recommended by controller specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) * Enable stream support (SS mode) related interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) * in EP_STS_EN Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (priv_dev->gadget.speed >= USB_SPEED_SUPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) reg |= EP_STS_EN_IOTEN | EP_STS_EN_PRIMEEEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) EP_STS_EN_SIDERREN | EP_STS_EN_MD_EXITEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) EP_STS_EN_STREAMREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) priv_ep->use_streams = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ret = cdns3_ep_config(priv_ep, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) priv_dev->using_streams |= true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ret = cdns3_ep_config(priv_ep, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ret = cdns3_allocate_trb_pool(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) bEndpointAddress = priv_ep->num | priv_ep->dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) cdns3_select_ep(priv_dev, bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) trace_cdns3_gadget_ep_enable(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) 1, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) cdns3_free_trb_pool(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) /* enable interrupt for selected endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) cdns3_set_register_bit(&priv_dev->regs->ep_ien,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) BIT(cdns3_ep_addr_to_index(bEndpointAddress)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (priv_dev->dev_ver < DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) cdns3_wa2_enable_detection(priv_dev, priv_ep, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) writel(reg, &priv_dev->regs->ep_sts_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ep->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) priv_ep->wa1_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) priv_ep->enqueue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) priv_ep->dequeue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) reg = readl(&priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) priv_ep->pcs = !!EP_STS_CCS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) priv_ep->ccs = !!EP_STS_CCS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* one TRB is reserved for link TRB used in DMULT mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) priv_ep->free_trbs = priv_ep->num_trbs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) * cdns3_gadget_ep_disable Disable endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) * @ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static int cdns3_gadget_ep_disable(struct usb_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) struct cdns3_device *priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) struct usb_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) u32 ep_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) pr_err("usbss: invalid parameters\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (dev_WARN_ONCE(priv_dev->dev, !(priv_ep->flags & EP_ENABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) "%s is already disabled\n", priv_ep->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) trace_cdns3_gadget_ep_disable(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ep_cfg = readl(&priv_dev->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ep_cfg &= ~EP_CFG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) writel(ep_cfg, &priv_dev->regs->ep_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * Driver needs some time before resetting endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * It need waits for clearing DBUSY bit or for timeout expired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) * 10us is enough time for controller to stop transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) !(val & EP_STS_DBUSY), 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) 1, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) priv_ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) while (!list_empty(&priv_ep->pending_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) request = cdns3_next_request(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) kfree(priv_req->request.buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) cdns3_gadget_ep_free_request(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) &priv_req->request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) list_del_init(&priv_req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) --priv_ep->wa2_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) while (!list_empty(&priv_ep->deferred_req_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) request = cdns3_next_request(&priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) -ESHUTDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) priv_ep->descmis_req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ep->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) priv_ep->flags &= ~EP_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) priv_ep->use_streams = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * cdns3_gadget_ep_queue Transfer data on endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) * @ep: endpoint object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) * @request: request object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) * @gfp_flags: gfp flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) request->actual = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) request->status = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) trace_cdns3_ep_queue(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) if (priv_dev->dev_ver < DEV_VER_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (ret == EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ret = cdns3_prepare_aligned_request_buf(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ret = usb_gadget_map_request_by_dev(priv_dev->sysdev, request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) usb_endpoint_dir_in(ep->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) list_add_tail(&request->list, &priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) * For stream capable endpoint if prime irq flag is set then only start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) * If hardware endpoint configuration has not been set yet then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) * just queue request in deferred list. Transfer will be started in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * cdns3_set_hw_configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (!request->stream_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (priv_dev->hw_configured_flag &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) !(priv_ep->flags & EP_STALLED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) !(priv_ep->flags & EP_STALL_PENDING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (priv_dev->hw_configured_flag && priv_ep->prime_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) struct usb_request *zlp_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) struct cdns3_device *priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (!request || !ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (ret == 0 && request->zero && request->length &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) (request->length % ep->maxpacket == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) zlp_request->buf = priv_dev->zlp_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) zlp_request->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) priv_req = to_cdns3_request(zlp_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) priv_req->flags |= REQUEST_ZLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) priv_ep->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) * cdns3_gadget_ep_dequeue Remove request from transfer queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) * @ep: endpoint object associated with request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) * @request: request object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) int cdns3_gadget_ep_dequeue(struct usb_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct usb_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) struct usb_request *req, *req_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct cdns3_trb *link_trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) u8 req_on_hw_ring = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (!ep || !request || !ep->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) trace_cdns3_ep_dequeue(priv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (request == req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) req_on_hw_ring = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (request == req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) goto not_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) link_trb = priv_req->trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) /* Update ring only if removed request is on pending_req_list list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (req_on_hw_ring && link_trb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) link_trb->buffer = cpu_to_le32(TRB_BUFFER(priv_ep->trb_pool_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) ((priv_req->end_trb + 1) * TRB_SIZE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) link_trb->control = cpu_to_le32((le32_to_cpu(link_trb->control) & TRB_CYCLE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) TRB_TYPE(TRB_LINK) | TRB_CHAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (priv_ep->wa1_trb == priv_req->trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) cdns3_wa1_restore_cycle_bit(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) not_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) * Should be called after acquiring spin_lock and selecting ep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) * @priv_ep: endpoint object to set stall on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) trace_cdns3_halt(priv_ep, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (!(priv_ep->flags & EP_STALLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) if (!(ep_sts_reg & EP_STS_DBUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) cdns3_ep_stall_flush(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) priv_ep->flags |= EP_STALL_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) * Should be called after acquiring spin_lock and selecting ep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) * @priv_ep: endpoint object to clear stall on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) struct usb_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) struct cdns3_request *priv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct cdns3_trb *trb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) trace_cdns3_halt(priv_ep, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) request = cdns3_next_request(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) priv_req = to_cdns3_request(request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) trb = priv_req->trb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) if (trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* wait for EPRST cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) !(val & EP_CMD_EPRST), 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (request) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) if (trb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) cdns3_rearm_transfer(priv_ep, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) cdns3_start_all_request(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) * @ep: endpoint object to set/clear stall on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * @value: 1 for set stall, 0 for clear stall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (!(priv_ep->flags & EP_ENABLED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (!value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) priv_ep->flags &= ~EP_WEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) ret = __cdns3_gadget_ep_clear_halt(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) __cdns3_gadget_ep_set_halt(priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) extern const struct usb_ep_ops cdns3_gadget_ep0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) static const struct usb_ep_ops cdns3_gadget_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .enable = cdns3_gadget_ep_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .disable = cdns3_gadget_ep_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .alloc_request = cdns3_gadget_ep_alloc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .free_request = cdns3_gadget_ep_free_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .queue = cdns3_gadget_ep_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .dequeue = cdns3_gadget_ep_dequeue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .set_halt = cdns3_gadget_ep_set_halt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .set_wedge = cdns3_gadget_ep_set_wedge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) * cdns3_gadget_get_frame Returns number of actual ITP frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) * @gadget: gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) * Returns number of actual ITP frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) static int cdns3_gadget_get_frame(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) return readl(&priv_dev->regs->usb_itpn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) enum usb_device_speed speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) speed = cdns3_get_speed(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) if (speed >= USB_SPEED_SUPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) /* Start driving resume signaling to indicate remote wakeup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static int cdns3_gadget_wakeup(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) ret = __cdns3_gadget_wakeup(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) int is_selfpowered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) priv_dev->is_selfpowered = !!is_selfpowered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (is_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) writel(~0, &priv_dev->regs->ep_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) writel(~0, &priv_dev->regs->usb_ists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static void cdns3_gadget_config(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) cdns3_ep0_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* enable interrupts for endpoint 0 (in and out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, ®s->ep_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) * revision of controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) if (priv_dev->dev_ver == DEV_VER_TI_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) reg = readl(®s->dbg_link1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) writel(reg, ®s->dbg_link1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) * By default some platforms has set protected access to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) * This cause problem with cache, so driver restore non-secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) * access to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) reg = readl(®s->dma_axi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) writel(reg, ®s->dma_axi_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) /* enable generic interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) writel(USB_IEN_INIT, ®s->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /* keep Fast Access bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) cdns3_configure_dmult(priv_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) * cdns3_gadget_udc_start Gadget start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) * @gadget: gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) * @driver: driver which operates on this gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) struct usb_gadget_driver *driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) enum usb_device_speed max_speed = driver->max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) spin_lock_irqsave(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) priv_dev->gadget_driver = driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* limit speed if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) max_speed = min(driver->max_speed, gadget->max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) switch (max_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) dev_err(priv_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) "invalid maximum_speed parameter %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) case USB_SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /* default to superspeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) max_speed = USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) cdns3_gadget_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) spin_unlock_irqrestore(&priv_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) * cdns3_gadget_udc_stop Stops gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) * @gadget: gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) * Returns 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) u32 bEndpointAddress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) struct usb_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) priv_dev->gadget_driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) priv_dev->onchip_used_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) priv_dev->out_mem_is_allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) priv_ep = ep_to_cdns3_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) bEndpointAddress = priv_ep->num | priv_ep->dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) cdns3_select_ep(priv_dev, bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) !(val & EP_CMD_EPRST), 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) priv_ep->flags &= ~EP_CLAIMED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* disable interrupt for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) writel(0, &priv_dev->regs->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) writel(0, &priv_dev->regs->usb_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static const struct usb_gadget_ops cdns3_gadget_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .get_frame = cdns3_gadget_get_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .wakeup = cdns3_gadget_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .set_selfpowered = cdns3_gadget_set_selfpowered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .pullup = cdns3_gadget_pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .udc_start = cdns3_gadget_udc_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .udc_stop = cdns3_gadget_udc_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .match_ep = cdns3_gadget_match_ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) /* ep0 OUT point to ep0 IN. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) priv_dev->eps[16] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (priv_dev->eps[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) cdns3_free_trb_pool(priv_dev->eps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) devm_kfree(priv_dev->dev, priv_dev->eps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * cdns3_init_eps Initializes software endpoints of gadget
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) * @priv_dev: extended gadget object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) * Returns 0 on success, error code elsewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static int cdns3_init_eps(struct cdns3_device *priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) u32 ep_enabled_reg, iso_ep_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) struct cdns3_endpoint *priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) int ep_dir, ep_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) u32 ep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* Read it from USB_CAP3 to USB_CAP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) ep_enabled_reg = readl(&priv_dev->regs->usb_cap3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) iso_ep_reg = readl(&priv_dev->regs->usb_cap4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) ep_dir = i >> 4; /* i div 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) ep_number = i & 0xF; /* i % 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) ep_mask = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) if (!(ep_enabled_reg & ep_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) if (ep_dir && !ep_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) priv_dev->eps[i] = priv_dev->eps[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) if (!priv_ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) /* set parent of endpoint object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) priv_ep->cdns3_dev = priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) priv_dev->eps[i] = priv_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) priv_ep->num = ep_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (!ep_number) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) ret = cdns3_init_ep0(priv_dev, priv_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) dev_err(priv_dev->dev, "Failed to init ep0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) ep_number, !!ep_dir ? "in" : "out");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) priv_ep->endpoint.name = priv_ep->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) CDNS3_EP_MAX_PACKET_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) priv_ep->endpoint.ops = &cdns3_gadget_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (ep_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) priv_ep->endpoint.caps.dir_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) priv_ep->endpoint.caps.dir_out = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) if (iso_ep_reg & ep_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) priv_ep->endpoint.caps.type_iso = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) priv_ep->endpoint.caps.type_bulk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) priv_ep->endpoint.caps.type_int = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) list_add_tail(&priv_ep->endpoint.ep_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) &priv_dev->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) priv_ep->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) dev_dbg(priv_dev->dev, "Initialized %s support: %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) priv_ep->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) priv_ep->endpoint.caps.type_iso ? "ISO" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) INIT_LIST_HEAD(&priv_ep->pending_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) INIT_LIST_HEAD(&priv_ep->deferred_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) cdns3_free_all_eps(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static void cdns3_gadget_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) struct cdns3_device *priv_dev = container_of(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) struct cdns3_device, gadget.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) kfree(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) void cdns3_gadget_exit(struct cdns3 *cdns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) struct cdns3_device *priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) priv_dev = cdns->gadget_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) pm_runtime_mark_last_busy(cdns->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) pm_runtime_put_autosuspend(cdns->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) usb_del_gadget(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) devm_free_irq(cdns->dev, cdns->dev_irq, priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) cdns3_free_all_eps(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) while (!list_empty(&priv_dev->aligned_buf_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) struct cdns3_aligned_buf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) dma_free_coherent(priv_dev->sysdev, buf->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) buf->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) buf->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) list_del(&buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) priv_dev->setup_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) kfree(priv_dev->zlp_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) usb_put_gadget(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) cdns->gadget_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) cdns3_drd_gadget_off(cdns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) static int cdns3_gadget_start(struct cdns3 *cdns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) struct cdns3_device *priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) u32 max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) if (!priv_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) usb_initialize_gadget(cdns->dev, &priv_dev->gadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) cdns3_gadget_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) cdns->gadget_dev = priv_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) priv_dev->sysdev = cdns->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) priv_dev->dev = cdns->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) priv_dev->regs = cdns->dev_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) &priv_dev->onchip_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (priv_dev->onchip_buffers <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) u32 reg = readl(&priv_dev->regs->usb_cap2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (!priv_dev->onchip_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) priv_dev->onchip_buffers = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) max_speed = usb_get_maximum_speed(cdns->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) /* Check the maximum_speed parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) switch (max_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) case USB_SPEED_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) case USB_SPEED_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) case USB_SPEED_SUPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) case USB_SPEED_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* default to superspeed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) max_speed = USB_SPEED_SUPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) /* fill gadget fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) priv_dev->gadget.max_speed = max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) priv_dev->gadget.ops = &cdns3_gadget_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) priv_dev->gadget.name = "usb-ss-gadget";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) priv_dev->gadget.quirk_avoids_skb_reserve = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) priv_dev->gadget.irq = cdns->dev_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) spin_lock_init(&priv_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) INIT_WORK(&priv_dev->pending_status_wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) cdns3_pending_setup_status_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) INIT_WORK(&priv_dev->aligned_buf_wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) cdns3_free_aligned_request_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /* initialize endpoint container */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) ret = cdns3_init_eps(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) dev_err(priv_dev->dev, "Failed to create endpoints\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) /* allocate memory for setup packet buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) &priv_dev->setup_dma, GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) if (!priv_dev->setup_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) goto err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) readl(&priv_dev->regs->usb_cap6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) readl(&priv_dev->regs->usb_cap1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) dev_dbg(priv_dev->dev, "On-Chip memory configuration: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) readl(&priv_dev->regs->usb_cap2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) if (priv_dev->dev_ver >= DEV_VER_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) priv_dev->gadget.sg_supported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) if (!priv_dev->zlp_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) goto err3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) /* add USB gadget device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) ret = usb_add_gadget(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) dev_err(priv_dev->dev, "Failed to add gadget\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) goto err4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) err4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) kfree(priv_dev->zlp_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) err3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) priv_dev->setup_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) cdns3_free_all_eps(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) usb_put_gadget(&priv_dev->gadget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) cdns->gadget_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) static int __cdns3_gadget_init(struct cdns3 *cdns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* Ensure 32-bit DMA Mask in case we switched back from Host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) ret = dma_set_mask_and_coherent(cdns->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) dev_err(cdns->dev, "Failed to set dma mask: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) cdns3_drd_gadget_on(cdns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) pm_runtime_get_sync(cdns->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) ret = cdns3_gadget_start(cdns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) pm_runtime_put_sync(cdns->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) * Because interrupt line can be shared with other components in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) * driver it can't use IRQF_ONESHOT flag here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) cdns3_device_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) cdns3_device_thread_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) IRQF_SHARED, dev_name(cdns->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) cdns->gadget_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) cdns3_gadget_exit(cdns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) __must_hold(&cdns->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) struct cdns3_device *priv_dev = cdns->gadget_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) spin_unlock(&cdns->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) cdns3_disconnect_gadget(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) spin_lock(&cdns->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) cdns3_hw_reset_eps_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) /* disable interrupt for device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) writel(0, &priv_dev->regs->usb_ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) struct cdns3_device *priv_dev = cdns->gadget_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) if (!priv_dev->gadget_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) cdns3_gadget_config(priv_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) * cdns3_gadget_init - initialize device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) * @cdns: cdns3 instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) * This function initializes the gadget.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) int cdns3_gadget_init(struct cdns3 *cdns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) struct cdns3_role_driver *rdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (!rdrv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) rdrv->start = __cdns3_gadget_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) rdrv->stop = cdns3_gadget_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) rdrv->suspend = cdns3_gadget_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) rdrv->resume = cdns3_gadget_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) rdrv->name = "gadget";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) cdns->roles[USB_ROLE_DEVICE] = rdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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