^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UIO driver for Hilscher NetX based fieldbus cards (cifX, comX).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * See http://www.hilscher.com for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) 2007 Hans J. Koch <hjk@hansjkoch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) 2008 Manuel Traut <manut@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uio_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_VENDOR_ID_HILSCHER 0x15CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVICE_ID_HILSCHER_NETX 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_HILSCHER_NETPLC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_SUBDEVICE_ID_NETPLC_RAM 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_SUBDEVICE_ID_NETPLC_FLASH 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_SUBDEVICE_ID_NXSB_PCA 0x3235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_SUBDEVICE_ID_NXPCA 0x3335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPM_HOST_INT_EN0 0xfff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPM_HOST_INT_STAT0 0xffe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPM_HOST_INT_MASK 0xe600ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPM_HOST_INT_GLOBAL_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static irqreturn_t netx_handler(int irq, struct uio_info *dev_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *int_enable_reg = dev_info->mem[0].internal_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) + DPM_HOST_INT_EN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *int_status_reg = dev_info->mem[0].internal_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) + DPM_HOST_INT_STAT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Is one of our interrupts enabled and active ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (!(ioread32(int_enable_reg) & ioread32(int_status_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) & DPM_HOST_INT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iowrite32(ioread32(int_enable_reg) & ~DPM_HOST_INT_GLOBAL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int_enable_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int netx_pci_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct uio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) info = kzalloc(sizeof(struct uio_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (pci_enable_device(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (pci_request_regions(dev, "netx"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) switch (id->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case PCI_DEVICE_ID_HILSCHER_NETX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) info->name = "netx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case PCI_DEVICE_ID_HILSCHER_NETPLC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) info->name = "netplc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bar = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) info->name = "netx_plx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* BAR0 or 2 points to the card's dual port memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) info->mem[0].addr = pci_resource_start(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (!info->mem[0].addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) goto out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) info->mem[0].internal_addr = ioremap(pci_resource_start(dev, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_resource_len(dev, bar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!info->mem[0].internal_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) goto out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) info->mem[0].size = pci_resource_len(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) info->mem[0].memtype = UIO_MEM_PHYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) info->irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) info->irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) info->handler = netx_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) info->version = "0.0.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Make sure all interrupts are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) iowrite32(0, info->mem[0].internal_addr + DPM_HOST_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (uio_register_device(&dev->dev, info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto out_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_info(&dev->dev, "Found %s card, registered UIO device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) out_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iounmap(info->mem[0].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void netx_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct uio_info *info = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) iowrite32(0, info->mem[0].internal_addr + DPM_HOST_INT_EN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uio_unregister_device(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) iounmap(info->mem[0].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct pci_device_id netx_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .vendor = PCI_VENDOR_ID_HILSCHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .device = PCI_DEVICE_ID_HILSCHER_NETX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .subvendor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .subdevice = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .vendor = PCI_VENDOR_ID_HILSCHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .device = PCI_DEVICE_ID_HILSCHER_NETPLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .subvendor = PCI_VENDOR_ID_HILSCHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .subdevice = PCI_SUBDEVICE_ID_NETPLC_RAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .vendor = PCI_VENDOR_ID_HILSCHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .device = PCI_DEVICE_ID_HILSCHER_NETPLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .subvendor = PCI_VENDOR_ID_HILSCHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .subdevice = PCI_SUBDEVICE_ID_NETPLC_FLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .vendor = PCI_VENDOR_ID_PLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .device = PCI_DEVICE_ID_PLX_9030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .subvendor = PCI_VENDOR_ID_PLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .subdevice = PCI_SUBDEVICE_ID_NXSB_PCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .vendor = PCI_VENDOR_ID_PLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .device = PCI_DEVICE_ID_PLX_9030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .subvendor = PCI_VENDOR_ID_PLX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .subdevice = PCI_SUBDEVICE_ID_NXPCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct pci_driver netx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "netx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .id_table = netx_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .probe = netx_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .remove = netx_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) module_pci_driver(netx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MODULE_DEVICE_TABLE(pci, netx_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_AUTHOR("Hans J. Koch, Manuel Traut");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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