^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * UIO driver fo Humusoft MF624 DAQ card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 Rostislav Lisovy <lisovy@gmail.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Czech Technical University in Prague
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uio_driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCI_VENDOR_ID_HUMUSOFT 0x186c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_DEVICE_ID_MF624 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_SUBVENDOR_ID_HUMUSOFT 0x186c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_SUBDEVICE_DEVICE 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* BAR0 Interrupt control/status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define INTCSR 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define INTCSR_ADINT_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define INTCSR_CTR4INT_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTCSR_PCIINT_ENABLE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTCSR_ADINT_STATUS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define INTCSR_CTR4INT_STATUS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum mf624_interrupt_source {ADC, CTR4, ALL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void mf624_disable_interrupt(enum mf624_interrupt_source source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct uio_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *INTCSR_reg = info->mem[0].internal_addr + INTCSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) switch (source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) case ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) & ~(INTCSR_ADINT_ENABLE | INTCSR_PCIINT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case CTR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) & ~(INTCSR_CTR4INT_ENABLE | INTCSR_PCIINT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) & ~(INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) | INTCSR_PCIINT_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void mf624_enable_interrupt(enum mf624_interrupt_source source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct uio_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *INTCSR_reg = info->mem[0].internal_addr + INTCSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) switch (source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case ADC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) | INTCSR_ADINT_ENABLE | INTCSR_PCIINT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case CTR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) | INTCSR_CTR4INT_ENABLE | INTCSR_PCIINT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case ALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) iowrite32(ioread32(INTCSR_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | INTCSR_ADINT_ENABLE | INTCSR_CTR4INT_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) | INTCSR_PCIINT_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) INTCSR_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static irqreturn_t mf624_irq_handler(int irq, struct uio_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *INTCSR_reg = info->mem[0].internal_addr + INTCSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if ((ioread32(INTCSR_reg) & INTCSR_ADINT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) && (ioread32(INTCSR_reg) & INTCSR_ADINT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mf624_disable_interrupt(ADC, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if ((ioread32(INTCSR_reg) & INTCSR_CTR4INT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) && (ioread32(INTCSR_reg) & INTCSR_CTR4INT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mf624_disable_interrupt(CTR4, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int mf624_irqcontrol(struct uio_info *info, s32 irq_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (irq_on == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mf624_disable_interrupt(ALL, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else if (irq_on == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mf624_enable_interrupt(ALL, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int mf624_setup_mem(struct pci_dev *dev, int bar, struct uio_mem *mem, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) resource_size_t start = pci_resource_start(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) resource_size_t len = pci_resource_len(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mem->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mem->addr = start & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mem->offs = start & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!mem->addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mem->size = ((start & ~PAGE_MASK) + len + PAGE_SIZE - 1) & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mem->memtype = UIO_MEM_PHYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mem->internal_addr = pci_ioremap_bar(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!mem->internal_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int mf624_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct uio_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) info = kzalloc(sizeof(struct uio_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (pci_enable_device(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (pci_request_regions(dev, "mf624"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) info->name = "mf624";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) info->version = "0.0.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Note: Datasheet says device uses BAR0, BAR1, BAR2 -- do not trust it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (mf624_setup_mem(dev, 0, &info->mem[0], "PCI chipset, interrupts, status "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "bits, special functions"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* BAR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (mf624_setup_mem(dev, 2, &info->mem[1], "ADC, DAC, DIO"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto out_unmap0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* BAR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (mf624_setup_mem(dev, 4, &info->mem[2], "Counter/timer chip"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto out_unmap1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) info->irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) info->irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) info->handler = mf624_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) info->irqcontrol = mf624_irqcontrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (uio_register_device(&dev->dev, info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto out_unmap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pci_set_drvdata(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) out_unmap2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iounmap(info->mem[2].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) out_unmap1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) iounmap(info->mem[1].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) out_unmap0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) iounmap(info->mem[0].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void mf624_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct uio_info *info = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mf624_disable_interrupt(ALL, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uio_unregister_device(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_release_regions(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) iounmap(info->mem[0].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) iounmap(info->mem[1].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iounmap(info->mem[2].internal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct pci_device_id mf624_pci_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { PCI_DEVICE(PCI_VENDOR_ID_HUMUSOFT, PCI_DEVICE_ID_MF624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct pci_driver mf624_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "mf624",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .id_table = mf624_pci_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .probe = mf624_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .remove = mf624_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DEVICE_TABLE(pci, mf624_pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_pci_driver(mf624_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_AUTHOR("Rostislav Lisovy <lisovy@gmail.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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