^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-1.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Device driver for Microgate SyncLink ISA and PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * high speed multiprotocol serial adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * written by Paul Fulghum for Microgate Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * paulkf@microgate.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Microgate and SyncLink are trademarks of Microgate Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Original release 01/11/99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This driver is primarily intended for use in synchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * HDLC mode. Asynchronous mode is also provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * When operating in synchronous mode, each call to mgsl_write()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * contains exactly one complete HDLC frame. Calling mgsl_put_char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * will start assembling an HDLC frame that will not be sent until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * mgsl_flush_chars or mgsl_write is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Synchronous receive data is reported as complete frames. To accomplish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * this, the TTY flip buffer is bypassed (too small to hold largest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * frame and may fragment frames) and the line discipline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * receive entry point is called directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * This driver has been tested with a slightly modified ppp.c driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * for synchronous PPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 2000/02/16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Added interface for syncppp.c driver (an alternate synchronous PPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * implementation that also supports Cisco HDLC). Each device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * registers as a tty device AND a network device (if dosyncppp option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * is set for the device). The functionality is determined by which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * device interface is opened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #if defined(__i386__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define BREAKPOINT() asm(" int $3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define BREAKPOINT() { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAX_ISA_DEVICES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAX_PCI_DEVICES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX_TOTAL_DEVICES 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/synclink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/termios.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/hdlc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SYNCLINK_GENERIC_HDLC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SYNCLINK_GENERIC_HDLC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GET_USER(error,value,addr) error = get_user(value,addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PUT_USER(error,value,addr) error = put_user(value,addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RCLRVALUE 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static MGSL_PARAMS default_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MGSL_MODE_HDLC, /* unsigned long mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0, /* unsigned char loopback; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0, /* unsigned long clock_speed; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0xff, /* unsigned char addr_filter; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 9600, /* unsigned long data_rate; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 8, /* unsigned char data_bits; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 1, /* unsigned char stop_bits; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ASYNC_PARITY_NONE /* unsigned char parity; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SHARED_MEM_ADDRESS_SIZE 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BUFFERLISTSIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DMABUFFERSIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MAXRXFRAMES 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) typedef struct _DMABUFFERENTRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 phys_addr; /* 32-bit flat physical address of data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) volatile u16 count; /* buffer size/data count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) volatile u16 status; /* Control/status field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) volatile u16 rcc; /* character count field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 reserved; /* padding required by 16C32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 link; /* 32-bit flat link to next buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) char *virt_addr; /* virtual address of data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 phys_entry; /* physical address of this buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } DMABUFFERENTRY, *DMAPBUFFERENTRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* The queue of BH actions to be performed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BH_RECEIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BH_TRANSMIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BH_STATUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IO_PIN_SHUTDOWN_LIMIT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct _input_signal_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ri_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ri_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int dsr_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int dsr_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int dcd_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int dcd_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int cts_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int cts_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* transmit holding buffer definitions*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAX_TX_HOLDING_BUFFERS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct tx_holding_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned char * buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Device instance data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct mgsl_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct tty_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int hw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct mgsl_icount icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int x_char; /* xon/xoff character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u16 read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 ignore_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char *xmit_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int xmit_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int xmit_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wait_queue_head_t status_event_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) wait_queue_head_t event_wait_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct timer_list tx_timer; /* HDLC transmit timeout timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct mgsl_struct *next_device; /* device list link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct work_struct task; /* task structure for scheduling bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 EventMask; /* event trigger mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 RecordedEvents; /* pending events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 max_frame_size; /* as set by device config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 pending_bh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool bh_running; /* Protection from multiple */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int isr_overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bool bh_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int dcd_chkcount; /* check counts to prevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int cts_chkcount; /* too many IRQs if a signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int dsr_chkcount; /* is floating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ri_chkcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) char *buffer_list; /* virtual address of Rx & Tx buffer lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 buffer_list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dma_addr_t buffer_list_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int current_rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int num_tx_dma_buffers; /* number of tx dma frames required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int tx_dma_buffers_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int current_tx_buffer; /* next tx dma buffer to be loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char *intermediate_rxbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int num_tx_holding_buffers; /* number of tx holding buffer allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int get_tx_holding_index; /* next tx holding buffer for adapter to load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int put_tx_holding_index; /* next tx holding buffer to store user request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int tx_holding_count; /* number of tx holding buffers waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bool rx_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool rx_overflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bool rx_rcc_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool tx_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bool tx_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 idle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u16 cmr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 tcsr_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) char device_name[25]; /* device instance name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned char bus; /* expansion bus number (zero based) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned char function; /* PCI device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int io_base; /* base I/O address of adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int io_addr_size; /* size of the I/O address range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) bool io_addr_requested; /* true if I/O address requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int irq_level; /* interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool irq_requested; /* true if IRQ requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int dma_level; /* DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bool dma_requested; /* true if dma channel requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u16 mbre_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u16 loopback_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 usc_idle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MGSL_PARAMS params; /* communications parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned char serial_signals; /* current serial signal states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool irq_occurred; /* for diagnostics use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int init_error; /* Initialization startup error (DIAGS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 last_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned char* memory_base; /* shared memory address (PCI only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 phys_memory_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bool shared_mem_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned char* lcr_base; /* local config registers (PCI only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 phys_lcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 lcr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bool lcr_mem_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 misc_ctrl_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) char *flag_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bool drop_rts_on_tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bool loopmode_insert_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bool loopmode_send_done_requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct _input_signal_events input_signal_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* generic HDLC device parts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int netcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) spinlock_t netlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MGSL_MAGIC 0x5401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * The size of the serial xmit buffer is 1 page, or 4096 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifndef SERIAL_XMIT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SERIAL_XMIT_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * These macros define the offsets used in calculating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * I/O address of the specified USC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DCPIN 2 /* Bit 1 of I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SDPIN 4 /* Bit 2 of I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DCAR 0 /* DMA command/address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CCAR SDPIN /* channel command/address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DATAREG DCPIN + SDPIN /* serial data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MSBONLY 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define LSBONLY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * These macros define the register address (ordinal number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * used for writing address/value pairs to the USC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CMR 0x02 /* Channel mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CCSR 0x04 /* Channel Command/status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CCR 0x06 /* Channel Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PSR 0x08 /* Port status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PCR 0x0a /* Port Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TMDR 0x0c /* Test mode Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TMCR 0x0e /* Test mode Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CMCR 0x10 /* Clock mode Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HCR 0x12 /* Hardware Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IVR 0x14 /* Interrupt Vector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IOCR 0x16 /* Input/Output Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ICR 0x18 /* Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DCCR 0x1a /* Daisy Chain Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MISR 0x1c /* Misc Interrupt status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SICR 0x1e /* status Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RDR 0x20 /* Receive Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define RMR 0x22 /* Receive mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define RCSR 0x24 /* Receive Command/status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RICR 0x26 /* Receive Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define RSR 0x28 /* Receive Sync Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define RCLR 0x2a /* Receive count Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define RCCR 0x2c /* Receive Character count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TC0R 0x2e /* Time Constant 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TDR 0x30 /* Transmit Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TMR 0x32 /* Transmit mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TCSR 0x34 /* Transmit Command/status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TICR 0x36 /* Transmit Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TSR 0x38 /* Transmit Sync Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TCLR 0x3a /* Transmit count Limit Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TCCR 0x3c /* Transmit Character count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TC1R 0x3e /* Time Constant 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * MACRO DEFINITIONS FOR DMA REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DCR 0x06 /* DMA Control Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DACR 0x08 /* DMA Array count Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TDMR 0x02 /* Transmit DMA mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TBCR 0x2a /* Transmit Byte count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TARL 0x2c /* Transmit Address Register (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TARU 0x2e /* Transmit Address Register (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define NTBCR 0x3a /* Next Transmit Byte count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define NTARL 0x3c /* Next Transmit Address Register (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define NTARU 0x3e /* Next Transmit Address Register (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RBCR 0xaa /* Receive Byte count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RARL 0xac /* Receive Address Register (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RARU 0xae /* Receive Address Register (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define NRBCR 0xba /* Next Receive Byte count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define NRARL 0xbc /* Next Receive Address Register (low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define NRARU 0xbe /* Next Receive Address Register (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * MACRO DEFINITIONS FOR MODEM STATUS BITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MODEMSTATUS_DTR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MODEMSTATUS_DSR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MODEMSTATUS_RTS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MODEMSTATUS_CTS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MODEMSTATUS_RI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MODEMSTATUS_DCD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Channel Command/Address Register (CCAR) Command Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define RTCmd_Null 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RTCmd_ResetHighestIus 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define RTCmd_TriggerChannelLoadDma 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define RTCmd_TriggerRxDma 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RTCmd_TriggerTxDma 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define RTCmd_TriggerRxAndTxDma 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define RTCmd_PurgeRxFifo 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define RTCmd_PurgeTxFifo 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define RTCmd_PurgeRxAndTxFifo 0x5800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define RTCmd_LoadRcc 0x6800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define RTCmd_LoadTcc 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define RTCmd_LoadRccAndTcc 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define RTCmd_LoadTC0 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define RTCmd_LoadTC1 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define RTCmd_LoadTC0AndTC1 0x9800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define RTCmd_SerialDataLSBFirst 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define RTCmd_SerialDataMSBFirst 0xa800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define RTCmd_SelectBigEndian 0xb000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define RTCmd_SelectLittleEndian 0xb800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * DMA Command/Address Register (DCAR) Command Codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define DmaCmd_Null 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define DmaCmd_ResetTxChannel 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define DmaCmd_ResetRxChannel 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define DmaCmd_StartTxChannel 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define DmaCmd_StartRxChannel 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define DmaCmd_ContinueTxChannel 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define DmaCmd_ContinueRxChannel 0x3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DmaCmd_PauseTxChannel 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define DmaCmd_PauseRxChannel 0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define DmaCmd_AbortTxChannel 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define DmaCmd_AbortRxChannel 0x5200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define DmaCmd_InitTxChannel 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define DmaCmd_InitRxChannel 0x7200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define DmaCmd_ResetHighestDmaIus 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define DmaCmd_ResetAllChannels 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define DmaCmd_StartAllChannels 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define DmaCmd_ContinueAllChannels 0xb000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define DmaCmd_PauseAllChannels 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define DmaCmd_AbortAllChannels 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define DmaCmd_InitAllChannels 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define TCmd_Null 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define TCmd_ClearTxCRC 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define TCmd_SelectTicrTtsaData 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define TCmd_SelectTicrTxFifostatus 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define TCmd_SelectTicrIntLevel 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TCmd_SelectTicrdma_level 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TCmd_SendFrame 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TCmd_SendAbort 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TCmd_EnableDleInsertion 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define TCmd_DisableDleInsertion 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define TCmd_ClearEofEom 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define TCmd_SetEofEom 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RCmd_Null 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RCmd_ClearRxCRC 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define RCmd_EnterHuntmode 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RCmd_SelectRicrRtsaData 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RCmd_SelectRicrRxFifostatus 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define RCmd_SelectRicrIntLevel 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RCmd_SelectRicrdma_level 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define RECEIVE_STATUS BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define RECEIVE_DATA BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TRANSMIT_STATUS BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define TRANSMIT_DATA BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IO_PIN BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MISC BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Receive status Bits in Receive Command/status Register RCSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define RXSTATUS_SHORT_FRAME BIT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define RXSTATUS_CODE_VIOLATION BIT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define RXSTATUS_EXITED_HUNT BIT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define RXSTATUS_IDLE_RECEIVED BIT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define RXSTATUS_BREAK_RECEIVED BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define RXSTATUS_ABORT_RECEIVED BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define RXSTATUS_RXBOUND BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define RXSTATUS_CRC_ERROR BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define RXSTATUS_FRAMING_ERROR BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define RXSTATUS_ABORT BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define RXSTATUS_PARITY_ERROR BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define RXSTATUS_OVERRUN BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define RXSTATUS_DATA_AVAILABLE BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define RXSTATUS_ALL 0x01f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Values for setting transmit idle mode in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Transmit Control/status Register (TCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IDLEMODE_FLAGS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IDLEMODE_ALT_ONE_ZERO 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IDLEMODE_ZERO 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IDLEMODE_ONE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define IDLEMODE_ALT_MARK_SPACE 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define IDLEMODE_SPACE 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define IDLEMODE_MARK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define IDLEMODE_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * IUSC revision identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IUSC_SL1660 0x4d44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IUSC_PRE_SL1660 0x4553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Transmit status Bits in Transmit Command/status Register (TCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define TCSR_PRESERVE 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define TCSR_UNDERWAIT BIT11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define TXSTATUS_PREAMBLE_SENT BIT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define TXSTATUS_IDLE_SENT BIT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define TXSTATUS_ABORT_SENT BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define TXSTATUS_EOF_SENT BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define TXSTATUS_EOM_SENT BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define TXSTATUS_CRC_SENT BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define TXSTATUS_ALL_SENT BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define TXSTATUS_UNDERRUN BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define TXSTATUS_FIFO_EMPTY BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define TXSTATUS_ALL 0x00fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MISCSTATUS_RXC_LATCHED BIT15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MISCSTATUS_RXC BIT14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MISCSTATUS_TXC_LATCHED BIT13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MISCSTATUS_TXC BIT12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MISCSTATUS_RI_LATCHED BIT11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MISCSTATUS_RI BIT10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define MISCSTATUS_DSR_LATCHED BIT9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define MISCSTATUS_DSR BIT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MISCSTATUS_DCD_LATCHED BIT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define MISCSTATUS_DCD BIT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MISCSTATUS_CTS_LATCHED BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MISCSTATUS_CTS BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MISCSTATUS_RCC_UNDERRUN BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define MISCSTATUS_DPLL_NO_SYNC BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define MISCSTATUS_BRG1_ZERO BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MISCSTATUS_BRG0_ZERO BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SICR_RXC_ACTIVE BIT15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SICR_RXC_INACTIVE BIT14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SICR_RXC (BIT15|BIT14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SICR_TXC_ACTIVE BIT13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SICR_TXC_INACTIVE BIT12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SICR_TXC (BIT13|BIT12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SICR_RI_ACTIVE BIT11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SICR_RI_INACTIVE BIT10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SICR_RI (BIT11|BIT10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SICR_DSR_ACTIVE BIT9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SICR_DSR_INACTIVE BIT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SICR_DSR (BIT9|BIT8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SICR_DCD_ACTIVE BIT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SICR_DCD_INACTIVE BIT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SICR_DCD (BIT7|BIT6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SICR_CTS_ACTIVE BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SICR_CTS_INACTIVE BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SICR_CTS (BIT5|BIT4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SICR_RCC_UNDERFLOW BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SICR_DPLL_NO_SYNC BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SICR_BRG1_ZERO BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SICR_BRG0_ZERO BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void usc_DisableMasterIrqBit( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) void usc_EnableMasterIrqBit( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define usc_EnableInterrupts( a, b ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define usc_DisableInterrupts( a, b ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define usc_EnableMasterIrqBit(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define usc_DisableMasterIrqBit(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Transmit status Bits in Transmit Control status Register (TCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define TXSTATUS_PREAMBLE_SENT BIT7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define TXSTATUS_IDLE_SENT BIT6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define TXSTATUS_ABORT_SENT BIT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define TXSTATUS_EOF BIT4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define TXSTATUS_CRC_SENT BIT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define TXSTATUS_ALL_SENT BIT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define TXSTATUS_UNDERRUN BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define TXSTATUS_FIFO_EMPTY BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define DICR_MASTER BIT15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DICR_TRANSMIT BIT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define DICR_RECEIVE BIT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define usc_EnableDmaInterrupts(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define usc_DisableDmaInterrupts(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define usc_EnableStatusIrqs(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define usc_DisablestatusIrqs(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Transmit status Bits in Transmit Control status Register (TCSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DISABLE_UNCONDITIONAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DISABLE_END_OF_FRAME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define ENABLE_UNCONDITIONAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define ENABLE_AUTO_CTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define ENABLE_AUTO_DCD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define usc_EnableTransmitter(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define usc_EnableReceiver(a,b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void usc_start_receiver( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void usc_stop_receiver( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static void usc_start_transmitter( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void usc_stop_transmitter( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static void usc_set_txidle( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static void usc_load_txfifo( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void usc_enable_loopback( struct mgsl_struct *info, int enable );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void usc_get_serial_signals( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void usc_set_serial_signals( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void usc_reset( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void usc_set_sync_mode( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void usc_set_sdlc_mode( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static void usc_set_async_mode( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void usc_loopback_frame( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void mgsl_tx_timeout(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void usc_loopmode_insert_request( struct mgsl_struct * info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int usc_loopmode_active( struct mgsl_struct * info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void usc_loopmode_send_done( struct mgsl_struct * info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define dev_to_port(D) (dev_to_hdlc(D)->priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static void hdlcdev_tx_done(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int hdlcdev_init(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void hdlcdev_exit(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * Defines a BUS descriptor value for the PCI adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * local bus address ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) (0x00400020 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ((WrHold) << 30) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ((WrDly) << 28) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ((RdDly) << 26) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ((Nwdd) << 20) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ((Nwad) << 15) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ((Nxda) << 13) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ((Nrdd) << 11) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ((Nrad) << 6) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * Adapter diagnostic routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static bool mgsl_register_test( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static bool mgsl_irq_test( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static bool mgsl_dma_test( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static bool mgsl_memory_test( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int mgsl_adapter_test( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * device and resource management routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int mgsl_claim_resources(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void mgsl_release_resources(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void mgsl_add_device(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static struct mgsl_struct* mgsl_allocate_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * DMA buffer manupulation functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static bool mgsl_get_rx_frame( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int num_free_tx_dma_buffers(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * DMA and Shared Memory buffer allocation and formatting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void mgsl_free_dma_buffers(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Bottom half interrupt handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void mgsl_bh_handler(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void mgsl_bh_receive(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void mgsl_bh_transmit(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void mgsl_bh_status(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * Interrupt handler routines and dispatch table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void mgsl_isr_null( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static void mgsl_isr_transmit_data( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void mgsl_isr_receive_data( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void mgsl_isr_receive_status( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void mgsl_isr_transmit_status( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static void mgsl_isr_io_pin( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static void mgsl_isr_misc( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void mgsl_isr_receive_dma( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) typedef void (*isr_dispatch_func)(struct mgsl_struct *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static isr_dispatch_func UscIsrTable[7] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mgsl_isr_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mgsl_isr_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mgsl_isr_io_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mgsl_isr_transmit_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mgsl_isr_transmit_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mgsl_isr_receive_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mgsl_isr_receive_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * ioctl call handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int tiocmget(struct tty_struct *tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int tiocmset(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned int set, unsigned int clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) __user *user_icount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int mgsl_txenable(struct mgsl_struct * info, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int mgsl_txabort(struct mgsl_struct * info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int mgsl_rxenable(struct mgsl_struct * info, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int mgsl_loopmode_send_done( struct mgsl_struct * info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* set non-zero on successful registration with PCI subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static bool pci_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * Global linked list of SyncLink devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct mgsl_struct *mgsl_device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int mgsl_device_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Set this param to non-zero to load eax with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * .text section address and breakpoint on module load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * This is useful for use with gdb and add-symbol-file command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static bool break_on_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Driver major number, defaults to zero to get auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * assigned major number. May be forced as module parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int ttymajor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * Array of user specified options for ISA adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int io[MAX_ISA_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int irq[MAX_ISA_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int dma[MAX_ISA_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int debug_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int maxframe[MAX_TOTAL_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int txdmabufs[MAX_TOTAL_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int txholdbufs[MAX_TOTAL_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) module_param(break_on_load, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) module_param(ttymajor, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) module_param_hw_array(io, int, ioport, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) module_param_hw_array(irq, int, irq, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) module_param_hw_array(dma, int, dma, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) module_param(debug_level, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) module_param_array(maxframe, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) module_param_array(txdmabufs, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) module_param_array(txholdbufs, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static char *driver_name = "SyncLink serial driver";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static char *driver_version = "$Revision: 4.38 $";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int synclink_init_one (struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) const struct pci_device_id *ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static void synclink_remove_one (struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const struct pci_device_id synclink_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { 0, }, /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static struct pci_driver synclink_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "synclink",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .id_table = synclink_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .probe = synclink_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .remove = synclink_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static struct tty_driver *serial_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* number of characters left in xmit buffer before we ask for more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define WAKEUP_CHARS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static void mgsl_change_params(struct mgsl_struct *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * 1st function defined in .text section. Calling this function in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * init_module() followed by a breakpoint allows a remote debugger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * (gdb) to get the .text address for the add-symbol-file command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * This allows remote debugging of dynamically loadable modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static void* mgsl_get_text_ptr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return mgsl_get_text_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static inline int mgsl_paranoia_check(struct mgsl_struct *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) char *name, const char *routine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #ifdef MGSL_PARANOIA_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const char *badmagic =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "Warning: bad magic number for mgsl struct (%s) in %s\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const char *badinfo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "Warning: null mgsl_struct for (%s) in %s\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) printk(badinfo, name, routine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (info->magic != MGSL_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) printk(badmagic, name, routine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * line discipline callback wrappers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * The wrappers maintain line discipline references
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * while calling into the line discipline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * ldisc_receive_buf - pass receive data to line discipline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static void ldisc_receive_buf(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) const __u8 *data, char *flags, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct tty_ldisc *ld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ld = tty_ldisc_ref(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ld) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (ld->ops->receive_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ld->ops->receive_buf(tty, data, flags, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) tty_ldisc_deref(ld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* mgsl_stop() throttle (stop) transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static void mgsl_stop(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) printk("mgsl_stop(%s)\n",info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (info->tx_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } /* end of mgsl_stop() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* mgsl_start() release (start) transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void mgsl_start(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) printk("mgsl_start(%s)\n",info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!info->tx_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } /* end of mgsl_start() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * Bottom half work queue access functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* mgsl_bh_action() Return next bottom half action to perform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * Return Value: BH action code or 0 if nothing to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static int mgsl_bh_action(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (info->pending_bh & BH_RECEIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) info->pending_bh &= ~BH_RECEIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) rc = BH_RECEIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) } else if (info->pending_bh & BH_TRANSMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) info->pending_bh &= ~BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) rc = BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) } else if (info->pending_bh & BH_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) info->pending_bh &= ~BH_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rc = BH_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Mark BH routine as complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) info->bh_running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) info->bh_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * Perform bottom half processing of work items queued by ISR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static void mgsl_bh_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct mgsl_struct *info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) container_of(work, struct mgsl_struct, task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) info->bh_running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) while((action = mgsl_bh_action(info)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Process work item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) __FILE__,__LINE__,action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) switch (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case BH_RECEIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mgsl_bh_receive(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case BH_TRANSMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) mgsl_bh_transmit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case BH_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mgsl_bh_status(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* unknown work item ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) printk("Unknown work item ID=%08X!\n", action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static void mgsl_bh_receive(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) bool (*get_rx_frame)(struct mgsl_struct *info) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) printk( "%s(%d):mgsl_bh_receive(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (info->rx_rcc_underrun) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) } while(get_rx_frame(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void mgsl_bh_transmit(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct tty_struct *tty = info->port.tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* if transmitter idle and loopmode_send_done_requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * then start echoing RxD to TxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if ( !info->tx_active && info->loopmode_send_done_requested )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) usc_loopmode_send_done( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static void mgsl_bh_status(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) printk( "%s(%d):mgsl_bh_status() entry on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) info->ri_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) info->dsr_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) info->dcd_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) info->cts_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* mgsl_isr_receive_status()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * Service a receive status interrupt. The type of status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * interrupt is indicated by the state of the RCSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * This is only used for HDLC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static void mgsl_isr_receive_status( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u16 status = usc_InReg( info, RCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) __FILE__,__LINE__,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if ( (status & RXSTATUS_ABORT_RECEIVED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) info->loopmode_insert_requested &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) usc_loopmode_active(info) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ++info->icount.rxabort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) info->loopmode_insert_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* clear CMR:13 to start echoing RxD to TxD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) info->cmr_value &= ~BIT13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) usc_OutReg(info, CMR, info->cmr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* disable received abort irq (no longer required) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) usc_OutReg(info, RICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (status & RXSTATUS_EXITED_HUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) info->icount.exithunt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (status & RXSTATUS_IDLE_RECEIVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) info->icount.rxidle++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) wake_up_interruptible(&info->event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (status & RXSTATUS_OVERRUN){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) info->icount.rxover++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) usc_process_rxoverrun_sync( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) usc_UnlatchRxstatusBits( info, status );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } /* end of mgsl_isr_receive_status() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* mgsl_isr_transmit_status()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Service a transmit status interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * HDLC mode :end of transmit frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Async mode:all data is sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * transmit status is indicated by bits in the TCSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static void mgsl_isr_transmit_status( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u16 status = usc_InReg( info, TCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) __FILE__,__LINE__,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) usc_UnlatchTxstatusBits( info, status );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* finished sending HDLC abort. This may leave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* the TxFifo with data from the aborted frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* so purge the TxFifo. Also shutdown the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* channel in case there is data remaining in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* the DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) usc_DmaCmd( info, DmaCmd_ResetTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if ( status & TXSTATUS_EOF_SENT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) info->icount.txok++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) else if ( status & TXSTATUS_UNDERRUN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) info->icount.txunder++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) else if ( status & TXSTATUS_ABORT_SENT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) info->icount.txabort++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) info->icount.txunder++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) info->tx_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) del_timer(&info->tx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if ( info->drop_rts_on_tx_done ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) usc_get_serial_signals( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if ( info->serial_signals & SerialSignal_RTS ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) info->serial_signals &= ~SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) usc_set_serial_signals( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) info->drop_rts_on_tx_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hdlcdev_tx_done(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (info->port.tty->stopped || info->port.tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) info->pending_bh |= BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) } /* end of mgsl_isr_transmit_status() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* mgsl_isr_io_pin()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Service an Input/Output pin interrupt. The type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * interrupt is indicated by bits in the MISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static void mgsl_isr_io_pin( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct mgsl_icount *icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u16 status = usc_InReg( info, MISR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) __FILE__,__LINE__,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) usc_ClearIrqPendingBits( info, IO_PIN );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) usc_UnlatchIostatusBits( info, status );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) icount = &info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* update input line counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (status & MISCSTATUS_RI_LATCHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) usc_DisablestatusIrqs(info,SICR_RI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) icount->rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if ( status & MISCSTATUS_RI )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) info->input_signal_events.ri_up++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) info->input_signal_events.ri_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (status & MISCSTATUS_DSR_LATCHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) usc_DisablestatusIrqs(info,SICR_DSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) icount->dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if ( status & MISCSTATUS_DSR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) info->input_signal_events.dsr_up++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) info->input_signal_events.dsr_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (status & MISCSTATUS_DCD_LATCHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) usc_DisablestatusIrqs(info,SICR_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) icount->dcd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (status & MISCSTATUS_DCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) info->input_signal_events.dcd_up++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) info->input_signal_events.dcd_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (info->netcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (status & MISCSTATUS_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) netif_carrier_on(info->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) netif_carrier_off(info->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (status & MISCSTATUS_CTS_LATCHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) usc_DisablestatusIrqs(info,SICR_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) icount->cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if ( status & MISCSTATUS_CTS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) info->input_signal_events.cts_up++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) info->input_signal_events.cts_down++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) wake_up_interruptible(&info->status_event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) wake_up_interruptible(&info->event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (tty_port_check_carrier(&info->port) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) (status & MISCSTATUS_DCD_LATCHED) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) printk("%s CD now %s...", info->device_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) (status & MISCSTATUS_DCD) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (status & MISCSTATUS_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) wake_up_interruptible(&info->port.open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) printk("doing serial hangup...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) tty_hangup(info->port.tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (tty_port_cts_enabled(&info->port) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) (status & MISCSTATUS_CTS_LATCHED) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (info->port.tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (status & MISCSTATUS_CTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) printk("CTS tx start...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) info->port.tty->hw_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) info->pending_bh |= BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!(status & MISCSTATUS_CTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) printk("CTS tx stop...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) info->port.tty->hw_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) info->pending_bh |= BH_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* for diagnostics set IRQ flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if ( status & MISCSTATUS_TXC_LATCHED ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) usc_OutReg( info, SICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) info->irq_occurred = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) } /* end of mgsl_isr_io_pin() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* mgsl_isr_transmit_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * Service a transmit data interrupt (async mode only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static void mgsl_isr_transmit_data( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) __FILE__,__LINE__,info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (info->port.tty->stopped || info->port.tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if ( info->xmit_cnt )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) usc_load_txfifo( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) info->tx_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (info->xmit_cnt < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) info->pending_bh |= BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) } /* end of mgsl_isr_transmit_data() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* mgsl_isr_receive_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * Service a receive data interrupt. This occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * when operating in asynchronous interrupt transfer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * The receive data FIFO is flushed to the receive data buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static void mgsl_isr_receive_data( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int Fifocount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) int work = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) unsigned char DataByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct mgsl_icount *icount = &info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) printk("%s(%d):mgsl_isr_receive_data\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) __FILE__,__LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) usc_ClearIrqPendingBits( info, RECEIVE_DATA );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* select FIFO status for RICR readback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* clear the Wordstatus bit so that status readback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* only reflects the status of this byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* flush the receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* read one byte from RxFIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) DataByte = inb( info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* get the status of the received byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) status = usc_InReg(info, RCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) icount->rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) printk("rxerr=%04X\n",status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* update error statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if ( status & RXSTATUS_BREAK_RECEIVED ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) icount->brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) } else if (status & RXSTATUS_PARITY_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) icount->parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) else if (status & RXSTATUS_FRAMING_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) icount->frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) else if (status & RXSTATUS_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* must issue purge fifo cmd before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* 16C32 accepts more receive chars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) usc_RTCmd(info,RTCmd_PurgeRxFifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) icount->overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* discard char if tty control flags say so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (status & info->ignore_status_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) status &= info->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (status & RXSTATUS_BREAK_RECEIVED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (info->port.flags & ASYNC_SAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) do_SAK(info->port.tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) } else if (status & RXSTATUS_PARITY_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) else if (status & RXSTATUS_FRAMING_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) } /* end of if (error) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) tty_insert_flip_char(&info->port, DataByte, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (status & RXSTATUS_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Overrun is special, since it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * reported immediately, and doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * affect the current character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if ( debug_level >= DEBUG_LEVEL_ISR ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) __FILE__,__LINE__,icount->rx,icount->brk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) icount->parity,icount->frame,icount->overrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if(work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) tty_flip_buffer_push(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* mgsl_isr_misc()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * Service a miscellaneous interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * Arguments: info pointer to device extension (instance data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static void mgsl_isr_misc( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) u16 status = usc_InReg( info, MISR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) printk("%s(%d):mgsl_isr_misc status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) __FILE__,__LINE__,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if ((status & MISCSTATUS_RCC_UNDERRUN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) (info->params.mode == MGSL_MODE_HDLC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* turn off receiver and rx DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) usc_DmaCmd(info, DmaCmd_ResetRxChannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* schedule BH handler to restart receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) info->pending_bh |= BH_RECEIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) info->rx_rcc_underrun = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) usc_ClearIrqPendingBits( info, MISC );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) usc_UnlatchMiscstatusBits( info, status );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) } /* end of mgsl_isr_misc() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* mgsl_isr_null()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * Services undefined interrupt vectors from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * USC. (hence this function SHOULD never be called)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * Arguments: info pointer to device extension (instance data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static void mgsl_isr_null( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) } /* end of mgsl_isr_null() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* mgsl_isr_receive_dma()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * Service a receive DMA channel interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * For this driver there are two sources of receive DMA interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * as identified in the Receive DMA mode Register (RDMR):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * BIT3 EOA/EOL End of List, all receive buffers in receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * buffer list have been filled (no more free buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * available). The DMA controller has shut down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) * BIT2 EOB End of Buffer. This interrupt occurs when a receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * DMA buffer is terminated in response to completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * of a good frame or a frame with errors. The status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * of the frame is stored in the buffer entry in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * list of receive buffer entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static void mgsl_isr_receive_dma( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* clear interrupt pending and IUS bit for Rx DMA IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* Read the receive DMA status to identify interrupt type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* This also clears the status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) status = usc_InDmaReg( info, RDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) __FILE__,__LINE__,info->device_name,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) info->pending_bh |= BH_RECEIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if ( status & BIT3 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) info->rx_overflow = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) info->icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) } /* end of mgsl_isr_receive_dma() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* mgsl_isr_transmit_dma()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * This function services a transmit DMA channel interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * For this driver there is one source of transmit DMA interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * as identified in the Transmit DMA Mode Register (TDMR):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * BIT2 EOB End of Buffer. This interrupt occurs when a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * transmit DMA buffer has been emptied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * The driver maintains enough transmit DMA buffers to hold at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * one max frame size transmit frame. When operating in a buffered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * transmit mode, there may be enough transmit DMA buffers to hold at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * least two or more max frame size frames. On an EOB condition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * determine if there are any queued transmit buffers and copy into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * transmit DMA buffers if we have room.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* clear interrupt pending and IUS bit for Tx DMA IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* Read the transmit DMA status to identify interrupt type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* This also clears the status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) status = usc_InDmaReg( info, TDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) __FILE__,__LINE__,info->device_name,status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if ( status & BIT2 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) --info->tx_dma_buffers_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* if there are transmit frames queued,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * try to load the next one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if ( load_next_tx_holding_buffer(info) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* if call returns non-zero value, we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * at least one free tx holding buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) info->pending_bh |= BH_TRANSMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } /* end of mgsl_isr_transmit_dma() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* mgsl_interrupt()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * Interrupt service routine entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * irq interrupt number that caused interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * dev_id device ID supplied during interrupt registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct mgsl_struct *info = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) u16 UscVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) u16 DmaVector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) __FILE__, __LINE__, info->irq_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) spin_lock(&info->irq_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* Read the interrupt vectors from hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) UscVector = usc_InReg(info, IVR) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) DmaVector = usc_InDmaReg(info, DIVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if ( !UscVector && !DmaVector )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* Dispatch interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if ( UscVector )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) (*UscIsrTable[UscVector])(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) mgsl_isr_transmit_dma(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) mgsl_isr_receive_dma(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if ( info->isr_overflow ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) __FILE__, __LINE__, info->device_name, info->irq_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) usc_DisableMasterIrqBit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) usc_DisableDmaInterrupts(info,DICR_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Request bottom half processing if there's something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * for it to do and the bh is not already running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) printk("%s(%d):%s queueing bh task.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) schedule_work(&info->task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) info->bh_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) spin_unlock(&info->irq_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if ( debug_level >= DEBUG_LEVEL_ISR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) __FILE__, __LINE__, info->irq_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) } /* end of mgsl_interrupt() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* startup()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * Initialize and start device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static int startup(struct mgsl_struct * info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (tty_port_initialized(&info->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (!info->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* allocate a page of memory for a transmit buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (!info->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) info->pending_bh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) memset(&info->icount, 0, sizeof(info->icount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) timer_setup(&info->tx_timer, mgsl_tx_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* Allocate and claim adapter resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) retval = mgsl_claim_resources(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* perform existence check and diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if ( !retval )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) retval = mgsl_adapter_test(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if ( retval ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (capable(CAP_SYS_ADMIN) && info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) set_bit(TTY_IO_ERROR, &info->port.tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) mgsl_release_resources(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* program hardware for current parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mgsl_change_params(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) tty_port_set_initialized(&info->port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } /* end of startup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /* shutdown()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static void shutdown(struct mgsl_struct * info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (!tty_port_initialized(&info->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) printk("%s(%d):mgsl_shutdown(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* clear status wait queue because status changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* can't happen after shutting down the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) wake_up_interruptible(&info->status_event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) wake_up_interruptible(&info->event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) del_timer_sync(&info->tx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (info->xmit_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) free_page((unsigned long) info->xmit_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) info->xmit_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) usc_DisableMasterIrqBit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) usc_stop_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* Disable DMAEN (Port 7, Bit 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* This disconnects the DMA request signal from the ISA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* on the ISA adapter. This has no effect for the PCI adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* Disable INTEN (Port 6, Bit12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* This disconnects the IRQ request signal to the ISA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* on the ISA adapter. This has no effect for the PCI adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) mgsl_release_resources(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) set_bit(TTY_IO_ERROR, &info->port.tty->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) tty_port_set_initialized(&info->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) } /* end of shutdown() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static void mgsl_program_hw(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) usc_stop_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) info->params.mode == MGSL_MODE_RAW ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) usc_set_sync_mode(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) usc_set_async_mode(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) info->dcd_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) info->cts_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) info->ri_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) info->dsr_chkcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) usc_EnableInterrupts(info, IO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* Reconfigure adapter based on new parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static void mgsl_change_params(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) unsigned cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) int bits_per_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (!info->port.tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) printk("%s(%d):mgsl_change_params(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) cflag = info->port.tty->termios.c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* if B0 rate (hangup) specified then negate RTS and DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* otherwise assert RTS and DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (cflag & CBAUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) case CS5: info->params.data_bits = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) case CS6: info->params.data_bits = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) case CS7: info->params.data_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case CS8: info->params.data_bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /* Never happens, but GCC is too dumb to figure it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) default: info->params.data_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) info->params.stop_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) info->params.stop_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) info->params.parity = ASYNC_PARITY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) info->params.parity = ASYNC_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) info->params.parity = ASYNC_PARITY_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #ifdef CMSPAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (cflag & CMSPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) info->params.parity = ASYNC_PARITY_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /* calculate number of jiffies to transmit a full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * FIFO (32 bytes) at specified data rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) bits_per_char = info->params.data_bits +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) info->params.stop_bits + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* if port data rate is set to 460800 or less then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * allow tty settings to override, otherwise keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * current data rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (info->params.data_rate <= 460800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) info->params.data_rate = tty_get_baud_rate(info->port.tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if ( info->params.data_rate ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) info->timeout = (32*HZ*bits_per_char) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) info->params.data_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) info->timeout += HZ/50; /* Add .02 seconds of slop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* process tty input control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) info->read_status_mask = RXSTATUS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (I_INPCK(info->port.tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (I_IGNPAR(info->port.tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (I_IGNBRK(info->port.tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* If ignoring parity and break indicators, ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * overruns too. (For real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (I_IGNPAR(info->port.tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) info->ignore_status_mask |= RXSTATUS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) mgsl_program_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) } /* end of mgsl_change_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /* mgsl_put_char()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * Add a character to the transmit buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) * Arguments: tty pointer to tty information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * ch character to add to transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (debug_level >= DEBUG_LEVEL_INFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) __FILE__, __LINE__, ch, info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (!info->xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) spin_lock_irqsave(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) info->xmit_buf[info->xmit_head++] = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) info->xmit_head &= SERIAL_XMIT_SIZE-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) info->xmit_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) spin_unlock_irqrestore(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) } /* end of mgsl_put_char() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* mgsl_flush_chars()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * Enable transmitter so remaining characters in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * transmit buffer are sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * Arguments: tty pointer to tty information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static void mgsl_flush_chars(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) __FILE__,__LINE__,info->device_name,info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) !info->xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) __FILE__,__LINE__,info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (!info->tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if ( (info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* operating in synchronous (frame oriented) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* copy data from circular xmit_buf to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* transmit DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) mgsl_load_tx_dma_buffer(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) info->xmit_buf,info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) } /* end of mgsl_flush_chars() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* mgsl_write()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) * Send a block of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * tty pointer to tty information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * buf pointer to buffer containing send data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * count size of send data in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * Return Value: number of characters written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int mgsl_write(struct tty_struct * tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) const unsigned char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) int c, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) printk( "%s(%d):mgsl_write(%s) count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) __FILE__,__LINE__,info->device_name,count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (!info->xmit_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if ( info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* operating in synchronous (frame oriented) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (info->tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if ( info->params.mode == MGSL_MODE_HDLC ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /* transmitter is actively sending data -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * if we have multiple transmit dma and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * holding buffers, attempt to queue this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * frame for transmission at a later time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* no tx holding buffers available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* queue transmit frame request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) save_tx_buffer_request(info,buf,count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* if we have sufficient tx dma buffers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) * load the next buffered tx request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) load_next_tx_holding_buffer(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /* if operating in HDLC LoopMode and the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* has yet to be inserted into the loop, we can't */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /* transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) !usc_loopmode_active(info) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if ( info->xmit_cnt ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* Send accumulated from send_char() calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* as frame and wait before accepting more data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* copy data from circular xmit_buf to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* transmit DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) mgsl_load_tx_dma_buffer(info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) info->xmit_buf,info->xmit_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ret = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) info->xmit_cnt = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) mgsl_load_tx_dma_buffer(info,buf,count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) c = min_t(int, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) SERIAL_XMIT_SIZE - info->xmit_head));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (c <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) memcpy(info->xmit_buf + info->xmit_head, buf, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) info->xmit_head = ((info->xmit_head + c) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) (SERIAL_XMIT_SIZE-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) info->xmit_cnt += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) buf += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) count -= c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ret += c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (!info->tx_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) printk( "%s(%d):mgsl_write(%s) returning=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) __FILE__,__LINE__,info->device_name,ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) } /* end of mgsl_write() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* mgsl_write_room()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) * Return the count of free bytes in transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static int mgsl_write_room(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) printk("%s(%d):mgsl_write_room(%s)=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) __FILE__,__LINE__, info->device_name,ret );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if ( info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /* operating in synchronous (frame oriented) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if ( info->tx_active )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return HDLC_MAX_FRAME_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) } /* end of mgsl_write_room() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* mgsl_chars_in_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) * Return the count of bytes in transmit buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static int mgsl_chars_in_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) __FILE__,__LINE__, info->device_name,info->xmit_cnt );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if ( info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* operating in synchronous (frame oriented) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) if ( info->tx_active )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) return info->max_frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return info->xmit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) } /* end of mgsl_chars_in_buffer() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* mgsl_flush_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * Discard all data in the send buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) static void mgsl_flush_buffer(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) del_timer(&info->tx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) tty_wakeup(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /* mgsl_send_xchar()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * Send a high-priority XON/XOFF character
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) * ch character to send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static void mgsl_send_xchar(struct tty_struct *tty, char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) __FILE__,__LINE__, info->device_name, ch );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) info->x_char = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /* Make sure transmit interrupts are on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (!info->tx_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) } /* end of mgsl_send_xchar() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* mgsl_throttle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * Signal remote device to throttle send data (our receive data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) static void mgsl_throttle(struct tty_struct * tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) printk("%s(%d):mgsl_throttle(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) if (I_IXOFF(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) mgsl_send_xchar(tty, STOP_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) info->serial_signals &= ~SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) } /* end of mgsl_throttle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* mgsl_unthrottle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * Signal remote device to stop throttling send data (our receive data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static void mgsl_unthrottle(struct tty_struct * tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) printk("%s(%d):mgsl_unthrottle(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) if (I_IXOFF(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (info->x_char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) info->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) mgsl_send_xchar(tty, START_CHAR(tty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) if (C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) info->serial_signals |= SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) } /* end of mgsl_unthrottle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) /* mgsl_get_stats()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) * get the current serial parameters information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) * user_icount pointer to buffer to hold returned stats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) printk("%s(%d):mgsl_get_params(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) __FILE__,__LINE__, info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) if (!user_icount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) memset(&info->icount, 0, sizeof(info->icount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) } /* end of mgsl_get_stats() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* mgsl_get_params()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) * get the current serial parameters information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) * user_params pointer to buffer to hold returned params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) printk("%s(%d):mgsl_get_params(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) __FILE__,__LINE__, info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) } /* end of mgsl_get_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* mgsl_set_params()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * set the serial parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * new_params user buffer containing new serial params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) MGSL_PARAMS tmp_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) mgsl_change_params(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) } /* end of mgsl_set_params() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* mgsl_get_txidle()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) * get the current transmit idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) * idle_mode pointer to buffer to hold returned idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) __FILE__,__LINE__, info->device_name, info->idle_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) } /* end of mgsl_get_txidle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* mgsl_set_txidle() service ioctl to set transmit idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) * idle_mode new idle mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) info->device_name, idle_mode );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) info->idle_mode = idle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) usc_set_txidle( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) } /* end of mgsl_set_txidle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* mgsl_txenable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) * enable or disable the transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) * enable 1 = enable, 0 = disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static int mgsl_txenable(struct mgsl_struct * info, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) info->device_name, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if ( enable ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if ( !info->tx_enabled ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /*--------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) * if HDLC/SDLC Loop mode, attempt to insert the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) * station in the 'loop' by setting CMR:13. Upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) * receipt of the next GoAhead (RxAbort) sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) * the OnLoop indicator (CCSR:7) should go active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * to indicate that we are on the loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) *--------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) usc_loopmode_insert_request( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if ( info->tx_enabled )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) } /* end of mgsl_txenable() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* mgsl_txabort() abort send HDLC frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static int mgsl_txabort(struct mgsl_struct * info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) usc_loopmode_cancel_transmit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) usc_TCmd(info,TCmd_SendAbort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) } /* end of mgsl_txabort() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) /* mgsl_rxenable() enable or disable the receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) * enable 1 = enable, 0 = disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) static int mgsl_rxenable(struct mgsl_struct * info, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) info->device_name, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) if ( enable ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) if ( !info->rx_enabled )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if ( info->rx_enabled )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) usc_stop_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) } /* end of mgsl_rxenable() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /* mgsl_wait_event() wait for specified event to occur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * mask pointer to bitmask of events to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) * Return Value: 0 if successful and bit mask updated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) * of events triggerred,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) int s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) int rc=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) struct mgsl_icount cprev, cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) int events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) struct _input_signal_events oldsigs, newsigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) info->device_name, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) /* return immediately if state matches requested events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) s = info->serial_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) events = mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /* save current irq counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) cprev = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) oldsigs = info->input_signal_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /* enable hunt and idle irqs if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) u16 oldreg = usc_InReg(info,RICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) u16 newreg = oldreg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (oldreg != newreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) usc_OutReg(info, RICR, newreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) add_wait_queue(&info->event_wait_q, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (signal_pending(current)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) rc = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) /* get current irq counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) cnow = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) newsigs = info->input_signal_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) /* if no change, wait aborted for some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) if (newsigs.dsr_up == oldsigs.dsr_up &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) newsigs.dsr_down == oldsigs.dsr_down &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) newsigs.dcd_up == oldsigs.dcd_up &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) newsigs.dcd_down == oldsigs.dcd_down &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) newsigs.cts_up == oldsigs.cts_up &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) newsigs.cts_down == oldsigs.cts_down &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) newsigs.ri_up == oldsigs.ri_up &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) newsigs.ri_down == oldsigs.ri_down &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) cnow.exithunt == cprev.exithunt &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) cnow.rxidle == cprev.rxidle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) events = mask &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) if (events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) cprev = cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) oldsigs = newsigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) remove_wait_queue(&info->event_wait_q, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (!waitqueue_active(&info->event_wait_q)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* disable enable exit hunt mode/idle rcvd IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) usc_OutReg(info, RICR, usc_InReg(info,RICR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if ( rc == 0 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) PUT_USER(rc, events, mask_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) } /* end of mgsl_wait_event() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) static int modem_input_wait(struct mgsl_struct *info,int arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) struct mgsl_icount cprev, cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) /* save current irq counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) cprev = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) add_wait_queue(&info->status_event_wait_q, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (signal_pending(current)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) rc = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) /* get new irq counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) cnow = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) /* if no change, wait aborted for some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* check for change in caller specified modem input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) cprev = cnow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) remove_wait_queue(&info->status_event_wait_q, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) /* return the state of the serial control and status signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) static int tiocmget(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) unsigned int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) printk("%s(%d):%s tiocmget() value=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) __FILE__,__LINE__, info->device_name, result );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) /* set modem control signals (DTR/RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static int tiocmset(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) unsigned int set, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) printk("%s(%d):%s tiocmset(%x,%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) __FILE__,__LINE__,info->device_name, set, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) if (set & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) info->serial_signals |= SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) if (set & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) info->serial_signals |= SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) if (clear & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) info->serial_signals &= ~SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) if (clear & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) info->serial_signals &= ~SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /* mgsl_break() Set or clear transmit break condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) * Arguments: tty pointer to tty instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) * break_state -1=set break condition, 0=clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) * Return Value: error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static int mgsl_break(struct tty_struct *tty, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) printk("%s(%d):mgsl_break(%s,%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) __FILE__,__LINE__, info->device_name, break_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) } /* end of mgsl_break() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) * Return: write counters to the user passed counter struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) * NB: both 1->0 and 0->1 transitions are counted except for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) * RI where only 0->1 is counted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) static int msgl_get_icount(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) struct serial_icounter_struct *icount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) struct mgsl_icount cnow; /* kernel counter temps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) cnow = info->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) icount->cts = cnow.cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) icount->dsr = cnow.dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) icount->rng = cnow.rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) icount->dcd = cnow.dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) icount->rx = cnow.rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) icount->tx = cnow.tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) icount->frame = cnow.frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) icount->overrun = cnow.overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) icount->parity = cnow.parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) icount->brk = cnow.brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) icount->buf_overrun = cnow.buf_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) /* mgsl_ioctl() Service an IOCTL request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) * tty pointer to tty instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) * cmd IOCTL command code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) * arg command argument/context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static int mgsl_ioctl(struct tty_struct *tty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) info->device_name, cmd );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if (cmd != TIOCMIWAIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) if (tty_io_error(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) return mgsl_ioctl_common(info, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) case MGSL_IOCGPARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) return mgsl_get_params(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) case MGSL_IOCSPARAMS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) return mgsl_set_params(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) case MGSL_IOCGTXIDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) return mgsl_get_txidle(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) case MGSL_IOCSTXIDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) return mgsl_set_txidle(info,(int)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) case MGSL_IOCTXENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) return mgsl_txenable(info,(int)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) case MGSL_IOCRXENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) return mgsl_rxenable(info,(int)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) case MGSL_IOCTXABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) return mgsl_txabort(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) case MGSL_IOCGSTATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) return mgsl_get_stats(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) case MGSL_IOCWAITEVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) return mgsl_wait_event(info, argp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) case MGSL_IOCLOOPTXDONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) return mgsl_loopmode_send_done(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) /* Wait for modem input (DCD,RI,DSR,CTS) change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) case TIOCMIWAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) return modem_input_wait(info,(int)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) /* mgsl_set_termios()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) * Set new termios settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) * tty pointer to tty structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) * termios pointer to buffer to hold returned old termios
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) tty->driver->name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) mgsl_change_params(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* Handle transition to B0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) /* Handle transition away from B0 status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) info->serial_signals |= SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) if (!C_CRTSCTS(tty) || !tty_throttled(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) info->serial_signals |= SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) /* Handle turning off CRTSCTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) tty->hw_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) mgsl_start(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) } /* end of mgsl_set_termios() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) /* mgsl_close()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) * Called when port is closed. Wait for remaining data to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) * sent. Disable port and free resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) * tty pointer to open tty structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) * filp pointer to open file object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) static void mgsl_close(struct tty_struct *tty, struct file * filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) __FILE__,__LINE__, info->device_name, info->port.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) if (tty_port_close_start(&info->port, tty, filp) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) mutex_lock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (tty_port_initialized(&info->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) mgsl_wait_until_sent(tty, info->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) mgsl_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) tty_ldisc_flush(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) shutdown(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) mutex_unlock(&info->port.mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) tty_port_close_end(&info->port, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) info->port.tty = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) tty->driver->name, info->port.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) } /* end of mgsl_close() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) /* mgsl_wait_until_sent()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) * Wait until the transmitter is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) * tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) * timeout time to wait for send completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) unsigned long orig_jiffies, char_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) if (!info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) if (!tty_port_initialized(&info->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) /* Set check interval to 1/5 of estimated time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) * send a character, and make it at least 1. The check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) * interval should also be less than the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) * Note: use tight timings here to satisfy the NIST-PCTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if ( info->params.data_rate ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) char_time = info->timeout/(32 * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) if (!char_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) char_time++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) char_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) char_time = min_t(unsigned long, char_time, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) if ( info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) while (info->tx_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) msleep_interruptible(jiffies_to_msecs(char_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) if (timeout && time_after(jiffies, orig_jiffies + timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) info->tx_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) msleep_interruptible(jiffies_to_msecs(char_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (timeout && time_after(jiffies, orig_jiffies + timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) } /* end of mgsl_wait_until_sent() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /* mgsl_hangup()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) * Called by tty_hangup() when a hangup is signaled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) * This is the same as to closing all open files for the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) * Arguments: tty pointer to associated tty object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) static void mgsl_hangup(struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) struct mgsl_struct * info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) printk("%s(%d):mgsl_hangup(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) mgsl_flush_buffer(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) shutdown(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) info->port.count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) tty_port_set_active(&info->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) info->port.tty = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) wake_up_interruptible(&info->port.open_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) } /* end of mgsl_hangup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) * carrier_raised()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) * Return true if carrier is raised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) static int carrier_raised(struct tty_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) spin_lock_irqsave(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) spin_unlock_irqrestore(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) static void dtr_rts(struct tty_port *port, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) usc_set_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* block_til_ready()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) * Block the current process until the specified port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) * is ready to be opened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) * tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) * filp pointer to open file object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) static int block_til_ready(struct tty_struct *tty, struct file * filp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) DECLARE_WAITQUEUE(wait, current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) bool do_clocal = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) int dcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) struct tty_port *port = &info->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) printk("%s(%d):block_til_ready on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) __FILE__,__LINE__, tty->driver->name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) /* nonblock mode is set or port is not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) tty_port_set_active(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) if (C_CLOCAL(tty))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) do_clocal = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /* Wait for carrier detect and the line to become
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) * free (i.e., not in use by the callout). While we are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) * this loop, port->count is dropped by one, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) * mgsl_close() knows when to free things. We restore it upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) * exit, either normal or abnormal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) add_wait_queue(&port->open_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) printk("%s(%d):block_til_ready before block on %s count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) __FILE__,__LINE__, tty->driver->name, port->count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) spin_lock_irqsave(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) port->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) spin_unlock_irqrestore(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) port->blocked_open++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) if (C_BAUD(tty) && tty_port_initialized(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) tty_port_raise_dtr_rts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) retval = (port->flags & ASYNC_HUP_NOTIFY) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) -EAGAIN : -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) dcd = tty_port_carrier_raised(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) if (do_clocal || dcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) if (signal_pending(current)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) retval = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) printk("%s(%d):block_til_ready blocking on %s count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) __FILE__,__LINE__, tty->driver->name, port->count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) tty_unlock(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) tty_lock(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) remove_wait_queue(&port->open_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) /* FIXME: Racy on hangup during close wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) if (!tty_hung_up_p(filp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) port->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) port->blocked_open--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) __FILE__,__LINE__, tty->driver->name, port->count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) if (!retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) tty_port_set_active(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) } /* end of block_til_ready() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) struct mgsl_struct *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) int line = tty->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) /* verify range of specified line number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) if (line >= mgsl_device_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) printk("%s(%d):mgsl_open with invalid line #%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) __FILE__, __LINE__, line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) /* find the info structure for the specified line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) info = mgsl_device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) while (info && info->line != line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) info = info->next_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) tty->driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) return tty_port_install(&info->port, driver, tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* mgsl_open()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) * Called when a port is opened. Init and enable port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) * Perform serial-specific initialization for the tty structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) * Arguments: tty pointer to tty info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) * filp associated file pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) * Return Value: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static int mgsl_open(struct tty_struct *tty, struct file * filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) struct mgsl_struct *info = tty->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) info->port.tty = tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) __FILE__,__LINE__,tty->driver->name, info->port.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) spin_lock_irqsave(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) if (info->netcount) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) info->port.count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if (info->port.count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) /* 1st open on this device, init hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) retval = startup(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) retval = block_til_ready(tty, filp, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) printk("%s(%d):block_til_ready(%s) returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) __FILE__,__LINE__, info->device_name, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) printk("%s(%d):mgsl_open(%s) success\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) __FILE__,__LINE__, info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) if (tty->count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) info->port.tty = NULL; /* tty layer will release tty struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if(info->port.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) info->port.count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) } /* end of mgsl_open() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) * /proc fs routines....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) char stat_buf[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) info->device_name, info->io_base, info->irq_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) info->phys_memory_base, info->phys_lcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) /* output current serial signal states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) stat_buf[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) stat_buf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (info->serial_signals & SerialSignal_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) strcat(stat_buf, "|RTS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) if (info->serial_signals & SerialSignal_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) strcat(stat_buf, "|CTS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) if (info->serial_signals & SerialSignal_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) strcat(stat_buf, "|DTR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) if (info->serial_signals & SerialSignal_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) strcat(stat_buf, "|DSR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) if (info->serial_signals & SerialSignal_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) strcat(stat_buf, "|CD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) if (info->serial_signals & SerialSignal_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) strcat(stat_buf, "|RI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) if (info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) seq_printf(m, " HDLC txok:%d rxok:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) info->icount.txok, info->icount.rxok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) if (info->icount.txunder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) seq_printf(m, " txunder:%d", info->icount.txunder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) if (info->icount.txabort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) seq_printf(m, " txabort:%d", info->icount.txabort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) if (info->icount.rxshort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) seq_printf(m, " rxshort:%d", info->icount.rxshort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) if (info->icount.rxlong)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) seq_printf(m, " rxlong:%d", info->icount.rxlong);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) if (info->icount.rxover)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) seq_printf(m, " rxover:%d", info->icount.rxover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) if (info->icount.rxcrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) seq_printf(m, " ASYNC tx:%d rx:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) info->icount.tx, info->icount.rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) if (info->icount.frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) seq_printf(m, " fe:%d", info->icount.frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) if (info->icount.parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) seq_printf(m, " pe:%d", info->icount.parity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) if (info->icount.brk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) seq_printf(m, " brk:%d", info->icount.brk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (info->icount.overrun)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) seq_printf(m, " oe:%d", info->icount.overrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) /* Append serial signal status to end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) seq_printf(m, " %s\n", stat_buf+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) info->tx_active,info->bh_requested,info->bh_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) info->pending_bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) u16 Tcsr = usc_InReg( info, TCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) u16 Tdmr = usc_InDmaReg( info, TDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) u16 Ticr = usc_InReg( info, TICR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) u16 Rscr = usc_InReg( info, RCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) u16 Rdmr = usc_InDmaReg( info, RDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) u16 Ricr = usc_InReg( info, RICR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) u16 Icr = usc_InReg( info, ICR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) u16 Dccr = usc_InReg( info, DCCR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) u16 Tmr = usc_InReg( info, TMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) u16 Tccr = usc_InReg( info, TCCR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) u16 Ccar = inw( info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) /* Called to print information about devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) static int mgsl_proc_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) struct mgsl_struct *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) seq_printf(m, "synclink driver:%s\n", driver_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) info = mgsl_device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) while( info ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) line_info(m, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) info = info->next_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) /* mgsl_allocate_dma_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) * Allocate and format DMA buffers (ISA adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) * or format shared memory buffers (PCI adapter).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) * Return Value: 0 if success, otherwise error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) unsigned short BuffersPerFrame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) info->last_mem_alloc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) /* Calculate the number of DMA buffers necessary to hold the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) /* largest allowable frame size. Note: If the max frame size is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) /* not an even multiple of the DMA buffer size then we need to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) /* round the buffer count per frame up one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) if ( info->max_frame_size % DMABUFFERSIZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) BuffersPerFrame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) * The PCI adapter has 256KBytes of shared memory to use. This is 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) * PAGE_SIZE buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) * The first page is used for padding at this time so the buffer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) * does not begin at offset 0 of the PCI adapter's shared memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) * The 2nd page is used for the buffer list. A 4K buffer list can hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) * 128 DMA_BUFFER structures at 32 bytes each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) * This leaves 62 4K pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) * The next N pages are used for transmit frame(s). We reserve enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) * 4K page blocks to hold the required number of transmit dma buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) * (num_tx_dma_buffers), each of MaxFrameSize size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) * Of the remaining pages (62-N), determine how many can be used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) * receive full MaxFrameSize inbound frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) info->rx_buffer_count = 62 - info->tx_buffer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) mgsl_reset_rx_dma_buffers( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) mgsl_reset_tx_dma_buffers( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) } /* end of mgsl_allocate_dma_buffers() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) * mgsl_alloc_buffer_list_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) * Allocate a common DMA buffer for use as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) * receive and transmit buffer lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) * A buffer list is a set of buffer entries where each entry contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) * a pointer to an actual buffer and a pointer to the next buffer entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) * (plus some other info about the buffer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) * The buffer entries for a list are built to form a circular list so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) * that when the entire list has been traversed you start back at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) * beginning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) * This function allocates memory for just the buffer entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) * The links (pointer to next entry) are filled in with the physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) * address of the next entry so the adapter can navigate the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) * using bus master DMA. The pointers to the actual buffers are filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) * out later when the actual buffers are allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) * Return Value: 0 if success, otherwise error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) /* PCI adapter uses shared memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) info->buffer_list = info->memory_base + info->last_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) info->buffer_list_phys = info->last_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) info->last_mem_alloc += BUFFERLISTSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) /* We got the memory for the buffer entry lists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) /* Initialize the memory block to all zeros. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) memset( info->buffer_list, 0, BUFFERLISTSIZE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) /* Save virtual address pointers to the receive and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) /* transmit buffer lists. (Receive 1st). These pointers will */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) /* be used by the processor to access the lists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) info->tx_buffer_list += info->rx_buffer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) * Build the links for the buffer entry lists such that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) * two circular lists are built. (Transmit and Receive).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) * Note: the links are physical addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) * which are read by the adapter to determine the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) * buffer entry to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) for ( i = 0; i < info->rx_buffer_count; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) /* calculate and store physical address of this buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) info->rx_buffer_list[i].phys_entry =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) /* calculate and store physical address of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) /* next entry in cirular list of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) info->rx_buffer_list[i].link = info->buffer_list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) if ( i < info->rx_buffer_count - 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) for ( i = 0; i < info->tx_buffer_count; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) /* calculate and store physical address of this buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /* calculate and store physical address of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) /* next entry in cirular list of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) info->tx_buffer_list[i].link = info->buffer_list_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) info->rx_buffer_count * sizeof(DMABUFFERENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) if ( i < info->tx_buffer_count - 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) } /* end of mgsl_alloc_buffer_list_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) /* Free DMA buffers allocated for use as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) * receive and transmit buffer lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) * Warning:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) * The data transfer buffers associated with the buffer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) * MUST be freed before freeing the buffer list itself because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) * the buffer list contains the information necessary to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) * the individual buffers!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) info->buffer_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) info->rx_buffer_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) info->tx_buffer_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) } /* end of mgsl_free_buffer_list_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) * mgsl_alloc_frame_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) * Allocate the frame DMA buffers used by the specified buffer list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) * Each DMA buffer will be one memory page in size. This is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) * because memory can fragment enough that it may be impossible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) * contiguous pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) * BufferList pointer to list of buffer entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) * Buffercount count of buffer entries in buffer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) * Return Value: 0 if success, otherwise -ENOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) /* Allocate page sized buffers for the receive buffer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) for ( i = 0; i < Buffercount; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) BufferList[i].phys_addr = info->last_mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) info->last_mem_alloc += DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) } /* end of mgsl_alloc_frame_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) * mgsl_free_frame_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) * Free the buffers associated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) * each buffer entry of a buffer list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) * BufferList pointer to list of buffer entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) * Buffercount count of buffer entries in buffer list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) if ( BufferList ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) for ( i = 0 ; i < Buffercount ; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if ( BufferList[i].virt_addr ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) BufferList[i].virt_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) } /* end of mgsl_free_frame_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) /* mgsl_free_dma_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) * Free DMA buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) static void mgsl_free_dma_buffers( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) mgsl_free_buffer_list_memory( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) } /* end of mgsl_free_dma_buffers() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) * mgsl_alloc_intermediate_rxbuffer_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) * Allocate a buffer large enough to hold max_frame_size. This buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) * is used to pass an assembled frame to the line discipline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) * Return Value: 0 if success, otherwise -ENOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if ( info->intermediate_rxbuffer == NULL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) /* unused flag buffer to satisfy receive_buf calling interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) if (!info->flag_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) kfree(info->intermediate_rxbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) info->intermediate_rxbuffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) * mgsl_free_intermediate_rxbuffer_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) kfree(info->intermediate_rxbuffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) info->intermediate_rxbuffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) kfree(info->flag_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) info->flag_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) } /* end of mgsl_free_intermediate_rxbuffer_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) * mgsl_alloc_intermediate_txbuffer_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) * This buffer is used to load transmit frames into the adapter's dma transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) * buffers when there is sufficient space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) * Return Value: 0 if success, otherwise -ENOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) printk("%s %s(%d) allocating %d tx holding buffers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) for ( i=0; i<info->num_tx_holding_buffers; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) info->tx_holding_buffers[i].buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) kmalloc(info->max_frame_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) if (info->tx_holding_buffers[i].buffer == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) for (--i; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) kfree(info->tx_holding_buffers[i].buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) info->tx_holding_buffers[i].buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) * mgsl_free_intermediate_txbuffer_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) kfree(info->tx_holding_buffers[i].buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) info->tx_holding_buffers[i].buffer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) info->get_tx_holding_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) info->put_tx_holding_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) info->tx_holding_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) } /* end of mgsl_free_intermediate_txbuffer_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) * load_next_tx_holding_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) * attempts to load the next buffered tx request into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) * tx dma buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) * Return Value: true if next buffered tx request loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) * into adapter's tx dma buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) * false otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) bool ret = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) if ( info->tx_holding_count ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) /* determine if we have enough tx dma buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) * to accommodate the next tx frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) struct tx_holding_buffer *ptx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) &info->tx_holding_buffers[info->get_tx_holding_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) int num_free = num_free_tx_dma_buffers(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) int num_needed = ptx->buffer_size / DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) if ( ptx->buffer_size % DMABUFFERSIZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) ++num_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) if (num_needed <= num_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) info->xmit_cnt = ptx->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) --info->tx_holding_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) info->get_tx_holding_index=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) /* restart transmit timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) ret = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) * save_tx_buffer_request()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) * attempt to store transmit frame request for later transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) * Buffer pointer to buffer containing frame to load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) * BufferSize size in bytes of frame in Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) * Return Value: 1 if able to store, 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) struct tx_holding_buffer *ptx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) return 0; /* all buffers in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) ptx->buffer_size = BufferSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) memcpy( ptx->buffer, Buffer, BufferSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) ++info->tx_holding_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) info->put_tx_holding_index=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) static int mgsl_claim_resources(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) __FILE__,__LINE__,info->device_name, info->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) info->io_addr_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) info->device_name, info ) < 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) __FILE__,__LINE__,info->device_name, info->irq_level );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) info->irq_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) __FILE__,__LINE__,info->device_name, info->phys_memory_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) info->shared_mem_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) info->lcr_mem_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) info->memory_base = ioremap(info->phys_memory_base, 0x40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) if (!info->memory_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) __FILE__,__LINE__,info->device_name, info->phys_memory_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) if ( !mgsl_memory_test(info) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) __FILE__,__LINE__,info->device_name, info->phys_memory_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) if (!info->lcr_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) info->lcr_base += info->lcr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) if ( mgsl_allocate_dma_buffers(info) < 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) __FILE__,__LINE__,info->device_name, info->dma_level );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) goto errout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) errout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) mgsl_release_resources(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) } /* end of mgsl_claim_resources() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) static void mgsl_release_resources(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) printk( "%s(%d):mgsl_release_resources(%s) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) __FILE__,__LINE__,info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) if ( info->irq_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) free_irq(info->irq_level, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) info->irq_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) if ( info->dma_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) disable_dma(info->dma_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) free_dma(info->dma_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) info->dma_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) mgsl_free_dma_buffers(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) mgsl_free_intermediate_rxbuffer_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) mgsl_free_intermediate_txbuffer_memory(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) if ( info->io_addr_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) release_region(info->io_base,info->io_addr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) info->io_addr_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) if ( info->shared_mem_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) release_mem_region(info->phys_memory_base,0x40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) info->shared_mem_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) if ( info->lcr_mem_requested ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) info->lcr_mem_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) if (info->memory_base){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) iounmap(info->memory_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) info->memory_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (info->lcr_base){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) iounmap(info->lcr_base - info->lcr_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) info->lcr_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) printk( "%s(%d):mgsl_release_resources(%s) exit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) __FILE__,__LINE__,info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) } /* end of mgsl_release_resources() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) /* mgsl_add_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) * Add the specified device instance data structure to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) * global linked list of devices and increment the device count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) static void mgsl_add_device( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) info->next_device = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) info->line = mgsl_device_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) sprintf(info->device_name,"ttySL%d",info->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) if (info->line < MAX_TOTAL_DEVICES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) if (maxframe[info->line])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) info->max_frame_size = maxframe[info->line];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) if (txdmabufs[info->line]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) info->num_tx_dma_buffers = txdmabufs[info->line];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) if (info->num_tx_dma_buffers < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) info->num_tx_dma_buffers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) if (txholdbufs[info->line]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) info->num_tx_holding_buffers = txholdbufs[info->line];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) if (info->num_tx_holding_buffers < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) info->num_tx_holding_buffers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) mgsl_device_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) if ( !mgsl_device_list )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) mgsl_device_list = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) struct mgsl_struct *current_dev = mgsl_device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) while( current_dev->next_device )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) current_dev = current_dev->next_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) current_dev->next_device = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) if ( info->max_frame_size < 4096 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) info->max_frame_size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) else if ( info->max_frame_size > 65535 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) info->max_frame_size = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) info->phys_memory_base, info->phys_lcr_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) info->max_frame_size );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) hdlcdev_init(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) } /* end of mgsl_add_device() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) static const struct tty_port_operations mgsl_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) .carrier_raised = carrier_raised,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) .dtr_rts = dtr_rts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) /* mgsl_allocate_device()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) * Allocate and initialize a device instance structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) * Arguments: none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) * Return Value: pointer to mgsl_struct if success, otherwise NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) static struct mgsl_struct* mgsl_allocate_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) struct mgsl_struct *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) info = kzalloc(sizeof(struct mgsl_struct),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) printk("Error can't allocate device instance data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) tty_port_init(&info->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) info->port.ops = &mgsl_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) info->magic = MGSL_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) INIT_WORK(&info->task, mgsl_bh_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) info->max_frame_size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) info->port.close_delay = 5*HZ/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) info->port.closing_wait = 30*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) init_waitqueue_head(&info->status_event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) init_waitqueue_head(&info->event_wait_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) spin_lock_init(&info->irq_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) spin_lock_init(&info->netlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) info->idle_mode = HDLC_TXIDLE_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) info->num_tx_dma_buffers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) info->num_tx_holding_buffers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) } /* end of mgsl_allocate_device()*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) static const struct tty_operations mgsl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) .install = mgsl_install,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) .open = mgsl_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) .close = mgsl_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) .write = mgsl_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) .put_char = mgsl_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) .flush_chars = mgsl_flush_chars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) .write_room = mgsl_write_room,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) .chars_in_buffer = mgsl_chars_in_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) .flush_buffer = mgsl_flush_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) .ioctl = mgsl_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) .throttle = mgsl_throttle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) .unthrottle = mgsl_unthrottle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) .send_xchar = mgsl_send_xchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) .break_ctl = mgsl_break,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) .wait_until_sent = mgsl_wait_until_sent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) .set_termios = mgsl_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) .stop = mgsl_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) .start = mgsl_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) .hangup = mgsl_hangup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) .tiocmget = tiocmget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) .tiocmset = tiocmset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) .get_icount = msgl_get_icount,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) .proc_show = mgsl_proc_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) * perform tty device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) static int mgsl_init_tty(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) serial_driver = alloc_tty_driver(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) if (!serial_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) serial_driver->driver_name = "synclink";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) serial_driver->name = "ttySL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) serial_driver->major = ttymajor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) serial_driver->minor_start = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) serial_driver->subtype = SERIAL_TYPE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) serial_driver->init_termios = tty_std_termios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) serial_driver->init_termios.c_cflag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) B9600 | CS8 | CREAD | HUPCL | CLOCAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) serial_driver->init_termios.c_ispeed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) serial_driver->init_termios.c_ospeed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) serial_driver->flags = TTY_DRIVER_REAL_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) tty_set_operations(serial_driver, &mgsl_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) if ((rc = tty_register_driver(serial_driver)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) printk("%s(%d):Couldn't register serial driver\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) __FILE__,__LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) put_tty_driver(serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) serial_driver = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) printk("%s %s, tty major#%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) driver_name, driver_version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) serial_driver->major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) static void synclink_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) struct mgsl_struct *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) struct mgsl_struct *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) printk("Unloading %s: %s\n", driver_name, driver_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) if (serial_driver) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) rc = tty_unregister_driver(serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) printk("%s(%d) failed to unregister tty driver err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) __FILE__,__LINE__,rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) put_tty_driver(serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) info = mgsl_device_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) while(info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) hdlcdev_exit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) mgsl_release_resources(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) tmp = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) info = info->next_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) tty_port_destroy(&tmp->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) if (pci_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) pci_unregister_driver(&synclink_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) static int __init synclink_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) if (break_on_load) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) mgsl_get_text_ptr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) BREAKPOINT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) printk("%s %s\n", driver_name, driver_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) pci_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) if ((rc = mgsl_init_tty()) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) synclink_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) static void __exit synclink_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) synclink_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) module_init(synclink_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) module_exit(synclink_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) * usc_RTCmd()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) * Issue a USC Receive/Transmit command to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) * Channel Command/Address Register (CCAR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) * The command is encoded in the most significant 5 bits <15..11>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) * of the CCAR value. Bits <10..7> of the CCAR must be preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) * and Bits <6..0> must be written as zeros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) * info pointer to device information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) * Cmd command mask (use symbolic macros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) /* output command to CCAR in bits <15..11> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) /* preserve bits <10..7>, bits <6..0> must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) outw( Cmd + info->loopback_bits, info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) /* Read to flush write to CCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) inw( info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) } /* end of usc_RTCmd() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) * usc_DmaCmd()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) * Issue a DMA command to the DMA Command/Address Register (DCAR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) * info pointer to device information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) * Cmd DMA command mask (usc_DmaCmd_XX Macros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) /* write command mask to DCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) outw( Cmd + info->mbre_bit, info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) /* Read to flush write to DCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) inw( info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) } /* end of usc_DmaCmd() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) * usc_OutDmaReg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) * Write a 16-bit value to a USC DMA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) * info pointer to device info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) * RegAddr register address (number) for write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) * RegValue 16-bit value to write to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) /* Note: The DCAR is located at the adapter base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) /* Note: must preserve state of BIT8 in DCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) outw( RegAddr + info->mbre_bit, info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) outw( RegValue, info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) /* Read to flush write to DCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) inw( info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) } /* end of usc_OutDmaReg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) * usc_InDmaReg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) * Read a 16-bit value from a DMA register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) * info pointer to device info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) * RegAddr register address (number) to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) * The 16-bit value read from register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) /* Note: The DCAR is located at the adapter base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) /* Note: must preserve state of BIT8 in DCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) outw( RegAddr + info->mbre_bit, info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) return inw( info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) } /* end of usc_InDmaReg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) * usc_OutReg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) * Write a 16-bit value to a USC serial channel register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) * info pointer to device info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) * RegAddr register address (number) to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) * RegValue 16-bit value to write to register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) * None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) outw( RegValue, info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) /* Read to flush write to CCAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) inw( info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) } /* end of usc_OutReg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) * usc_InReg()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) * Reads a 16-bit value from a USC serial channel register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) * info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) * RegAddr register address (number) to read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) * Return Value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) * 16-bit value read from register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) return inw( info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) } /* end of usc_InReg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) /* usc_set_sdlc_mode()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) * Set up the adapter for SDLC DMA communications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) * Return Value: NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) static void usc_set_sdlc_mode( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) u16 RegValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) bool PreSL1660;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) * determine if the IUSC on the adapter is pre-SL1660. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) * not, take advantage of the UnderWait feature of more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) * modern chips. If an underrun occurs and this bit is set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) * the transmitter will idle the programmed idle pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) * until the driver has time to service the underrun. Otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) * the dma controller may get the cycles previously requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) * and begin transmitting queued tx data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) usc_OutReg(info,TMCR,0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) RegValue=usc_InReg(info,TMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) PreSL1660 = (RegValue == IUSC_PRE_SL1660);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) ** Channel Mode Register (CMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) ** <13> 0 0 = Transmit Disabled (initially)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) ** <12> 0 1 = Consecutive Idles share common 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) ** <3..0> 0110 Receiver Mode = HDLC/SDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) ** 1000 1110 0000 0110 = 0x8e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) RegValue = 0x8e06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) /*--------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) * ignore user options for UnderRun Actions and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) * preambles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) *--------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) /* Channel mode Register (CMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) * <15..14> 00 Tx Sub modes, Underrun Action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) * <13> 0 1 = Send Preamble before opening flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) * <12> 0 1 = Consecutive Idles share common 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) * <11..8> 0110 Transmitter mode = HDLC/SDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) * <3..0> 0110 Receiver mode = HDLC/SDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) * 0000 0110 0000 0110 = 0x0606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) if (info->params.mode == MGSL_MODE_RAW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) RegValue = 0x0001; /* Set Receive mode = external sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) * TxSubMode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) * CMR <15> 0 Don't send CRC on Tx Underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) * CMR <14> x undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) * CMR <13> 0 Send preamble before openning sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) * TxMode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) * CMR <11-8) 0100 MonoSync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) * 0x00 0100 xxxx xxxx 04xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) RegValue |= 0x0400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) RegValue = 0x0606;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) RegValue |= BIT14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) RegValue |= BIT15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) RegValue |= BIT15 | BIT14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) RegValue |= BIT13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) if ( info->params.mode == MGSL_MODE_HDLC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) RegValue |= BIT12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) if ( info->params.addr_filter != 0xff )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) /* set up receive address filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) usc_OutReg( info, RSR, info->params.addr_filter );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) RegValue |= BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) usc_OutReg( info, CMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) info->cmr_value = RegValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) /* Receiver mode Register (RMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) * <15..13> 000 encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) * <9> 0 1 = Include Receive chars in CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) * <8> 1 1 = Use Abort/PE bit as abort indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) * <7..6> 00 Even parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) * <5> 0 parity disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) * <4..2> 000 Receive Char Length = 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) * <1..0> 00 Disable Receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) * 0000 0101 0000 0000 = 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) RegValue = 0x0500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) switch ( info->params.encoding ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) RegValue |= BIT9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) RegValue |= ( BIT12 | BIT10 | BIT9 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) usc_OutReg( info, RMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) /* Set the Receive count Limit Register (RCLR) to 0xffff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) /* When an opening flag of an SDLC frame is recognized the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) /* Receive Character count (RCC) is loaded with the value in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) /* RCLR. The RCC is decremented for each received byte. The */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) /* value of RCC is stored after the closing flag of the frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) /* allowing the frame size to be computed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) usc_OutReg( info, RCLR, RCLRVALUE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) usc_RCmd( info, RCmd_SelectRicrdma_level );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) /* Receive Interrupt Control Register (RICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) * <15..8> ? RxFIFO DMA Request Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) * <7> 0 Exited Hunt IA (Interrupt Arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) * <6> 0 Idle Received IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) * <5> 0 Break/Abort IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) * <4> 0 Rx Bound IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) * <3> 1 Queued status reflects oldest 2 bytes in FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) * <2> 0 Abort/PE IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) * <1> 1 Rx Overrun IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) * <0> 0 Select TC0 value for readback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) * 0000 0000 0000 1000 = 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) /* Carry over the Exit Hunt and Idle Received bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) /* in case they have been armed by usc_ArmEvents. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) RegValue = usc_InReg( info, RICR ) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) /* Transmit mode Register (TMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) * <15..13> 000 encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) * <9> 0 1 = Tx CRC Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) * <8> 0 1 = Append CRC to end of transmit frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) * <7..6> 00 Transmit parity Even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) * <5> 0 Transmit parity Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) * <4..2> 000 Tx Char Length = 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) * <1..0> 00 Disable Transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) * 0000 0100 0000 0000 = 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) RegValue = 0x0400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) switch ( info->params.encoding ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) RegValue |= BIT9 | BIT8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) usc_OutReg( info, TMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) usc_set_txidle( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) usc_TCmd( info, TCmd_SelectTicrdma_level );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) /* Transmit Interrupt Control Register (TICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) * <15..8> ? Transmit FIFO DMA Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) * <7> 0 Present IA (Interrupt Arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * <6> 0 Idle Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) * <5> 1 Abort Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) * <4> 1 EOF/EOM Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) * <3> 0 CRC Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) * <2> 1 1 = Wait for SW Trigger to Start Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) * <1> 1 Tx Underrun IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) * <0> 0 TC0 constant on read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) * 0000 0000 0011 0110 = 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) usc_OutReg( info, TICR, 0x0736 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) ** Transmit Command/Status Register (TCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) ** <15..12> 0000 TCmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) ** <11> 0/1 UnderWait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) ** <10..08> 000 TxIdle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) ** <7> x PreSent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) ** <6> x IdleSent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) ** <5> x AbortSent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) ** <4> x EOF/EOM Sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) ** <3> x CRC Sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) ** <2> x All Sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) ** <1> x TxUnder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) ** <0> x TxEmpty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) ** 0000 0000 0000 0000 = 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) info->tcsr_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) if ( !PreSL1660 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) info->tcsr_value |= TCSR_UNDERWAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) usc_OutReg( info, TCSR, info->tcsr_value );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) /* Clock mode Control Register (CMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) * <15..14> 00 counter 1 Source = Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) * <13..12> 00 counter 0 Source = Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) * <11..10> 11 BRG1 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) * <9..8> 11 BRG0 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) * <7..6> 01 DPLL Input is BRG1 Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) * <5..3> XXX TxCLK comes from Port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) * <2..0> XXX RxCLK comes from Port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) * 0000 1111 0111 0111 = 0x0f77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) RegValue = 0x0f40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) RegValue |= 0x0003; /* RxCLK from DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) RegValue |= 0x0004; /* RxCLK from BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) RegValue |= 0x0006; /* RxCLK from TXC Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) RegValue |= 0x0007; /* RxCLK from Port1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) RegValue |= 0x0018; /* TxCLK from DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) RegValue |= 0x0020; /* TxCLK from BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) RegValue |= 0x0038; /* RxCLK from TXC Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) RegValue |= 0x0030; /* TxCLK from Port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) usc_OutReg( info, CMCR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) /* Hardware Configuration Register (HCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) * <12> 0 CVOK:0=report code violation in biphase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) * <7..6> 00 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) * <5> 0 BRG1 mode:0=continuous,1=single cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) * <4> X BRG1 Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) * <3..2> 00 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) * <1> 0 BRG0 mode:0=continuous,1=single cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) * <0> 0 BRG0 Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) RegValue = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) u32 XtalSpeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) u32 DpllDivisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) u16 Tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) XtalSpeed = 11059200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) DpllDivisor = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) RegValue |= BIT10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) DpllDivisor = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) RegValue |= BIT11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) DpllDivisor = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) /* Tc = (Xtal/Speed) - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) /* If twice the remainder of (Xtal/Speed) is greater than Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) /* then rounding up gives a more precise time constant. Instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) /* of rounding up and then subtracting 1 we just don't subtract */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) /* the one in this case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) /*--------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) * ejz: for DPLL mode, application should use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) * same clock speed as the partner system, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) * though clocking is derived from the input RxData.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) * In case the user uses a 0 for the clock speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) * default to 0xffffffff and don't try to divide by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) * zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) *--------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) if ( info->params.clock_speed )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) / info->params.clock_speed) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) Tc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) Tc = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) /* Write 16-bit Time Constant for BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) usc_OutReg( info, TC1R, Tc );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) RegValue |= BIT4; /* enable BRG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) switch ( info->params.encoding ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) case HDLC_ENCODING_NRZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) case HDLC_ENCODING_NRZB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) case HDLC_ENCODING_NRZI_MARK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) case HDLC_ENCODING_BIPHASE_MARK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) case HDLC_ENCODING_BIPHASE_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) usc_OutReg( info, HCR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) /* Channel Control/status Register (CCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) * <15> X RCC FIFO Overflow status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) * <14> X RCC FIFO Not Empty status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) * <13> 0 1 = Clear RCC FIFO (WO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) * <12> X DPLL Sync (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) * <11> X DPLL 2 Missed Clocks status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) * <10> X DPLL 1 Missed Clock status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) * <9..8> 00 DPLL Resync on rising and falling edges (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) * <7> X SDLC Loop On status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) * <6> X SDLC Loop Send status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) * <5> 1 Bypass counters for TxClk and RxClk (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) * <1..0> 00 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) * 0000 0000 0010 0000 = 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) usc_OutReg( info, CCSR, 0x1020 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) usc_OutReg( info, SICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) /* enable Master Interrupt Enable bit (MIE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) usc_EnableMasterIrqBit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) /* arm RCC underflow interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) usc_EnableInterrupts(info, MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) info->mbre_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) info->mbre_bit = BIT8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) /* DMA Control Register (DCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) * <15..14> 10 Priority mode = Alternating Tx/Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) * 01 Rx has priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) * 00 Tx has priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) * <13> 1 Enable Priority Preempt per DCR<15..14>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) * (WARNING DCR<11..10> must be 00 when this is 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) * 0 Choose activate channel per DCR<11..10>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) * <12> 0 Little Endian for Array/List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) * <11..10> 00 Both Channels can use each bus grant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) * <9..6> 0000 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) * <5> 0 7 CLK - Minimum Bus Re-request Interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) * <4> 0 1 = drive D/C and S/D pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) * <3> 1 1 = Add one wait state to all DMA cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) * <2> 0 1 = Strobe /UAS on every transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) * <1..0> 11 Addr incrementing only affects LS24 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) * 0110 0000 0000 1011 = 0x600b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) /* PCI adapter does not need DMA wait state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) usc_OutDmaReg( info, DCR, 0xa00b );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) /* Receive DMA mode Register (RDMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) * <15..14> 11 DMA mode = Linked List Buffer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) * <12> 1 Clear count of List Entry after fetching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) * <11..10> 00 Address mode = Increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) * <9> 1 Terminate Buffer on RxBound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) * <8> 0 Bus Width = 16bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) * <7..0> ? status Bits (write as 0s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) * 1111 0010 0000 0000 = 0xf200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) usc_OutDmaReg( info, RDMR, 0xf200 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) /* Transmit DMA mode Register (TDMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) * <15..14> 11 DMA mode = Linked List Buffer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) * <12> 1 Clear count of List Entry after fetching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) * <11..10> 00 Address mode = Increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) * <9> 1 Terminate Buffer on end of frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) * <8> 0 Bus Width = 16bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) * <7..0> ? status Bits (Read Only so write as 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) * 1111 0010 0000 0000 = 0xf200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) usc_OutDmaReg( info, TDMR, 0xf200 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) /* DMA Interrupt Control Register (DICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) * <15> 1 DMA Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) * <14> 0 1 = Disable IEO from USC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) * <13> 0 1 = Don't provide vector during IntAck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) * <12> 1 1 = Include status in Vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) * <10..2> 0 reserved, Must be 0s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) * <1> 0 1 = Rx DMA Interrupt Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) * <0> 0 1 = Tx DMA Interrupt Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) * 1001 0000 0000 0000 = 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) usc_OutDmaReg( info, DICR, 0x9000 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) /* Channel Control Register (CCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) * <13> 0 Trigger Tx on SW Command Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) * <12> 0 Flag Preamble Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) * <11..10> 00 Preamble Length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) * <9..8> 00 Preamble Pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) * <5> 0 Trigger Rx on SW Command Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) * <4..0> 0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) * 1000 0000 1000 0000 = 0x8080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) RegValue = 0x8080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) switch ( info->params.preamble_length ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) switch ( info->params.preamble ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) usc_OutReg( info, CCR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) * Burst/Dwell Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) * <15..8> 0x20 Maximum number of transfers per bus grant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) * <7..0> 0x00 Maximum number of clock cycles per bus grant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) /* don't limit bus occupancy on PCI adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) usc_OutDmaReg( info, BDCR, 0x0000 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) usc_stop_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) } /* end of usc_set_sdlc_mode() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) /* usc_enable_loopback()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) * Set the 16C32 for internal loopback mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) * The TxCLK and RxCLK signals are generated from the BRG0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) * the TxD is looped back to the RxD internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) * enable 1 = enable loopback, 0 = disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) static void usc_enable_loopback(struct mgsl_struct *info, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) /* blank external TXD output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) /* Clock mode Control Register (CMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) * <15..14> 00 counter 1 Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) * <13..12> 00 counter 0 Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) * <11..10> 11 BRG1 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) * <9..8> 11 BRG0 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) * <7..6> 01 DPLL Input is BRG1 Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) * <5..3> 100 TxCLK comes from BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) * <2..0> 100 RxCLK comes from BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) * 0000 1111 0110 0100 = 0x0f64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) usc_OutReg( info, CMCR, 0x0f64 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) /* Write 16-bit Time Constant for BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) /* use clock speed if available, otherwise use 8 for diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) if (info->params.clock_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) usc_OutReg(info, TC0R, (u16)8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) mode = Continuous Set Bit 0 to enable BRG0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) /* set Internal Data loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) info->loopback_bits = 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) outw( 0x0300, info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) /* enable external TXD output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) /* clear Internal Data loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) info->loopback_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) outw( 0,info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) } /* end of usc_enable_loopback() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) /* usc_enable_aux_clock()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) * Enabled the AUX clock output at the specified frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) * info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) * data_rate data rate of clock in bits per second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) * A data rate of 0 disables the AUX clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) u32 XtalSpeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) u16 Tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) if ( data_rate ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) XtalSpeed = 11059200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) /* Tc = (Xtal/Speed) - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) /* If twice the remainder of (Xtal/Speed) is greater than Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) /* then rounding up gives a more precise time constant. Instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) /* of rounding up and then subtracting 1 we just don't subtract */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) /* the one in this case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) Tc = (u16)(XtalSpeed/data_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) Tc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) /* Write 16-bit Time Constant for BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) usc_OutReg( info, TC0R, Tc );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) * Hardware Configuration Register (HCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) * Clear Bit 1, BRG0 mode = Continuous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) * Set Bit 0 to enable BRG0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) /* data rate == 0 so turn off BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) } /* end of usc_enable_aux_clock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) * usc_process_rxoverrun_sync()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) * This function processes a receive overrun by resetting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) * receive DMA buffers and issuing a Purge Rx FIFO command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) * to allow the receiver to continue receiving.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) * info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) int start_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) int end_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) int frame_start_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) bool start_of_frame_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) bool end_of_frame_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) bool reprogram_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) u32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) usc_DmaCmd( info, DmaCmd_PauseRxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) usc_RCmd( info, RCmd_EnterHuntmode );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) /* CurrentRxBuffer points to the 1st buffer of the next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) /* possibly available receive frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) frame_start_index = start_index = end_index = info->current_rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) /* Search for an unfinished string of buffers. This means */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) /* that a receive frame started (at least one buffer with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) /* count set to zero) but there is no terminiting buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) /* (status set to non-zero). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) while( !buffer_list[end_index].count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) /* Count field has been reset to zero by 16C32. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) /* This buffer is currently in use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) if ( !start_of_frame_found )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) start_of_frame_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) frame_start_index = end_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) end_of_frame_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) if ( buffer_list[end_index].status )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) /* Status field has been set by 16C32. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) /* This is the last buffer of a received frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) /* We want to leave the buffers for this frame intact. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /* Move on to next possible frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) start_of_frame_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) end_of_frame_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) /* advance to next buffer entry in linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) end_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) if ( end_index == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) end_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) if ( start_index == end_index )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) /* The entire list has been searched with all Counts == 0 and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /* all Status == 0. The receive buffers are */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) /* completely screwed, reset all receive buffers! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) mgsl_reset_rx_dma_buffers( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) frame_start_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) start_of_frame_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) reprogram_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) if ( start_of_frame_found && !end_of_frame_found )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) /* There is an unfinished string of receive DMA buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) /* as a result of the receiver overrun. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) /* Reset the buffers for the unfinished frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) /* and reprogram the receive DMA controller to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) /* at the 1st buffer of unfinished frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) start_index = frame_start_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) /* Adjust index for wrap around. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) if ( start_index == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) start_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) } while( start_index != end_index );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) reprogram_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) if ( reprogram_dma )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) /* This empties the receive FIFO and loads the RCC with RCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) /* program 16C32 with physical address of 1st DMA buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) usc_OutDmaReg( info, NRARL, (u16)phys_addr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) usc_EnableInterrupts( info, RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) usc_DmaCmd( info, DmaCmd_InitRxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) usc_EnableReceiver(info,ENABLE_AUTO_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) /* This empties the receive FIFO and loads the RCC with RCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) } /* end of usc_process_rxoverrun_sync() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) /* usc_stop_receiver()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) * Disable USC receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) static void usc_stop_receiver( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) if (debug_level >= DEBUG_LEVEL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) printk("%s(%d):usc_stop_receiver(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) /* Disable receive DMA channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) /* This also disables receive DMA channel interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) usc_DmaCmd( info, DmaCmd_ResetRxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) /* This empties the receive FIFO and loads the RCC with RCLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) info->rx_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) info->rx_overflow = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) info->rx_rcc_underrun = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) } /* end of stop_receiver() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) /* usc_start_receiver()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) * Enable the USC receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) static void usc_start_receiver( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) u32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) if (debug_level >= DEBUG_LEVEL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) printk("%s(%d):usc_start_receiver(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) mgsl_reset_rx_dma_buffers( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) usc_stop_receiver( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) if ( info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) /* DMA mode Transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) /* Program the DMA controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) /* Enable the DMA controller end of buffer interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) /* program 16C32 with physical address of 1st DMA buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) phys_addr = info->rx_buffer_list[0].phys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) usc_OutDmaReg( info, NRARL, (u16)phys_addr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) usc_EnableInterrupts( info, RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) usc_DmaCmd( info, DmaCmd_InitRxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) usc_EnableReceiver(info,ENABLE_AUTO_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) usc_EnableInterrupts(info, RECEIVE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) usc_RCmd( info, RCmd_EnterHuntmode );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) usc_OutReg( info, CCSR, 0x1020 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) info->rx_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) } /* end of usc_start_receiver() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) /* usc_start_transmitter()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) * Enable the USC transmitter and send a transmit frame if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) * one is loaded in the DMA buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) static void usc_start_transmitter( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) u32 phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) unsigned int FrameSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) if (debug_level >= DEBUG_LEVEL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) printk("%s(%d):usc_start_transmitter(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) if ( info->xmit_cnt ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) /* If auto RTS enabled and RTS is inactive, then assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /* RTS and set a flag indicating that the driver should */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) /* negate RTS when the transmission completes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) info->drop_rts_on_tx_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) usc_get_serial_signals( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) if ( !(info->serial_signals & SerialSignal_RTS) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) info->serial_signals |= SerialSignal_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) usc_set_serial_signals( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) info->drop_rts_on_tx_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) if ( info->params.mode == MGSL_MODE_ASYNC ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) if ( !info->tx_active ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) usc_EnableInterrupts(info, TRANSMIT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) usc_load_txfifo(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) /* Disable transmit DMA controller while programming. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) usc_DmaCmd( info, DmaCmd_ResetTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) /* Transmit DMA buffer is loaded, so program USC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) /* to send the frame contained in the buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) /* if operating in Raw sync mode, reset the rcc component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) * of the tx dma buffer entry, otherwise, the serial controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) * will send a closing sync char after this count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) if ( info->params.mode == MGSL_MODE_RAW )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) /* Program the Transmit Character Length Register (TCLR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) usc_OutReg( info, TCLR, (u16)FrameSize );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) /* Program the address of the 1st DMA Buffer Entry in linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) usc_OutDmaReg( info, NTARL, (u16)phys_addr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) usc_EnableInterrupts( info, TRANSMIT_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) if ( info->params.mode == MGSL_MODE_RAW &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) info->num_tx_dma_buffers > 1 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) /* When running external sync mode, attempt to 'stream' transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) /* by filling tx dma buffers as they become available. To do this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) /* we need to enable Tx DMA EOB Status interrupts : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) /* Initialize Transmit DMA Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) usc_DmaCmd( info, DmaCmd_InitTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) usc_TCmd( info, TCmd_SendFrame );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) mod_timer(&info->tx_timer, jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) msecs_to_jiffies(5000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) info->tx_active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) if ( !info->tx_enabled ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) info->tx_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) } /* end of usc_start_transmitter() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) /* usc_stop_transmitter()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) * Stops the transmitter and DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) * Arguments: info pointer to device isntance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) static void usc_stop_transmitter( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) if (debug_level >= DEBUG_LEVEL_ISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) printk("%s(%d):usc_stop_transmitter(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) __FILE__,__LINE__, info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) del_timer(&info->tx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) usc_DmaCmd( info, DmaCmd_ResetTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) info->tx_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) info->tx_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) } /* end of usc_stop_transmitter() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) /* usc_load_txfifo()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) * Fill the transmit FIFO until the FIFO is full or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) * there is no more data to load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) * Arguments: info pointer to device extension (instance data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) static void usc_load_txfifo( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) int Fifocount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) u8 TwoBytes[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) if ( !info->xmit_cnt && !info->x_char )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) /* Select transmit FIFO status readback in TICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) /* load the Transmit FIFO until FIFOs full or all data sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) /* there is more space in the transmit FIFO and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) /* there is more data in transmit buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) /* write a 16-bit word from transmit buffer to 16C32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) info->xmit_cnt -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) info->icount.tx += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) /* only 1 byte left to transmit or 1 FIFO slot left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) if (info->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) /* transmit pending high priority char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) outw( info->x_char,info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) info->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) info->xmit_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) info->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) } /* end of usc_load_txfifo() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) /* usc_reset()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) * Reset the adapter to a known state and prepare it for further use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) static void usc_reset( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) u32 readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) /* Set BIT30 of Misc Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) /* (Local Control Register 0x50) to force reset of USC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) info->misc_ctrl_value |= BIT30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) *MiscCtrl = info->misc_ctrl_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) * Force at least 170ns delay before clearing reset bit. Each read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) * LCR takes at least 30ns so 10 times for 300ns to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) for(i=0;i<10;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) readval = *MiscCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) info->misc_ctrl_value &= ~BIT30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) *MiscCtrl = info->misc_ctrl_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) *LCR0BRDR = BUS_DESCRIPTOR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) 1, // Write Strobe Hold (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) 2, // Write Strobe Delay (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) 2, // Read Strobe Delay (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) 0, // NWDD (Write data-data) (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) 4, // NWAD (Write Addr-data) (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) 0, // NXDA (Read/Write Data-Addr) (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) 0, // NRDD (Read Data-Data) (0-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) 5 // NRAD (Read Addr-Data) (0-31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) info->mbre_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) info->loopback_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) info->usc_idle_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) * Program the Bus Configuration Register (BCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) * <15> 0 Don't use separate address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) * <14..6> 0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) * <5..4> 00 IAckmode = Default, don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) * <3> 1 Bus Request Totem Pole output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) * <2> 1 Use 16 Bit data bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) * <1> 0 IRQ Totem Pole output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) * <0> 0 Don't Shift Right Addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) * 0000 0000 0000 1100 = 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) * By writing to io_base + SDPIN the Wait/Ack pin is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) * programmed to work as a Wait pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) outw( 0x000c,info->io_base + SDPIN );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) outw( 0,info->io_base );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) outw( 0,info->io_base + CCAR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) /* select little endian byte ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) usc_RTCmd( info, RTCmd_SelectLittleEndian );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) /* Port Control Register (PCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) * <3..2> 01 Port 1 is Input (Dedicated RxC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) * <1..0> 01 Port 0 is Input (Dedicated TxC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) * 1111 0000 1111 0101 = 0xf0f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) usc_OutReg( info, PCR, 0xf0f5 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) * Input/Output Control Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) * <15..14> 00 CTS is active low input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) * <13..12> 00 DCD is active low input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) * <11..10> 00 TxREQ pin is input (DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) * <9..8> 00 RxREQ pin is input (RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) * <7..6> 00 TxD is output (Transmit Data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) * <2..0> 100 RxC is Output (drive with BRG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) * 0000 0000 0000 0100 = 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) usc_OutReg( info, IOCR, 0x0004 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) } /* end of usc_reset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) /* usc_set_async_mode()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) * Program adapter for asynchronous communications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) static void usc_set_async_mode( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) u16 RegValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) /* disable interrupts while programming USC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) usc_DisableMasterIrqBit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) usc_loopback_frame( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) /* Channel mode Register (CMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) * <13..12> 00 00 = 16X Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) * <11..8> 0000 Transmitter mode = Asynchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) * <7..6> 00 reserved?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) * <5..4> 00 Rx Sub modes, 00 = 16X Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) * <3..0> 0000 Receiver mode = Asynchronous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) * 0000 0000 0000 0000 = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) RegValue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) if ( info->params.stop_bits != 1 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) RegValue |= BIT14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) usc_OutReg( info, CMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) /* Receiver mode Register (RMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) * <15..13> 000 encoding = None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) * <12..08> 00000 reserved (Sync Only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) * <7..6> 00 Even parity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) * <5> 0 parity disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) * <4..2> 000 Receive Char Length = 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) * <1..0> 00 Disable Receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) * 0000 0000 0000 0000 = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) RegValue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) if ( info->params.data_bits != 8 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) RegValue |= BIT4 | BIT3 | BIT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) if ( info->params.parity != ASYNC_PARITY_NONE ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) RegValue |= BIT5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) if ( info->params.parity != ASYNC_PARITY_ODD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) RegValue |= BIT6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) usc_OutReg( info, RMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) /* Set IRQ trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) usc_RCmd( info, RCmd_SelectRicrIntLevel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) /* Receive Interrupt Control Register (RICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) * <15..8> ? RxFIFO IRQ Request Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) * Note: For async mode the receive FIFO level must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) * to 0 to avoid the situation where the FIFO contains fewer bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) * than the trigger level and no more data is expected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) * <7> 0 Exited Hunt IA (Interrupt Arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) * <6> 0 Idle Received IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) * <5> 0 Break/Abort IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) * <4> 0 Rx Bound IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) * <3> 0 Queued status reflects oldest byte in FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) * <2> 0 Abort/PE IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) * <1> 0 Rx Overrun IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) * <0> 0 Select TC0 value for readback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) usc_OutReg( info, RICR, 0x0000 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) /* Transmit mode Register (TMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) * <15..13> 000 encoding = None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) * <12..08> 00000 reserved (Sync Only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) * <7..6> 00 Transmit parity Even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) * <5> 0 Transmit parity Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) * <4..2> 000 Tx Char Length = 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) * <1..0> 00 Disable Transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) * 0000 0000 0000 0000 = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) RegValue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) if ( info->params.data_bits != 8 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) RegValue |= BIT4 | BIT3 | BIT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) if ( info->params.parity != ASYNC_PARITY_NONE ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) RegValue |= BIT5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) if ( info->params.parity != ASYNC_PARITY_ODD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) RegValue |= BIT6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) usc_OutReg( info, TMR, RegValue );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) usc_set_txidle( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) /* Set IRQ trigger level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) usc_TCmd( info, TCmd_SelectTicrIntLevel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) /* Transmit Interrupt Control Register (TICR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) * <15..8> ? Transmit FIFO IRQ Level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) * <7> 0 Present IA (Interrupt Arm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) * <6> 1 Idle Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) * <5> 0 Abort Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) * <4> 0 EOF/EOM Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) * <3> 0 CRC Sent IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) * <2> 0 1 = Wait for SW Trigger to Start Frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) * <1> 0 Tx Underrun IA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) * <0> 0 TC0 constant on read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) * 0000 0000 0100 0000 = 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) usc_OutReg( info, TICR, 0x1f40 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) usc_enable_async_clock( info, info->params.data_rate );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) /* Channel Control/status Register (CCSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) * <15> X RCC FIFO Overflow status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) * <14> X RCC FIFO Not Empty status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) * <13> 0 1 = Clear RCC FIFO (WO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) * <12> X DPLL in Sync status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) * <11> X DPLL 2 Missed Clocks status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) * <10> X DPLL 1 Missed Clock status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) * <9..8> 00 DPLL Resync on rising and falling edges (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) * <7> X SDLC Loop On status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) * <6> X SDLC Loop Send status (RO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) * <5> 1 Bypass counters for TxClk and RxClk (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) * <1..0> 00 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) * 0000 0000 0010 0000 = 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) usc_OutReg( info, CCSR, 0x0020 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) RECEIVE_DATA + RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) RECEIVE_DATA + RECEIVE_STATUS );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) usc_EnableMasterIrqBit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) if (info->params.loopback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) info->loopback_bits = 0x300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) outw(0x0300, info->io_base + CCAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) } /* end of usc_set_async_mode() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) /* usc_loopback_frame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) * Loop back a small (2 byte) dummy SDLC frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) * Interrupts and DMA are NOT used. The purpose of this is to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) * clear any 'stale' status info left over from running in async mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) * The 16C32 shows the strange behaviour of marking the 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) * received SDLC frame with a CRC error even when there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) * CRC error. To get around this a small dummy from of 2 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) * is looped back when switching from async to sync mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) static void usc_loopback_frame( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) unsigned long oldmode = info->params.mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) info->params.mode = MGSL_MODE_HDLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) usc_DisableMasterIrqBit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) usc_set_sdlc_mode( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) usc_enable_loopback( info, 1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) /* Write 16-bit Time Constant for BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) usc_OutReg( info, TC0R, 0 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) /* Channel Control Register (CCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) * <13> 0 Trigger Tx on SW Command Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) * <12> 0 Flag Preamble Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) * <11..10> 00 Preamble Length = 8-Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) * <9..8> 01 Preamble Pattern = flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) * <5> 0 Trigger Rx on SW Command Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) * <4..0> 0 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) * 0000 0001 0000 0000 = 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) usc_OutReg( info, CCR, 0x0100 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) /* SETUP RECEIVER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) /* SETUP TRANSMITTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) /* Program the Transmit Character Length Register (TCLR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) usc_OutReg( info, TCLR, 2 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) /* unlatch Tx status bits, and start transmit channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) outw(0,info->io_base + DATAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) /* ENABLE TRANSMITTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) usc_TCmd( info, TCmd_SendFrame );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) /* WAIT FOR RECEIVE COMPLETE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) for (i=0 ; i<1000 ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) /* clear Internal Data loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) usc_enable_loopback(info, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) usc_EnableMasterIrqBit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) info->params.mode = oldmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) } /* end of usc_loopback_frame() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) /* usc_set_sync_mode() Programs the USC for SDLC communications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) * Arguments: info pointer to adapter info structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) static void usc_set_sync_mode( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) usc_loopback_frame( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) usc_set_sdlc_mode( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) usc_enable_aux_clock(info, info->params.clock_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) if (info->params.loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) usc_enable_loopback(info,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) } /* end of mgsl_set_sync_mode() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) static void usc_set_txidle( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) u16 usc_idle_mode = IDLEMODE_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) /* Map API idle mode to USC register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) switch( info->idle_mode ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) info->usc_idle_mode = usc_idle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) //usc_OutReg(info, TCSR, usc_idle_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) info->tcsr_value += usc_idle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) usc_OutReg(info, TCSR, info->tcsr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) * if SyncLink WAN adapter is running in external sync mode, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) * transmitter has been set to Monosync in order to try to mimic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) * a true raw outbound bit stream. Monosync still sends an open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) * sync char at the start/end of a frame. Try to match those sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) * patterns to the idle mode set here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) if ( info->params.mode == MGSL_MODE_RAW ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) unsigned char syncpat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) switch( info->idle_mode ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) case HDLC_TXIDLE_FLAGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) syncpat = 0x7e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) case HDLC_TXIDLE_ALT_ZEROS_ONES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) syncpat = 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) case HDLC_TXIDLE_ZEROS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) case HDLC_TXIDLE_SPACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) syncpat = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) case HDLC_TXIDLE_ONES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) case HDLC_TXIDLE_MARK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) syncpat = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) case HDLC_TXIDLE_ALT_MARK_SPACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) syncpat = 0xaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) usc_SetTransmitSyncChars(info,syncpat,syncpat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) } /* end of usc_set_txidle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) /* usc_get_serial_signals()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) * Query the adapter for the state of the V24 status (input) signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) static void usc_get_serial_signals( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) /* clear all serial signals except RTS and DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) /* Read the Misc Interrupt status Register (MISR) to get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) /* the V24 status signals. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) status = usc_InReg( info, MISR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) /* set serial signal bits to reflect MISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) if ( status & MISCSTATUS_CTS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) info->serial_signals |= SerialSignal_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) if ( status & MISCSTATUS_DCD )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) info->serial_signals |= SerialSignal_DCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) if ( status & MISCSTATUS_RI )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) info->serial_signals |= SerialSignal_RI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) if ( status & MISCSTATUS_DSR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) info->serial_signals |= SerialSignal_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) } /* end of usc_get_serial_signals() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) /* usc_set_serial_signals()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) * Set the state of RTS and DTR based on contents of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) * serial_signals member of device extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) static void usc_set_serial_signals( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) u16 Control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) unsigned char V24Out = info->serial_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) /* get the current value of the Port Control Register (PCR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) Control = usc_InReg( info, PCR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) if ( V24Out & SerialSignal_RTS )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) Control &= ~(BIT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) Control |= BIT6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) if ( V24Out & SerialSignal_DTR )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) Control &= ~(BIT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) Control |= BIT4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) usc_OutReg( info, PCR, Control );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) } /* end of usc_set_serial_signals() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) /* usc_enable_async_clock()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) * Enable the async clock at the specified frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) * data_rate data rate of clock in bps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) * 0 disables the AUX clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) if ( data_rate ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) * Clock mode Control Register (CMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) * <15..14> 00 counter 1 Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) * <13..12> 00 counter 0 Disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) * <11..10> 11 BRG1 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) * <9..8> 11 BRG0 Input is TxC Pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) * <7..6> 01 DPLL Input is BRG1 Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) * <5..3> 100 TxCLK comes from BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) * <2..0> 100 RxCLK comes from BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) * 0000 1111 0110 0100 = 0x0f64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) usc_OutReg( info, CMCR, 0x0f64 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) * Write 16-bit Time Constant for BRG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) * Time Constant = (ClkSpeed / data_rate) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) * ClkSpeed = 921600 (ISA), 691200 (PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) * Hardware Configuration Register (HCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) * Clear Bit 1, BRG0 mode = Continuous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) * Set Bit 0 to enable BRG0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) usc_OutReg( info, HCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) usc_OutReg( info, IOCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) /* data rate == 0 so turn off BRG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) } /* end of usc_enable_async_clock() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) * Buffer Structures:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) * Normal memory access uses virtual addresses that can make discontiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) * physical memory pages appear to be contiguous in the virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) * space (the processors memory mapping handles the conversions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) * DMA transfers require physically contiguous memory. This is because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) * the DMA system controller and DMA bus masters deal with memory using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) * only physical addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) * This causes a problem under Windows NT when large DMA buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) * needed. Fragmentation of the nonpaged pool prevents allocations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) * physically contiguous buffers larger than the PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) * However the 16C32 supports Bus Master Scatter/Gather DMA which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) * allows DMA transfers to physically discontiguous buffers. Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) * about each data transfer buffer is contained in a memory structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) * called a 'buffer entry'. A list of buffer entries is maintained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) * to track and control the use of the data transfer buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) * To support this strategy we will allocate sufficient PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) * contiguous memory buffers to allow for the total required buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) * space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) * The 16C32 accesses the list of buffer entries using Bus Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) * DMA. Control information is read from the buffer entries by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) * 16C32 to control data transfers. status information is written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) * the buffer entries by the 16C32 to indicate the status of completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) * transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) * The CPU writes control information to the buffer entries to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) * the 16C32 and reads status information from the buffer entries to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) * determine information about received and transmitted frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) * Because the CPU and 16C32 (adapter) both need simultaneous access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) * to the buffer entries, the buffer entry memory is allocated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) * HalAllocateCommonBuffer(). This restricts the size of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) * entry list to PAGE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) * The actual data buffers on the other hand will only be accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) * by the CPU or the adapter but not by both simultaneously. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) * Scatter/Gather packet based DMA procedures for using physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) * discontiguous pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) * mgsl_reset_tx_dma_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) * Set the count for all transmit buffers to 0 to indicate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) * buffer is available for use and set the current buffer to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) * first buffer. This effectively makes all buffers free and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) * discards any data in buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) for ( i = 0; i < info->tx_buffer_count; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) info->current_tx_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) info->start_tx_dma_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) info->tx_dma_buffers_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) info->get_tx_holding_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) info->put_tx_holding_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) info->tx_holding_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) } /* end of mgsl_reset_tx_dma_buffers() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) * num_free_tx_dma_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) * returns the number of free tx dma buffers available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) * Return Value: number of free tx dma buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) static int num_free_tx_dma_buffers(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) return info->tx_buffer_count - info->tx_dma_buffers_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) * mgsl_reset_rx_dma_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) * Set the count for all receive buffers to DMABUFFERSIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) * and set the current buffer to the first buffer. This effectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) * makes all buffers free and discards any data in buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) for ( i = 0; i < info->rx_buffer_count; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) // info->rx_buffer_list[i].count = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) // info->rx_buffer_list[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) info->current_rx_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) } /* end of mgsl_reset_rx_dma_buffers() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) * mgsl_free_rx_frame_buffers()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) * Free the receive buffers used by a received SDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) * frame such that the buffers can be reused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) * info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) * StartIndex index of 1st receive buffer of frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) * EndIndex index of last receive buffer of frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) bool Done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) DMABUFFERENTRY *pBufEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) unsigned int Index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) /* Starting with 1st buffer entry of the frame clear the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) /* field and set the count field to DMA Buffer Size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) Index = StartIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) while( !Done ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) pBufEntry = &(info->rx_buffer_list[Index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) if ( Index == EndIndex ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) /* This is the last buffer of the frame! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) Done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) /* reset current buffer for reuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) // pBufEntry->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) // pBufEntry->count = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) /* advance to next buffer entry in linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) Index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) if ( Index == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) Index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) /* set current buffer to next buffer after last buffer of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) info->current_rx_buffer = Index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) } /* end of free_rx_frame_buffers() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) /* mgsl_get_rx_frame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) * This function attempts to return a received SDLC frame from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) * receive DMA buffers. Only frames received without errors are returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) * Arguments: info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) * Return Value: true if frame returned, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) static bool mgsl_get_rx_frame(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) DMABUFFERENTRY *pBufEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) unsigned int framesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) bool ReturnCode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) struct tty_struct *tty = info->port.tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) bool return_frame = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) * current_rx_buffer points to the 1st buffer of the next available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) * receive frame. To find the last buffer of the frame look for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) * a non-zero status field in the buffer entries. (The status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) * field is set by the 16C32 after completing a receive frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) StartIndex = EndIndex = info->current_rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) while( !info->rx_buffer_list[EndIndex].status ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) * If the count field of the buffer entry is non-zero then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) * this buffer has not been used. (The 16C32 clears the count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) * field when it starts using the buffer.) If an unused buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) * is encountered then there are no frames available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) if ( info->rx_buffer_list[EndIndex].count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) goto Cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) /* advance to next buffer entry in linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) EndIndex++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) if ( EndIndex == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) EndIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) /* if entire list searched then no frame available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) if ( EndIndex == StartIndex ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) /* If this occurs then something bad happened,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) * all buffers have been 'used' but none mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) * the end of a frame. Reset buffers and receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) if ( info->rx_enabled ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) goto Cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) /* check status of receive frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) status = info->rx_buffer_list[EndIndex].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) if ( status & RXSTATUS_SHORT_FRAME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) info->icount.rxshort++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) else if ( status & RXSTATUS_ABORT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) info->icount.rxabort++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) else if ( status & RXSTATUS_OVERRUN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) info->icount.rxover++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) info->icount.rxcrc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) return_frame = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) framesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) info->netdev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) info->netdev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) return_frame = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) if ( return_frame ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) /* receive frame has no errors, get frame size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) * The frame size is the starting value of the RCC (which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) * set to 0xffff) minus the ending value of the RCC (decremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) * once for each receive character) minus 2 for the 16-bit CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) /* adjust frame size for CRC if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) if ( info->params.crc_type == HDLC_CRC_16_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) framesize -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) framesize -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) __FILE__,__LINE__,info->device_name,status,framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) if ( debug_level >= DEBUG_LEVEL_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) min_t(int, framesize, DMABUFFERSIZE),0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) if (framesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) ((framesize+1) > info->max_frame_size) ) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) (framesize > info->max_frame_size) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) info->icount.rxlong++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) /* copy dma buffer(s) to contiguous intermediate buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) int copy_count = framesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) int index = StartIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) unsigned char *ptmp = info->intermediate_rxbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) if ( !(status & RXSTATUS_CRC_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) info->icount.rxok++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) while(copy_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) int partial_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) if ( copy_count > DMABUFFERSIZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) partial_count = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) partial_count = copy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) pBufEntry = &(info->rx_buffer_list[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) memcpy( ptmp, pBufEntry->virt_addr, partial_count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) ptmp += partial_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) copy_count -= partial_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) if ( ++index == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) ++framesize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) *ptmp = (status & RXSTATUS_CRC_ERROR ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) RX_CRC_ERROR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) RX_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) if ( debug_level >= DEBUG_LEVEL_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) __FILE__,__LINE__,info->device_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) *ptmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) if (info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) /* Free the buffers used by this frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) ReturnCode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) Cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) if ( info->rx_enabled && info->rx_overflow ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) /* The receiver needs to restarted because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) * a receive overflow (buffer or FIFO). If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) * receive buffers are now empty, then restart receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) if ( !info->rx_buffer_list[EndIndex].status &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) info->rx_buffer_list[EndIndex].count ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) return ReturnCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) } /* end of mgsl_get_rx_frame() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) /* mgsl_get_raw_rx_frame()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) * This function attempts to return a received frame from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) * receive DMA buffers when running in external loop mode. In this mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) * we will return at most one DMABUFFERSIZE frame to the application.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) * The USC receiver is triggering off of DCD going active to start a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) * frame, and DCD going inactive to terminate the frame (similar to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) * processing a closing flag character).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) * status field and the RCC field will indicate the length of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) * entire received frame. We take this RCC field and get the modulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) * of RCC and DMABUFFERSIZE to determine if number of bytes in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) * last Rx DMA buffer and return that last portion of the frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) * Arguments: info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) * Return Value: true if frame returned, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) unsigned int CurrentIndex, NextIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) DMABUFFERENTRY *pBufEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) unsigned int framesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) bool ReturnCode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) struct tty_struct *tty = info->port.tty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) * current_rx_buffer points to the 1st buffer of the next available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) * receive frame. The status field is set by the 16C32 after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) * completing a receive frame. If the status field of this buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) * is zero, either the USC is still filling this buffer or this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) * is one of a series of buffers making up a received frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) * If the count field of this buffer is zero, the USC is either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) * using this buffer or has used this buffer. Look at the count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) * field of the next buffer. If that next buffer's count is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) * non-zero, the USC is still actively using the current buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) * Otherwise, if the next buffer's count field is zero, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) * current buffer is complete and the USC is using the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) * buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) CurrentIndex = NextIndex = info->current_rx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) ++NextIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) if ( NextIndex == info->rx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) NextIndex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) (info->rx_buffer_list[CurrentIndex].count == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) info->rx_buffer_list[NextIndex].count == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) * Either the status field of this dma buffer is non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) * (indicating the last buffer of a receive frame) or the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) * buffer is marked as in use -- implying this buffer is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) * and an intermediate buffer for this received frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) status = info->rx_buffer_list[CurrentIndex].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) if ( status & RXSTATUS_SHORT_FRAME )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) info->icount.rxshort++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) else if ( status & RXSTATUS_ABORT )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) info->icount.rxabort++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) else if ( status & RXSTATUS_OVERRUN )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) info->icount.rxover++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) info->icount.rxcrc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) framesize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) * A receive frame is available, get frame size and status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) * The frame size is the starting value of the RCC (which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) * set to 0xffff) minus the ending value of the RCC (decremented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) * once for each receive character) minus 2 or 4 for the 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) * or 32-bit CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) * If the status field is zero, this is an intermediate buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) * It's size is 4K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) * If the DMA Buffer Entry's Status field is non-zero, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) * receive operation completed normally (ie: DCD dropped). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) * RCC field is valid and holds the received frame size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) * It is possible that the RCC field will be zero on a DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) * entry with a non-zero status. This can occur if the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) * frame size (number of bytes between the time DCD goes active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) * to the time DCD goes inactive) exceeds 65535 bytes. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) * case the 16C32 has underrun on the RCC count and appears to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) * stop updating this counter to let us know the actual received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) * frame size. If this happens (non-zero status and zero RCC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) * simply return the entire RxDMA Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) if ( status ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) * In the event that the final RxDMA Buffer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) * terminated with a non-zero status and the RCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) * field is zero, we interpret this as the RCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) * having underflowed (received frame > 65535 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) * Signal the event to the user by passing back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) * a status of RxStatus_CrcError returning the full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) * buffer and let the app figure out what data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) * actually valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) if ( info->rx_buffer_list[CurrentIndex].rcc )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) framesize = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) framesize = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) if ( framesize > DMABUFFERSIZE ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) * if running in raw sync mode, ISR handler for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) * End Of Buffer events terminates all buffers at 4K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) * If this frame size is said to be >4K, get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) * actual number of bytes of the frame in this buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) framesize = framesize % DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) if ( debug_level >= DEBUG_LEVEL_BH )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) __FILE__,__LINE__,info->device_name,status,framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) if ( debug_level >= DEBUG_LEVEL_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) min_t(int, framesize, DMABUFFERSIZE),0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) if (framesize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) /* copy dma buffer(s) to contiguous intermediate buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) /* NOTE: we never copy more than DMABUFFERSIZE bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) info->icount.rxok++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) /* Free the buffers used by this frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) ReturnCode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) if ( info->rx_enabled && info->rx_overflow ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) /* The receiver needs to restarted because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) * a receive overflow (buffer or FIFO). If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) * receive buffers are now empty, then restart receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641) if ( !info->rx_buffer_list[CurrentIndex].status &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) info->rx_buffer_list[CurrentIndex].count ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) usc_start_receiver(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) return ReturnCode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) } /* end of mgsl_get_raw_rx_frame() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) /* mgsl_load_tx_dma_buffer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) * Load the transmit DMA buffer with the specified data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) * info pointer to device extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) * Buffer pointer to buffer containing frame to load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661) * BufferSize size in bytes of frame in Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) const char *Buffer, unsigned int BufferSize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) unsigned short Copycount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) DMABUFFERENTRY *pBufEntry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) if ( debug_level >= DEBUG_LEVEL_DATA )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) /* set CMR:13 to start transmit when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) * next GoAhead (abort) is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) info->cmr_value |= BIT13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) /* begin loading the frame in the next available tx dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) * buffer, remember it's starting location for setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) * up tx dma operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) i = info->current_tx_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) info->start_tx_dma_buffer = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) /* Setup the status and RCC (Frame Size) fields of the 1st */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) /* buffer entry in the transmit DMA buffer list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) info->tx_buffer_list[i].rcc = BufferSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694) info->tx_buffer_list[i].count = BufferSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) /* Copy frame data from 1st source buffer to the DMA buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) /* The frame data may span multiple DMA buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) while( BufferSize ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) /* Get a pointer to next DMA buffer entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) pBufEntry = &info->tx_buffer_list[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) if ( i == info->tx_buffer_count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) i=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) /* Calculate the number of bytes that can be copied from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) /* the source buffer to this DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) if ( BufferSize > DMABUFFERSIZE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) Copycount = DMABUFFERSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) Copycount = BufferSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) /* Actually copy data from source buffer to DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) /* Also set the data count for this individual DMA buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) pBufEntry->count = Copycount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) /* Advance source pointer and reduce remaining data count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720) Buffer += Copycount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) BufferSize -= Copycount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) ++info->tx_dma_buffers_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) /* remember next available tx dma buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727) info->current_tx_buffer = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) } /* end of mgsl_load_tx_dma_buffer() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) * mgsl_register_test()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) * Performs a register test of the 16C32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) * Return Value: true if test passed, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739) static bool mgsl_register_test( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) static unsigned short BitPatterns[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742) { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) bool rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) usc_reset(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751) /* Verify the reset state of some registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) if ( (usc_InReg( info, SICR ) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754) (usc_InReg( info, IVR ) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) (usc_InDmaReg( info, DIVR ) != 0) ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759) if ( rc ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) /* Write bit patterns to various registers but do it out of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) /* sync, then read back and verify values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763) for ( i = 0 ; i < Patterncount ; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) usc_OutReg( info, TC0R, BitPatterns[i] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775) (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) usc_reset(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) } /* end of mgsl_register_test() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) /* mgsl_irq_test() Perform interrupt test of the 16C32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) * Return Value: true if test passed, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) static bool mgsl_irq_test( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) unsigned long EndTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) usc_reset(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) * The ISR sets irq_occurred to true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) info->irq_occurred = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) /* Enable INTEN (Port 6, Bit12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812) /* This connects the IRQ request signal to the ISA bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) /* on the ISA adapter. This has no effect for the PCI adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814) usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) usc_EnableMasterIrqBit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) usc_EnableInterrupts(info, IO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) usc_ClearIrqPendingBits(info, IO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821) usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825) EndTime=100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) while( EndTime-- && !info->irq_occurred ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) usc_reset(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) return info->irq_occurred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) } /* end of mgsl_irq_test() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) /* mgsl_dma_test()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840) * Perform a DMA test of the 16C32. A small frame is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) * transmitted via DMA from a transmit buffer to a receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) * using single buffer DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) * Return Value: true if test passed, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) static bool mgsl_dma_test( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) unsigned short FifoLevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) unsigned long phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) unsigned int FrameSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) char *TmpPtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) bool rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) unsigned short status=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) unsigned long EndTime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858) MGSL_PARAMS tmp_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) /* save current port options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) /* load default port options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865) #define TESTFRAMESIZE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) /* setup 16C32 for SDLC DMA transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) usc_reset(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872) usc_set_sdlc_mode(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) usc_enable_loopback(info,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) /* Reprogram the RDMR so that the 16C32 does NOT clear the count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) * field of the buffer entry after fetching buffer address. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877) * way we can detect a DMA failure for a DMA read (which should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) * non-destructive to system memory) before we try and write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) * memory (where a failure could corrupt system memory).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) /* Receive DMA mode Register (RDMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) * <15..14> 11 DMA mode = Linked List Buffer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) * <13> 1 RSBinA/L = store Rx status Block in List entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) * <12> 0 1 = Clear count of List Entry after fetching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) * <11..10> 00 Address mode = Increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) * <9> 1 Terminate Buffer on RxBound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) * <8> 0 Bus Width = 16bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890) * <7..0> ? status Bits (write as 0s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) * 1110 0010 0000 0000 = 0xe200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) usc_OutDmaReg( info, RDMR, 0xe200 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) FrameSize = TESTFRAMESIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) /* setup 1st transmit buffer entry: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905) /* with frame size and transmit control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) info->tx_buffer_list[0].count = FrameSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908) info->tx_buffer_list[0].rcc = FrameSize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) info->tx_buffer_list[0].status = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911) /* build a transmit frame in 1st transmit DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) TmpPtr = info->tx_buffer_list[0].virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) for (i = 0; i < FrameSize; i++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) *TmpPtr++ = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) /* setup 1st receive buffer entry: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) /* clear status, set max receive buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) info->rx_buffer_list[0].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) info->rx_buffer_list[0].count = FrameSize + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) /* zero out the 1st receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) /* Set count field of next buffer entries to prevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928) /* 16C32 from using buffers after the 1st one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930) info->tx_buffer_list[1].count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) info->rx_buffer_list[1].count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) /***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935) /* Program 16C32 receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) /***************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) /* setup DMA transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) usc_RTCmd( info, RTCmd_PurgeRxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) /* program 16C32 receiver with physical address of 1st DMA buffer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) phys_addr = info->rx_buffer_list[0].phys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945) usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948) /* Clear the Rx DMA status bits (read RDMR) and start channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) usc_InDmaReg( info, RDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) usc_DmaCmd( info, DmaCmd_InitRxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) /* Enable Receiver (RMR <1..0> = 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) /*************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) /*************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962) /* Wait 100ms for interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) EndTime = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966) if (time_after(jiffies, EndTime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972) status = usc_InDmaReg( info, RDMR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) if ( !(status & BIT4) && (status & BIT5) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) /* INITG (BIT 4) is inactive (no entry read in progress) AND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977) /* BUSY (BIT 5) is active (channel still active). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) /* This means the buffer entry read has completed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) /******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985) /* Program 16C32 transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) /******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990) /* Program the Transmit Character Length Register (TCLR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993) usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996) /* Program the address of the 1st DMA Buffer Entry in linked list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) phys_addr = info->tx_buffer_list[0].phys_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002) /* unlatch Tx status bits, and start transmit channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) usc_DmaCmd( info, DmaCmd_InitTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) /* wait for DMA controller to fill transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009) usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) /**********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015) /* WAIT FOR TRANSMIT FIFO TO FILL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) /**********************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) /* Wait 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) EndTime = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) for(;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) if (time_after(jiffies, EndTime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) FifoLevel = usc_InReg(info, TICR) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031) if ( FifoLevel < 16 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034) if ( FrameSize < 32 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) /* This frame is smaller than the entire transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) /* so wait for the entire frame to be loaded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) if ( FifoLevel <= (32 - FrameSize) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) if ( rc )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) /* Enable 16C32 transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) usc_TCmd( info, TCmd_SendFrame );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) /******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) /* WAIT FOR TRANSMIT COMPLETE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) /******************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060) /* Wait 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) EndTime = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) /* While timer not expired wait for transmit complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) status = usc_InReg( info, TCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069) while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) if (time_after(jiffies, EndTime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) status = usc_InReg( info, TCSR );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) if ( rc ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) /* CHECK FOR TRANSMIT ERRORS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) if ( status & (BIT5 | BIT1) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) if ( rc ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) /* WAIT FOR RECEIVE COMPLETE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) /* Wait 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) EndTime = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) /* Wait for 16C32 to write receive status to buffer entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) status=info->rx_buffer_list[0].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) while ( status == 0 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) if (time_after(jiffies, EndTime)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) status=info->rx_buffer_list[0].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) if ( rc ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) /* CHECK FOR RECEIVE ERRORS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) status = info->rx_buffer_list[0].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110) if ( status & (BIT8 | BIT3 | BIT1) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) /* receive error has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) if ( memcmp( info->tx_buffer_list[0].virt_addr ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) info->rx_buffer_list[0].virt_addr, FrameSize ) ){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) usc_reset( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) /* restore current port options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) } /* end of mgsl_dma_test() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) /* mgsl_adapter_test()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) * Perform the register, IRQ, and DMA tests for the 16C32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) * Return Value: 0 if success, otherwise -ENODEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) static int mgsl_adapter_test( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) printk( "%s(%d):Testing device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) __FILE__,__LINE__,info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) if ( !mgsl_register_test( info ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) info->init_error = DiagStatus_AddressFailure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) if ( !mgsl_irq_test( info ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153) info->init_error = DiagStatus_IrqFailure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) if ( !mgsl_dma_test( info ) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) info->init_error = DiagStatus_DmaFailure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161) printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) printk( "%s(%d):device %s passed diagnostics\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) __FILE__,__LINE__,info->device_name );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) } /* end of mgsl_adapter_test() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) /* mgsl_memory_test()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) * Test the shared memory on a PCI adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) * Arguments: info pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) * Return Value: true if test passed, otherwise false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) static bool mgsl_memory_test( struct mgsl_struct *info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) static unsigned long BitPatterns[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185) unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) unsigned long * TestAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) TestAddr = (unsigned long *)info->memory_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192) /* Test data lines with test pattern at one location. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194) for ( i = 0 ; i < Patterncount ; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) *TestAddr = BitPatterns[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) if ( *TestAddr != BitPatterns[i] )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200) /* Test address lines with incrementing pattern over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) /* entire address range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) for ( i = 0 ; i < TestLimit ; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) *TestAddr = i * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) TestAddr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) TestAddr = (unsigned long *)info->memory_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) for ( i = 0 ; i < TestLimit ; i++ ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) if ( *TestAddr != i * 4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) TestAddr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220) } /* End Of mgsl_memory_test() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223) /* mgsl_load_pci_memory()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) * Load a large block of data into the PCI shared memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) * Use this instead of memcpy() or memmove() to move data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) * into the PCI shared memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231) * This function prevents the PCI9050 interface chip from hogging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) * the adapter local bus, which can starve the 16C32 by preventing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) * 16C32 bus master cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) * The PCI9050 documentation says that the 9050 will always release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) * control of the local bus after completing the current read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) * or write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) * It appears that as long as the PCI9050 write FIFO is full, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240) * PCI9050 treats all of the writes as a single burst transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) * and will not release the bus. This causes DMA latency problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) * at high speeds when copying large data blocks to the shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) * memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) * This function in effect, breaks the a large shared memory write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) * into multiple transations by interleaving a shared memory read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247) * which will flush the write FIFO and 'complete' the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) * transation. This allows any pending DMA request to gain control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) * of the local bus in a timely fasion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) * Arguments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) * TargetPtr pointer to target address in PCI shared memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) * SourcePtr pointer to source buffer for data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) * count count in bytes of data to copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) unsigned short count )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) #define PCI_LOAD_INTERVAL 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) unsigned short Index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) unsigned long Dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) for ( Index = 0 ; Index < Intervalcount ; Index++ )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271) memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) Dummy = *((volatile unsigned long *)TargetPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) TargetPtr += PCI_LOAD_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) SourcePtr += PCI_LOAD_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) } /* End Of mgsl_load_pci_memory() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) int linecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) if (xmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) printk("%s tx data:\n",info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) printk("%s rx data:\n",info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) while(count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291) if (count > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) linecount = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) linecount = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) for(i=0;i<linecount;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) printk("%02X ",(unsigned char)data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) for(;i<17;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) printk(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) for(i=0;i<linecount;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) if (data[i]>=040 && data[i]<=0176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) printk("%c",data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) printk(".");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) data += linecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) count -= linecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) } /* end of mgsl_trace_block() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) /* mgsl_tx_timeout()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) * called when HDLC frame times out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) * update stats and do tx completion processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) * Arguments: context pointer to device instance data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) * Return Value: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) static void mgsl_tx_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) struct mgsl_struct *info = from_timer(info, t, tx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) if ( debug_level >= DEBUG_LEVEL_INFO )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) printk( "%s(%d):mgsl_tx_timeout(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) __FILE__,__LINE__,info->device_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) if(info->tx_active &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) (info->params.mode == MGSL_MODE_HDLC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) info->params.mode == MGSL_MODE_RAW) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) info->icount.txtimeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) info->tx_active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) usc_loopmode_cancel_transmit( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) if (info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) hdlcdev_tx_done(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) mgsl_bh_transmit(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) } /* end of mgsl_tx_timeout() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) /* signal that there are no more frames to send, so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) * line is 'released' by echoing RxD to TxD when current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) * transmission is complete (or immediately if no tx in progress).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) static int mgsl_loopmode_send_done( struct mgsl_struct * info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) if (info->tx_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) info->loopmode_send_done_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) usc_loopmode_send_done(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372) /* release the line by echoing RxD to TxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) * upon completion of a transmit frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) static void usc_loopmode_send_done( struct mgsl_struct * info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) info->loopmode_send_done_requested = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) /* clear CMR:13 to 0 to start echoing RxData to TxData */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) info->cmr_value &= ~BIT13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) usc_OutReg(info, CMR, info->cmr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) /* abort a transmit in progress while in HDLC LoopMode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) /* reset tx dma channel and purge TxFifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) usc_RTCmd( info, RTCmd_PurgeTxFifo );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) usc_DmaCmd( info, DmaCmd_ResetTxChannel );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) usc_loopmode_send_done( info );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) * we must clear CMR:13 to begin repeating TxData to RxData
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) static void usc_loopmode_insert_request( struct mgsl_struct * info )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) info->loopmode_insert_requested = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) * begin repeating TxData on RxData (complete insertion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404) usc_OutReg( info, RICR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) info->cmr_value |= BIT13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) usc_OutReg(info, CMR, info->cmr_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) /* return 1 if station is inserted into the loop, otherwise 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) static int usc_loopmode_active( struct mgsl_struct * info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416) return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) #if SYNCLINK_GENERIC_HDLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422) * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) * @encoding: serial encoding setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) * @parity: FCS setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) * Set encoding and frame check sequence (FCS) options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) * Return: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) unsigned short parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) unsigned char new_encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) unsigned short new_crctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) /* return error if TTY interface open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) if (info->port.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) switch (encoding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444) case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448) case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) switch (parity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455) case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) info->params.encoding = new_encoding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) info->params.crc_type = new_crctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) /* if network interface up, reprogram hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) if (info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465) mgsl_program_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7470) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7471) * hdlcdev_xmit - called by generic HDLC layer to send a frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7472) * @skb: socket buffer containing HDLC frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7473) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7475) static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7476) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7478) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7479) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7481) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7482) printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7484) /* stop sending until this frame completes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7485) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7487) /* copy data to device buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7488) info->xmit_cnt = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7489) mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7491) /* update network statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7492) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7493) dev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7495) /* done with socket buffer, so free it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7496) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7498) /* save start time for transmit timeout detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7499) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7501) /* start hardware transmitter if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7502) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7503) if (!info->tx_active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7504) usc_start_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7505) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7507) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7510) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7511) * hdlcdev_open - called by network layer when interface enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7512) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7514) * Claim resources and initialize hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7516) * Return: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7518) static int hdlcdev_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7520) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7521) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7522) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7524) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7525) printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7527) /* generic HDLC layer open processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7528) rc = hdlc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7529) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7530) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7532) /* arbitrate between network and tty opens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7533) spin_lock_irqsave(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7534) if (info->port.count != 0 || info->netcount != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7535) printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7536) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7537) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7539) info->netcount=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7540) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7542) /* claim resources and init adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7543) if ((rc = startup(info)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7544) spin_lock_irqsave(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7545) info->netcount=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7546) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7547) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7550) /* assert RTS and DTR, apply hardware settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7551) info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7552) mgsl_program_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7554) /* enable network layer transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7555) netif_trans_update(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7556) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7558) /* inform generic HDLC layer of current DCD status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7559) spin_lock_irqsave(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7560) usc_get_serial_signals(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7561) spin_unlock_irqrestore(&info->irq_spinlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7562) if (info->serial_signals & SerialSignal_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7563) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7565) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7569) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7570) * hdlcdev_close - called by network layer when interface is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7571) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7572) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7573) * Shutdown hardware and release resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7575) * Return: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7577) static int hdlcdev_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7579) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7580) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7582) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7583) printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7585) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7587) /* shutdown adapter and release resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7588) shutdown(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7590) hdlc_close(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7592) spin_lock_irqsave(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7593) info->netcount=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7594) spin_unlock_irqrestore(&info->netlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7599) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7600) * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7601) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7602) * @ifr: pointer to network interface request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7603) * @cmd: IOCTL command code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7605) * Return: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7607) static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7609) const size_t size = sizeof(sync_serial_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7610) sync_serial_settings new_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7611) sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7612) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7613) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7615) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7616) printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7618) /* return error if TTY interface open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7619) if (info->port.count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7620) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7622) if (cmd != SIOCWANDEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7623) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7625) switch(ifr->ifr_settings.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7626) case IF_GET_IFACE: /* return current sync_serial_settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7628) ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7629) if (ifr->ifr_settings.size < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7630) ifr->ifr_settings.size = size; /* data size wanted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7631) return -ENOBUFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7634) flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7635) HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7636) HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7637) HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7639) memset(&new_line, 0, sizeof(new_line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7640) switch (flags){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7641) case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7642) case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7643) case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7644) case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7645) default: new_line.clock_type = CLOCK_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7648) new_line.clock_rate = info->params.clock_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7649) new_line.loopback = info->params.loopback ? 1:0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7651) if (copy_to_user(line, &new_line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7652) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7655) case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7657) if(!capable(CAP_NET_ADMIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7658) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7659) if (copy_from_user(&new_line, line, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7660) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7662) switch (new_line.clock_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7664) case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7665) case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7666) case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7667) case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7668) case CLOCK_DEFAULT: flags = info->params.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7669) (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7670) HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7671) HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7672) HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7673) default: return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7676) if (new_line.loopback != 0 && new_line.loopback != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7679) info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7680) HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7681) HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7682) HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7683) info->params.flags |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7685) info->params.loopback = new_line.loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7687) if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7688) info->params.clock_speed = new_line.clock_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7690) info->params.clock_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7692) /* if network interface up, reprogram hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7693) if (info->netcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7694) mgsl_program_hw(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7697) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7698) return hdlc_ioctl(dev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7702) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7703) * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7704) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7705) * @dev: pointer to network device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7707) static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7709) struct mgsl_struct *info = dev_to_port(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7710) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7712) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7713) printk("hdlcdev_tx_timeout(%s)\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7715) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7716) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7718) spin_lock_irqsave(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7719) usc_stop_transmitter(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7720) spin_unlock_irqrestore(&info->irq_spinlock,flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7722) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7725) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7726) * hdlcdev_tx_done - called by device driver when transmit completes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7727) * @info: pointer to device instance information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7728) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7729) * Reenable network layer transmit if stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7731) static void hdlcdev_tx_done(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7733) if (netif_queue_stopped(info->netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7734) netif_wake_queue(info->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7737) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7738) * hdlcdev_rx - called by device driver when frame received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7739) * @info: pointer to device instance information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7740) * @buf: pointer to buffer contianing frame data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7741) * @size: count of data bytes in buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7743) * Pass frame to network layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7745) static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7747) struct sk_buff *skb = dev_alloc_skb(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7748) struct net_device *dev = info->netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7750) if (debug_level >= DEBUG_LEVEL_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7751) printk("hdlcdev_rx(%s)\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7753) if (skb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7754) printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7755) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7756) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7760) skb_put_data(skb, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7762) skb->protocol = hdlc_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7764) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7765) dev->stats.rx_bytes += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7767) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7770) static const struct net_device_ops hdlcdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7771) .ndo_open = hdlcdev_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7772) .ndo_stop = hdlcdev_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7773) .ndo_start_xmit = hdlc_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7774) .ndo_do_ioctl = hdlcdev_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7775) .ndo_tx_timeout = hdlcdev_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7778) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7779) * hdlcdev_init - called by device driver when adding device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7780) * @info: pointer to device instance information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7781) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7782) * Do generic HDLC initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7783) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7784) * Return: 0 if success, otherwise error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7786) static int hdlcdev_init(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7788) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7789) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7790) hdlc_device *hdlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7792) /* allocate and initialize network and HDLC layer objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7794) dev = alloc_hdlcdev(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7795) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7796) printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7797) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7800) /* for network layer reporting purposes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7801) dev->base_addr = info->io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7802) dev->irq = info->irq_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7803) dev->dma = info->dma_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7805) /* network layer callbacks and settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7806) dev->netdev_ops = &hdlcdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7807) dev->watchdog_timeo = 10 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7808) dev->tx_queue_len = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7810) /* generic HDLC layer callbacks and settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7811) hdlc = dev_to_hdlc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7812) hdlc->attach = hdlcdev_attach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7813) hdlc->xmit = hdlcdev_xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7815) /* register objects with HDLC layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7816) rc = register_hdlc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7817) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7818) printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7819) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7820) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7823) info->netdev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7827) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7828) * hdlcdev_exit - called by device driver when removing device instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7829) * @info: pointer to device instance information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7831) * Do generic HDLC cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7833) static void hdlcdev_exit(struct mgsl_struct *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7835) unregister_hdlc_device(info->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7836) free_netdev(info->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7837) info->netdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7840) #endif /* CONFIG_HDLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7843) static int synclink_init_one (struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7844) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7846) struct mgsl_struct *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7848) if (pci_enable_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7849) printk("error enabling pci device %p\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7850) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7853) info = mgsl_allocate_device();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7854) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7855) printk("can't allocate device instance data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7856) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7859) /* Copy user configuration info to device instance data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7861) info->io_base = pci_resource_start(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7862) info->irq_level = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7863) info->phys_memory_base = pci_resource_start(dev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7865) /* Because veremap only works on page boundaries we must map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7866) * a larger area than is actually implemented for the LCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7867) * memory range. We map a full page starting at the page boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7869) info->phys_lcr_base = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7870) info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7871) info->phys_lcr_base &= ~(PAGE_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7873) info->io_addr_size = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7874) info->irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7876) if (dev->device == 0x0210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7877) /* Version 1 PCI9030 based universal PCI adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7878) info->misc_ctrl_value = 0x007c4080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7879) info->hw_version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7880) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7881) /* Version 0 PCI9050 based 5V PCI adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7882) * A PCI9050 bug prevents reading LCR registers if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7883) * LCR base address bit 7 is set. Maintain shadow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7884) * value so we can write to LCR misc control reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7885) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7886) info->misc_ctrl_value = 0x087e4546;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7887) info->hw_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7890) mgsl_add_device(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7895) static void synclink_remove_one (struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7898)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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