^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * zs.h: Definitions for the DECstation Z85C30 serial driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _SERIAL_ZS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _SERIAL_ZS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ZS_NUM_REGS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This is our internal structure for each serial port's state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct zs_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct zs_scc *scc; /* Containing SCC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct uart_port port; /* Underlying UART. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int clk_mode; /* May be 1, 16, 32, or 64. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int tty_break; /* Set on BREAK condition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int tx_stopped; /* Output is suspended. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int mctrl; /* State of modem lines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 brk; /* BREAK state from RR0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Per-SCC state for locking and the interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct zs_scc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct zs_port zport[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) spinlock_t zlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) atomic_t irq_guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int initialised;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Conversion routines to/from brg time constants from/to bits per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * The Zilog register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Write Register 0 (Command) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R0 0 /* Register selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NULLCODE 0 /* Null Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define POINT_HIGH 0x8 /* Select upper half of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SEND_ABORT 0x18 /* HDLC Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RES_Tx_P 0x28 /* Reset TxINT Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ERR_RES 0x30 /* Error Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RES_H_IUS 0x38 /* Reset highest IUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RES_EOM_L 0xC0 /* Reset EOM latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TxINT_ENAB 0x2 /* Tx Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PAR_SPEC 0x4 /* Parity is special condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RxINT_DISAB 0 /* Rx Int Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RxINT_ERR 0x18 /* Int on error only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RxINT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Write Register 2 (Interrupt Vector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Write Register 3 (Receive Parameters and Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RxENABLE 0x1 /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ENT_HM 0x10 /* Enter Hunt Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AUTO_ENAB 0x20 /* Auto Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define Rx5 0x0 /* Rx 5 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define Rx7 0x40 /* Rx 7 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define Rx6 0x80 /* Rx 6 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define Rx8 0xc0 /* Rx 8 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RxNBITS_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PAR_ENA 0x1 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PAR_EVEN 0x2 /* Parity Even/Odd* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SYNC_ENAB 0 /* Sync Modes Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SB1 0x4 /* 1 stop bit/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SB15 0x8 /* 1.5 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SB2 0xc /* 2 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SB_MASK 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MONSYNC 0 /* 8 Bit Sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BISYNC 0x10 /* 16 bit sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EXTSYNC 0x30 /* External Sync Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define X1CLK 0x0 /* x1 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define X16CLK 0x40 /* x16 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define X32CLK 0x80 /* x32 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define X64CLK 0xc0 /* x64 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define XCLK_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Write Register 5 (Transmit Parameters and Controls) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RTS 0x2 /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TxENAB 0x8 /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SND_BRK 0x10 /* Send Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define Tx5 0x0 /* Tx 5 bits (or less)/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define Tx7 0x20 /* Tx 7 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define Tx6 0x40 /* Tx 6 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define Tx8 0x60 /* Tx 8 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TxNBITS_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DTR 0x80 /* DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Write Register 8 (Transmit Buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Write Register 9 (Master Interrupt Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VIS 1 /* Vector Includes Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NV 2 /* No Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DLC 4 /* Disable Lower Chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MIE 8 /* Master Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define STATHI 0x10 /* Status high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SOFTACK 0x20 /* Software Interrupt Acknowledge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define NORESET 0 /* No reset on write to R9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CHRB 0x40 /* Reset channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CHRA 0x80 /* Reset channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FHWRES 0xc0 /* Force hardware reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BIT6 1 /* 6 bit/8bit sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define LOOPMODE 2 /* SDLC Loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MARKIDLE 8 /* Mark/flag on idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GAOP 0x10 /* Go active on poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NRZ 0 /* NRZ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define NRZI 0x20 /* NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FM1 0x40 /* FM1 (transition = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FM0 0x60 /* FM0 (transition = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CRCPS 0x80 /* CRC Preset I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Write Register 11 (Clock Mode Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TRxCXT 0 /* TRxC = Xtal output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TRxCTC 1 /* TRxC = Transmit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TRxCBR 2 /* TRxC = BR Generator Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TRxCDP 3 /* TRxC = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TRxCOI 4 /* TRxC O/I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TCRTxCP 0 /* Transmit clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TCTRxCP 8 /* Transmit clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TCBR 0x10 /* Transmit clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TCDPLL 0x18 /* Transmit clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RCRTxCP 0 /* Receive clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RCBR 0x40 /* Receive clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RCDPLL 0x60 /* Receive clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Write Register 14 (Miscellaneous Control Bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BRENABL 1 /* Baud rate generator enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BRSRC 2 /* Baud rate generator source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DTRREQ 4 /* DTR/Request function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AUTOECHO 8 /* Auto Echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define LOOPBAK 0x10 /* Local loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SEARCH 0x20 /* Enter search mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RMC 0x40 /* Reset missing clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DISDPLL 0x60 /* Disable DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SSBR 0x80 /* Set DPLL source = BR generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SFMM 0xc0 /* Set FM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SNRZI 0xe0 /* Set NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Write Register 15 (External/Status Interrupt Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ZCIE 2 /* Zero count IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DCDIE 8 /* DCD IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SYNCIE 0x10 /* Sync/hunt IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CTSIE 0x20 /* CTS IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TxUIE 0x40 /* Tx Underrun/EOM IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BRKIE 0x80 /* Break/Abort IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define Rx_CH_AV 0x1 /* Rx Character Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ZCOUNT 0x2 /* Zero count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DCD 0x8 /* DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SYNC_HUNT 0x10 /* Sync/hunt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CTS 0x20 /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TxEOM 0x40 /* Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define BRK_ABRT 0x80 /* Break/Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Read Register 1 (Special Receive Condition Status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ALL_SNT 0x1 /* All sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Residue Data for 8 Rx bits/char programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RES3 0x8 /* 0/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define RES4 0x4 /* 0/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define RES5 0xc /* 0/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define RES6 0x2 /* 0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RES7 0xa /* 0/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RES8 0x6 /* 0/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RES18 0xe /* 1/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RES28 0x0 /* 2/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Special Rx Condition Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PAR_ERR 0x10 /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define Rx_OVR 0x20 /* Rx Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FRM_ERR 0x40 /* CRC/Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define END_FR 0x80 /* End of Frame (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Read Register 2 (Modified Interrupt Vector -- channel B). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Read Register 3 (Interrupt Pending Bits -- channel A only). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CHBTxIP 0x2 /* Channel B Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CHBRxIP 0x4 /* Channel B Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CHATxIP 0x10 /* Channel A Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CHARxIP 0x20 /* Channel A Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Read Register 8 (Receive Data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Read Register 10 (Miscellaneous Status Bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ONLOOP 2 /* On loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LOOPSEND 0x10 /* Loop sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK2MIS 0x40 /* Two clocks missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK1MIS 0x80 /* One clock missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Read Register 15 (External/Status Interrupt Control (WR15)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif /* _SERIAL_ZS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags