^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * zs.c: Serial port driver for IOASIC DECstations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * DECstation changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1998-2000 Harald Koerfgen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * For the rest of the code the original Copyright applies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Note: for IOASIC systems the wiring is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * mouse/keyboard:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * DIN-7 MJ-4 signal SCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 2 1 TxD <- A.TxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 3 4 RxD -> A.RxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * EIA-232/EIA-423:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * DB-25 MMJ-6 signal SCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 2 2 TxD <- B.TxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 3 5 RxD -> B.RxD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 4 RTS <- ~A.RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 5 CTS -> ~B.CTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 6 6 DSR -> ~A.SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 8 CD -> ~B.DCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 12 DSRS(DCE) -> ~A.CTS (*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 15 TxC -> B.TxC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 17 RxC -> B.RxC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 20 1 DTR <- ~A.DTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 22 RI -> ~A.DCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 23 DSRS(DTE) <- ~B.RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * is shared with DSRS(DTE) at pin 23.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * As you can immediately notice the wiring of the RTS, DTR and DSR signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * is a bit odd. This makes the handling of port B unnecessarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * complicated and prevents the use of some automatic modes of operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <asm/dec/interrupts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <asm/dec/ioasic_addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm/dec/system.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include "zs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static char zs_version[] __initdata = "0.10";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * It would be nice to dynamically allocate everything that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * depends on ZS_NUM_SCCS, so we could support any number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Z85C30s, but for now...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ZS_NUM_SCCS 2 /* Max # of ZS chips supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ZS_NUM_CHAN 2 /* 2 channels per chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ZS_CHAN_A 0 /* Index of the channel A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ZS_CHAN_B 1 /* Index of the channel B. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ZS_CHAN_IO_SIZE 8 /* IOMEM space size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ZS_CHAN_IO_STRIDE 4 /* Register alignment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ZS_CHAN_IO_OFFSET 1 /* The SCC resides on the high byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) of the 16-bit IOBUS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ZS_CLOCK 7372800 /* Z85C30 PCLK input clock rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define to_zport(uport) container_of(uport, struct zs_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct zs_parms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) resource_size_t scc[ZS_NUM_SCCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int irq[ZS_NUM_SCCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct zs_scc zs_sccs[ZS_NUM_SCCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0, /* write 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PAR_SPEC, /* write 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0, /* write 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0, /* write 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) X16CLK | SB1, /* write 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0, /* write 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0, 0, 0, /* write 6, 7, 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MIE | DLC | NV, /* write 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) NRZ, /* write 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) TCBR | RCBR, /* write 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0, 0, /* BRG time constant, write 12 + 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) BRSRC | BRENABL, /* write 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0, /* write 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #undef ZS_DEBUG_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Reading and writing Z85C30 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void recovery_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static u8 read_zsreg(struct zs_port *zport, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (reg != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writeb(reg & 0xf, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fast_iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) retval = readb(control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void write_zsreg(struct zs_port *zport, int reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (reg != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writeb(reg & 0xf, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) fast_iob(); recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writeb(value, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) fast_iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static u8 read_zsdata(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void __iomem *data = zport->port.membase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) retval = readb(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void write_zsdata(struct zs_port *zport, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __iomem *data = zport->port.membase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeb(value, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fast_iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) recovery_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef ZS_DEBUG_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void zs_dump(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct zs_port *zport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!zport->scc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) for (j = 0; j < 16; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) for (j = 0; j < 16; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) printk("\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_lock_irq(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_unlock_irq(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int zs_receive_drain(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) read_zsdata(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int zs_transmit_drain(struct zs_port *zport, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) zs_spin_unlock_cond_irq(&scc->zlock, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) zs_spin_lock_cond_irq(&scc->zlock, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int zs_line_drain(struct zs_port *zport, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) zs_spin_unlock_cond_irq(&scc->zlock, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) zs_spin_lock_cond_irq(&scc->zlock, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Let the current transmission finish. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) zs_line_drain(zport, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Load 'em up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) write_zsreg(zport, R3, regs[3] & ~RxENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) write_zsreg(zport, R5, regs[5] & ~TxENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) write_zsreg(zport, R4, regs[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) write_zsreg(zport, R9, regs[9]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) write_zsreg(zport, R1, regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) write_zsreg(zport, R2, regs[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) write_zsreg(zport, R10, regs[10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) write_zsreg(zport, R14, regs[14] & ~BRENABL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) write_zsreg(zport, R11, regs[11]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) write_zsreg(zport, R12, regs[12]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) write_zsreg(zport, R13, regs[13]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) write_zsreg(zport, R14, regs[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) write_zsreg(zport, R15, regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (regs[3] & RxENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) write_zsreg(zport, R3, regs[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (regs[5] & TxENAB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) write_zsreg(zport, R5, regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Status handling routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * zs_tx_empty() -- get the transmitter empty status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Purpose: Let user call ioctl() to get info when the UART physically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * is emptied. On bus types like RS485, the transmitter must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * release the bus after transmitting. This must be done when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * the transmit shift register is empty, not be done when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * transmit holding register is empty. This functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * allows an RS485 driver to be written in user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static unsigned int zs_tx_empty(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) status = read_zsreg(zport, R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return status & ALL_SNT ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct zs_port *zport_b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 status_a, status_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) status_a = read_zsreg(zport_a, R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) status_b = read_zsreg(zport_b, R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ((status_b & DCD) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ((status_a & DCD) ? TIOCM_RNG : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int mmask, mctrl, delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 mask_a, mask_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (zport == zport_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mask_a = zport_a->regs[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mask_b = zport->regs[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mctrl = zport->mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (mmask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mctrl &= ~mmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) delta = mctrl ^ zport->mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) zport->mctrl = mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static unsigned int zs_get_mctrl(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mctrl = zs_raw_get_mctrl(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 oldloop, newloop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (zport != zport_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (mctrl & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) zport_a->regs[5] |= DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) zport_a->regs[5] &= ~DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) zport_a->regs[5] |= RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) zport_a->regs[5] &= ~RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) write_zsreg(zport_a, R5, zport_a->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Rarely modified, so don't poke at hardware unless necessary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) oldloop = zport->regs[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) newloop = oldloop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) newloop |= LOOPBAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) newloop &= ~LOOPBAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (newloop != oldloop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) zport->regs[14] = newloop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) write_zsreg(zport, R14, zport->regs[14]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void zs_raw_stop_tx(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) write_zsreg(zport, R0, RES_Tx_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) zport->tx_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void zs_stop_tx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) zs_raw_stop_tx(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void zs_raw_transmit_chars(struct zs_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void zs_start_tx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (zport->tx_stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) zs_transmit_drain(zport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) zport->tx_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) zs_raw_transmit_chars(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void zs_stop_rx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) zport->regs[15] &= ~BRKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) zport->regs[1] |= RxINT_DISAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (zport != zport_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* A-side DCD tracks RI and SYNC tracks DSR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) zport_a->regs[15] &= ~(DCDIE | SYNCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) write_zsreg(zport_a, R15, zport_a->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!(zport_a->regs[15] & BRKIE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) zport_a->regs[1] &= ~EXT_INT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) write_zsreg(zport_a, R1, zport_a->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* This-side DCD tracks DCD and CTS tracks CTS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) zport->regs[15] &= ~(DCDIE | CTSIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) zport->regs[1] &= ~EXT_INT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* DCD tracks RI and SYNC tracks DSR for the B side. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!(zport->regs[15] & (DCDIE | SYNCIE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) zport->regs[1] &= ~EXT_INT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) write_zsreg(zport, R15, zport->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) write_zsreg(zport, R1, zport->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static void zs_enable_ms(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (zport == zport_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Clear Ext interrupts if not being handled already. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!(zport_a->regs[1] & EXT_INT_ENAB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) write_zsreg(zport_a, R0, RES_EXT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* A-side DCD tracks RI and SYNC tracks DSR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) zport_a->regs[1] |= EXT_INT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) zport_a->regs[15] |= DCDIE | SYNCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* This-side DCD tracks DCD and CTS tracks CTS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) zport->regs[15] |= DCDIE | CTSIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) zs_raw_xor_mctrl(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) write_zsreg(zport_a, R1, zport_a->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) write_zsreg(zport_a, R15, zport_a->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) write_zsreg(zport, R15, zport->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void zs_break_ctl(struct uart_port *uport, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) zport->regs[5] |= SND_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) zport->regs[5] &= ~SND_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Interrupt handling routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define Rx_BRK 0x0100 /* BREAK event software flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define Rx_SYS 0x0200 /* SysRq event software flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void zs_receive_chars(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct uart_icount *icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int avail, status, ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (count = 16; count; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) avail = read_zsreg(zport, R0) & Rx_CH_AV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ch = read_zsdata(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) icount = &uport->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) icount->rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Handle the null char got when BREAK is removed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) status |= zport->tty_break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (unlikely(status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) zport->tty_break = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Reset the error indication. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) write_zsreg(zport, R0, ERR_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (status & (Rx_SYS | Rx_BRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) icount->brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* SysRq discards the null char. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (status & Rx_SYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else if (status & FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) icount->frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else if (status & PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) icount->parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (status & Rx_OVR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) icount->overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) status &= uport->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (status & Rx_BRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else if (status & FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) else if (status & PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (uart_handle_sysrq_char(uport, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uart_insert_char(uport, status, Rx_OVR, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) tty_flip_buffer_push(&uport->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void zs_raw_transmit_chars(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct circ_buf *xmit = &zport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* XON/XOFF chars. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (zport->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) write_zsdata(zport, zport->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) zport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) zport->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* If nothing to do or stopped or hardware stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) zs_raw_stop_tx(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Send char. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) write_zsdata(zport, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) zport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) uart_write_wakeup(&zport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Are we are done? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) zs_raw_stop_tx(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void zs_transmit_chars(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) zs_raw_transmit_chars(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u8 status, brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Get status from Read Register 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) status = read_zsreg(zport, R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (zport->regs[15] & BRKIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) brk = status & BRK_ABRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (brk && !zport->brk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (uart_handle_break(uport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) zport->tty_break = Rx_SYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) zport->tty_break = Rx_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) zport->brk = brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (zport != zport_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) delta = zs_raw_xor_mctrl(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (delta & TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) uart_handle_cts_change(uport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) zport->mctrl & TIOCM_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (delta & TIOCM_CAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) uart_handle_dcd_change(uport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) zport->mctrl & TIOCM_CAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (delta & TIOCM_RNG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) uport->icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (delta & TIOCM_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) uport->icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) wake_up_interruptible(&uport->state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Clear the status condition... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) write_zsreg(zport, R0, RES_EXT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * This is the Z85C30 driver's generic interrupt routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static irqreturn_t zs_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct zs_scc *scc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) irqreturn_t status = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 zs_intreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * NOTE: The read register 3, which holds the irq status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * does so for both channels on each chip. Although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * the status value itself must be read from the A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * channel and is only valid when read from channel A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Yes... broken hardware...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) for (count = 16; count; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) spin_lock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) zs_intreg = read_zsreg(zport_a, R3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) spin_unlock(&scc->zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!zs_intreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * We do not like losing characters, so we prioritise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * interrupt sources a little bit differently than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * the SCC would, was it allowed to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (zs_intreg & CHBRxIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) zs_receive_chars(zport_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (zs_intreg & CHARxIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) zs_receive_chars(zport_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (zs_intreg & CHBEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) zs_status_handle(zport_b, zport_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (zs_intreg & CHAEXT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) zs_status_handle(zport_a, zport_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (zs_intreg & CHBTxIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) zs_transmit_chars(zport_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (zs_intreg & CHATxIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) zs_transmit_chars(zport_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Finally, routines used to initialize the serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int zs_startup(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int irq_guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) irq_guard = atomic_add_return(1, &scc->irq_guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (irq_guard == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = request_irq(zport->port.irq, zs_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) IRQF_SHARED, "scc", scc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) atomic_add(-1, &scc->irq_guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) printk(KERN_ERR "zs: can't get irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) zport->port.irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Clear the receive FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) zs_receive_drain(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Clear the interrupt registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) write_zsreg(zport, R0, ERR_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) write_zsreg(zport, R0, RES_Tx_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* But Ext only if not being handled already. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!(zport->regs[1] & EXT_INT_ENAB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) write_zsreg(zport, R0, RES_EXT_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Finally, enable sequencing and interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) zport->regs[1] &= ~RxINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) zport->regs[3] |= RxENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) zport->regs[15] |= BRKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) write_zsreg(zport, R1, zport->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) write_zsreg(zport, R3, zport->regs[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) write_zsreg(zport, R15, zport->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Record the current state of RR0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) zport->mctrl = zs_raw_get_mctrl(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) zport->tx_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void zs_shutdown(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int irq_guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) zport->regs[3] &= ~RxENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) write_zsreg(zport, R3, zport->regs[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) irq_guard = atomic_add_return(-1, &scc->irq_guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!irq_guard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) free_irq(zport->port.irq, scc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void zs_reset(struct zs_port *zport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) irq = !irqs_disabled_flags(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (!scc->initialised) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Reset the pointer first, just in case... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) read_zsreg(zport, R0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* And let the current transmission finish. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) zs_line_drain(zport, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) write_zsreg(zport, R9, FHWRES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) write_zsreg(zport, R9, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) scc->initialised = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) load_zsregs(zport, zport->regs, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned int baud, brg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) irq = !irqs_disabled_flags(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Byte size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) zport->regs[3] &= ~RxNBITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) zport->regs[5] &= ~TxNBITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) zport->regs[3] |= Rx5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) zport->regs[5] |= Tx5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) zport->regs[3] |= Rx6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) zport->regs[5] |= Tx6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) zport->regs[3] |= Rx7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) zport->regs[5] |= Tx7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) zport->regs[3] |= Rx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) zport->regs[5] |= Tx8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Parity and stop bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) zport->regs[4] |= SB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) zport->regs[4] |= SB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) zport->regs[4] |= PAR_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) zport->regs[4] |= PAR_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) switch (zport->clk_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) zport->regs[4] |= X64CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) zport->regs[4] |= X32CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) zport->regs[4] |= X16CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) zport->regs[4] |= X1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) baud = uart_get_baud_rate(uport, termios, old_termios, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) uport->uartclk / zport->clk_mode / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) zport->regs[12] = brg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) zport->regs[13] = (brg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) uart_update_timeout(uport, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) uport->read_status_mask = Rx_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) uport->read_status_mask |= FRM_ERR | PAR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) uport->read_status_mask |= Rx_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uport->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) uport->ignore_status_mask |= Rx_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) uport->ignore_status_mask |= Rx_OVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (termios->c_cflag & CREAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) zport->regs[3] |= RxENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) zport->regs[3] &= ~RxENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (zport != zport_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (!(termios->c_cflag & CLOCAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) zport->regs[15] |= DCDIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) zport->regs[15] &= ~DCDIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) zport->regs[15] |= CTSIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) zport->regs[15] &= ~CTSIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) zs_raw_xor_mctrl(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Load up the new values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) load_zsregs(zport, zport->regs, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Hack alert!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * Required solely so that the initial PROM-based console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * works undisturbed in parallel with this one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static void zs_pm(struct uart_port *uport, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (state < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) zport->regs[5] |= TxENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) zport->regs[5] &= ~TxENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const char *zs_type(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return "Z85C30 SCC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void zs_release_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) iounmap(uport->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) uport->membase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int zs_map_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!uport->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) uport->membase = ioremap(uport->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ZS_CHAN_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!uport->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) printk(KERN_ERR "zs: Cannot map MMIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int zs_request_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = zs_map_port(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static void zs_config_port(struct uart_port *uport, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (zs_request_port(uport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) uport->type = PORT_ZS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) zs_reset(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (ser->irq != uport->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct uart_ops zs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .tx_empty = zs_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .set_mctrl = zs_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .get_mctrl = zs_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .stop_tx = zs_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .start_tx = zs_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .stop_rx = zs_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .enable_ms = zs_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .break_ctl = zs_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .startup = zs_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .shutdown = zs_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .set_termios = zs_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .pm = zs_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .type = zs_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .release_port = zs_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .request_port = zs_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .config_port = zs_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .verify_port = zs_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * Initialize Z85C30 port structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int __init zs_probe_sccs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int probed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct zs_parms zs_parms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int chip, side, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int n_chips = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (probed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) irq = dec_interrupt[DEC_IRQ_SCC0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) zs_parms.scc[n_chips] = IOASIC_SCC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) n_chips++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) irq = dec_interrupt[DEC_IRQ_SCC1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) zs_parms.scc[n_chips] = IOASIC_SCC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) n_chips++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!n_chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) probed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) for (chip = 0; chip < n_chips; chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) spin_lock_init(&zs_sccs[chip].zlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) for (side = 0; side < ZS_NUM_CHAN; side++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct zs_port *zport = &zs_sccs[chip].zport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) zport->scc = &zs_sccs[chip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) zport->clk_mode = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) uport->irq = zs_parms.irq[chip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) uport->uartclk = ZS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) uport->fifosize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) uport->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) uport->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) uport->ops = &zs_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) uport->line = chip * ZS_NUM_CHAN + side;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) uport->mapbase = dec_kn_slot_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) zs_parms.scc[chip] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) for (i = 0; i < ZS_NUM_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) zport->regs[i] = zs_init_regs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #ifdef CONFIG_SERIAL_ZS_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static void zs_console_putchar(struct uart_port *uport, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) struct zs_port *zport = to_zport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) irq = !irqs_disabled_flags(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (zs_transmit_drain(zport, irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) write_zsdata(zport, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * Print a string to the serial port trying not to disturb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * any possible real use of the port...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static void zs_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct zs_port *zport = &zs_sccs[chip].zport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct zs_scc *scc = zport->scc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u8 txint, txenb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Disable transmit interrupts and enable the transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) txint = zport->regs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) txenb = zport->regs[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (txint & TxINT_ENAB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) zport->regs[1] = txint & ~TxINT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) write_zsreg(zport, R1, zport->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!(txenb & TxENAB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) zport->regs[5] = txenb | TxENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) uart_console_write(&zport->port, s, count, zs_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Restore transmit interrupts and the transmitter enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) spin_lock_irqsave(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) irq = !irqs_disabled_flags(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) zs_line_drain(zport, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (!(txenb & TxENAB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) zport->regs[5] &= ~TxENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) write_zsreg(zport, R5, zport->regs[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (txint & TxINT_ENAB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) zport->regs[1] |= TxINT_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) write_zsreg(zport, R1, zport->regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Resume any transmission as the TxIP bit won't be set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!zport->tx_stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) zs_raw_transmit_chars(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) spin_unlock_irqrestore(&scc->zlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * Setup serial console baud/bits/parity. We do two things here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * - construct a cflag setting for the first uart_open()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * - initialise the serial port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * Return non-zero if we didn't find a serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int __init zs_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct zs_port *zport = &zs_sccs[chip].zport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = zs_map_port(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) zs_reset(zport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) zs_pm(uport, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return uart_set_options(uport, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static struct uart_driver zs_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct console zs_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .write = zs_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .setup = zs_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .data = &zs_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Register console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int __init zs_serial_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ret = zs_probe_sccs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) register_console(&zs_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) console_initcall(zs_serial_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define SERIAL_ZS_CONSOLE &zs_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define SERIAL_ZS_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif /* CONFIG_SERIAL_ZS_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static struct uart_driver zs_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .driver_name = "serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .dev_name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .minor = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .nr = ZS_NUM_SCCS * ZS_NUM_CHAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .cons = SERIAL_ZS_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* zs_init inits the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int __init zs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pr_info("%s%s\n", zs_name, zs_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Find out how many Z85C30 SCCs we have. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = zs_probe_sccs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = uart_register_driver(&zs_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (zport->scc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) uart_add_one_port(&zs_reg, uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static void __exit zs_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct uart_port *uport = &zport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (zport->scc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) uart_remove_one_port(&zs_reg, uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) uart_unregister_driver(&zs_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) module_init(zs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) module_exit(zs_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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