^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on msm_serial.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Robert Love <rlove@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * UART Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VT8500_URTDR 0x0000 /* Transmit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VT8500_URRDR 0x0004 /* Receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VT8500_URLCR 0x000C /* Line control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VT8500_URICR 0x0010 /* IrDA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VT8500_URIER 0x0014 /* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VT8500_URISR 0x0018 /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VT8500_URUSR 0x001c /* UART status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VT8500_URFCR 0x0020 /* FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VT8500_URFIDX 0x0024 /* FIFO index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VT8500_URBKR 0x0028 /* Break signal count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VT8500_URTOD 0x002c /* Time out divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Interrupt enable and status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TXDE (1 << 0) /* Tx Data empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RXDF (1 << 1) /* Rx Data full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TXFAE (1 << 2) /* Tx FIFO almost empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TXFE (1 << 3) /* Tx FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RXFAF (1 << 4) /* Rx FIFO almost full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RXFF (1 << 5) /* Rx FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TXUDR (1 << 6) /* Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RXOVER (1 << 7) /* Rx overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PER (1 << 8) /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FER (1 << 9) /* Frame error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TCTS (1 << 10) /* Toggle of CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RXTOUT (1 << 11) /* Rx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BKDONE (1 << 12) /* Break signal done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ERR (1 << 13) /* AHB error response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Line control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VT8500_RXEN (1 << 1) /* Enable receive logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VT8500_PARENB (1 << 4) /* Enable parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VT8500_RTS (1 << 6) /* Ready to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VT8500_BREAK (1 << 9) /* Initiate break signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Capability flags (driver-internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VT8500_RECOMMENDED_CLK 12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VT8500_OVERSAMPLING_DIVISOR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VT8500_MAX_PORTS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct vt8500_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct uart_port uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int clk_predivisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int vt8500_uart_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * we use this variable to keep track of which ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * have been allocated as we can't use pdev->id in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * devicetree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void vt8500_write(struct uart_port *port, unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(val, port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return readl(port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void vt8500_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct vt8500_port *vt8500_port = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct vt8500_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vt8500_port->ier &= ~TX_FIFO_INTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) vt8500_write(port, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void vt8500_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct vt8500_port *vt8500_port = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct vt8500_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) vt8500_port->ier &= ~RX_FIFO_INTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) vt8500_write(port, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void vt8500_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct vt8500_port *vt8500_port = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct vt8500_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) vt8500_port->ier |= TCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) vt8500_write(port, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void handle_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Handle overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* and now the main RX loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Mask conditions we're ignorning. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) c &= ~port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (c & FER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } else if (c & PER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!uart_handle_sysrq_char(port, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tty_insert_flip_char(tport, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void handle_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writeb(port->x_char, port->membase + VT8500_TXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vt8500_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) vt8500_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void vt8500_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct vt8500_port *vt8500_port = container_of(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct vt8500_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) vt8500_port->ier &= ~TX_FIFO_INTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vt8500_write(port, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) handle_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) vt8500_port->ier |= TX_FIFO_INTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) vt8500_write(port, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void handle_delta_cts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) port->icount.cts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) wake_up_interruptible(&port->state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static irqreturn_t vt8500_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) isr = vt8500_read(port, VT8500_URISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Acknowledge active status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) vt8500_write(port, isr, VT8500_URISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (isr & RX_FIFO_INTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) handle_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (isr & TX_FIFO_INTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) handle_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (isr & TCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) handle_delta_cts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static unsigned int vt8500_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static unsigned int vt8500_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) usr = vt8500_read(port, VT8500_URUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (usr & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int lcr = vt8500_read(port, VT8500_URLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) lcr |= VT8500_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) lcr &= ~VT8500_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) vt8500_write(port, lcr, VT8500_URLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (break_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) vt8500_write(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) VT8500_URLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct vt8500_port *vt8500_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) container_of(port, struct vt8500_port, uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int loops = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Effective baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) vt8500_write(port, div, VT8500_URDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Break signal timing depends on baud rate, update accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int vt8500_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct vt8500_port *vt8500_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) container_of(port, struct vt8500_port, uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) snprintf(vt8500_port->name, sizeof(vt8500_port->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "vt8500_serial%d", port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) vt8500_port->name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void vt8500_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct vt8500_port *vt8500_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) container_of(port, struct vt8500_port, uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) vt8500_port->ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* disable interrupts and FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void vt8500_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct vt8500_port *vt8500_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) container_of(port, struct vt8500_port, uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int baud, lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int loops = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* calculate and set baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) baud = uart_get_baud_rate(port, termios, old, 900, 921600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) baud = vt8500_set_baud_rate(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* calculate parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) lcr &= ~(VT8500_PARENB | VT8500_PARODD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) lcr |= VT8500_PARENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) termios->c_cflag &= ~CMSPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) lcr |= VT8500_PARODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* calculate bits per char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lcr &= ~VT8500_CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lcr |= VT8500_CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) termios->c_cflag &= ~CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) termios->c_cflag |= CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* calculate stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lcr &= ~VT8500_CSTOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lcr |= VT8500_CSTOPB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) lcr &= ~VT8500_SWRTSCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lcr |= VT8500_SWRTSCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* set parity, bits per char, and stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Configure status bits to ignore based on termio flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) port->read_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) port->read_status_mask = FER | PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Reset FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Every possible FIFO-related interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * CTS flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) vt8500_port->ier |= TCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char *vt8500_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct vt8500_port *vt8500_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) container_of(port, struct vt8500_port, uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return vt8500_port->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void vt8500_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int vt8500_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static void vt8500_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) port->type = PORT_VT8500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int vt8500_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (unlikely(port->irq != ser->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct uart_driver vt8500_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #ifdef CONFIG_SERIAL_VT8500_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void wait_for_xmitr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Wait up to 10ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) status = vt8500_read(port, VT8500_URFIDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } while (status & 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static void vt8500_console_putchar(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writeb(c, port->membase + VT8500_TXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void vt8500_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) uart_console_write(&vt8500_port->uart, s, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) vt8500_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * and switch back to FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) wait_for_xmitr(&vt8500_port->uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int __init vt8500_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct vt8500_port *vt8500_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) vt8500_port = vt8500_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!vt8500_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return uart_set_options(&vt8500_port->uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static struct console vt8500_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .name = "ttyWMT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .write = vt8500_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .setup = vt8500_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .data = &vt8500_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define VT8500_CONSOLE (&vt8500_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define VT8500_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int vt8500_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int status = vt8500_read(port, VT8500_URFIDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!(status & 0x1f00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return vt8500_read(port, VT8500_RXFIFO) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) status = vt8500_read(port, VT8500_URFIDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } while (status & 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) vt8500_write(port, c, VT8500_TXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const struct uart_ops vt8500_uart_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .tx_empty = vt8500_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .set_mctrl = vt8500_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .get_mctrl = vt8500_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .stop_tx = vt8500_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .start_tx = vt8500_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .stop_rx = vt8500_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .enable_ms = vt8500_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .break_ctl = vt8500_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .startup = vt8500_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .shutdown = vt8500_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .set_termios = vt8500_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .type = vt8500_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .release_port = vt8500_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .request_port = vt8500_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .config_port = vt8500_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .verify_port = vt8500_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .poll_get_char = vt8500_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .poll_put_char = vt8500_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static struct uart_driver vt8500_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .driver_name = "vt8500_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .dev_name = "ttyWMT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .nr = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .cons = VT8500_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static unsigned int vt8500_flags; /* none required so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct of_device_id wmt_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int vt8500_serial_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct vt8500_port *vt8500_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct resource *mmres, *irqres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const unsigned int *flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) match = of_match_device(wmt_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) flags = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!mmres || !irqres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) port = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (port >= VT8500_MAX_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (port < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* calculate the port id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) port = find_first_zero_bit(vt8500_ports_in_use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) VT8500_MAX_PORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (port >= VT8500_MAX_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* reserve the port id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (test_and_set_bit(port, vt8500_ports_in_use)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* port already in use - shouldn't really happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!vt8500_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (IS_ERR(vt8500_port->uart.membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return PTR_ERR(vt8500_port->uart.membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (IS_ERR(vt8500_port->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = clk_prepare_enable(vt8500_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(&pdev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) vt8500_port->vt8500_uart_flags = *flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) clk_get_rate(vt8500_port->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) VT8500_RECOMMENDED_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) vt8500_port->uart.type = PORT_VT8500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) vt8500_port->uart.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) vt8500_port->uart.mapbase = mmres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) vt8500_port->uart.irq = irqres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) vt8500_port->uart.fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) vt8500_port->uart.ops = &vt8500_uart_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) vt8500_port->uart.line = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) vt8500_port->uart.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Serial core uses the magic "16" everywhere - adjust for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) vt8500_port->clk_predivisor /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) VT8500_OVERSAMPLING_DIVISOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) snprintf(vt8500_port->name, sizeof(vt8500_port->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "VT8500 UART%d", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) vt8500_uart_ports[port] = vt8500_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) platform_set_drvdata(pdev, vt8500_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct platform_driver vt8500_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .probe = vt8500_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .name = "vt8500_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .of_match_table = wmt_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int __init vt8500_serial_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = uart_register_driver(&vt8500_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = platform_driver_register(&vt8500_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) uart_unregister_driver(&vt8500_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) device_initcall(vt8500_serial_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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