^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * uartlite.c: Serial driver for Xilinx uartlite serial controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Secret Lab Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ULITE_NAME "ttyUL"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ULITE_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ULITE_MINOR 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * For register details see datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ULITE_RX 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ULITE_TX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ULITE_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ULITE_CONTROL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ULITE_REGION 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ULITE_STATUS_RXVALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ULITE_STATUS_RXFULL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ULITE_STATUS_TXEMPTY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ULITE_STATUS_TXFULL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ULITE_STATUS_IE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ULITE_STATUS_OVERRUN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ULITE_STATUS_FRAME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ULITE_STATUS_PARITY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ULITE_CONTROL_RST_TX 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ULITE_CONTROL_RST_RX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ULITE_CONTROL_IE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Static pointer to console port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct uart_port *console_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct uartlite_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct uartlite_reg_ops *reg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct uartlite_reg_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 (*in)(void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void (*out)(u32 val, void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u32 uartlite_inbe32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ioread32be(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void uartlite_outbe32(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) iowrite32be(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct uartlite_reg_ops uartlite_be = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .in = uartlite_inbe32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .out = uartlite_outbe32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u32 uartlite_inle32(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void uartlite_outle32(u32 val, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite32(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct uartlite_reg_ops uartlite_le = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .in = uartlite_inle32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .out = uartlite_outle32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u32 uart_in32(u32 offset, struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return pdata->reg_ops->in(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pdata->reg_ops->out(val, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct uart_port ulite_ports[ULITE_NR_UARTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Core UART driver operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ulite_receive(struct uart_port *port, int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned char ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | ULITE_STATUS_FRAME)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (stat & ULITE_STATUS_RXVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ch = uart_in32(ULITE_RX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (stat & ULITE_STATUS_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (stat & ULITE_STATUS_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (stat & ULITE_STATUS_FRAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* drop byte with parity error if IGNPAR specificed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) stat &= ~ULITE_STATUS_RXVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) stat &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (stat & ULITE_STATUS_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) stat &= ~port->ignore_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (stat & ULITE_STATUS_RXVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tty_insert_flip_char(tport, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (stat & ULITE_STATUS_FRAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tty_insert_flip_char(tport, 0, TTY_FRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (stat & ULITE_STATUS_OVERRUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int ulite_transmit(struct uart_port *port, int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (stat & ULITE_STATUS_TXFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uart_out32(port->x_char, ULITE_TX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (uart_circ_empty(xmit) || uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t ulite_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int stat, busy, n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) stat = uart_in32(ULITE_STATUS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) busy = ulite_receive(port, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) busy |= ulite_transmit(port, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } while (busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* work done? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (n > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static unsigned int ulite_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = uart_in32(ULITE_STATUS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static unsigned int ulite_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* N/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void ulite_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* N/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void ulite_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ulite_transmit(port, uart_in32(ULITE_STATUS, port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void ulite_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* don't forward any more data (like !CREAD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void ulite_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* N/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int ulite_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ret = clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(port->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "uartlite", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void ulite_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uart_out32(0, ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uart_in32(ULITE_CONTROL, port); /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) | ULITE_STATUS_TXFULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) port->read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) port->ignore_status_mask |= ULITE_STATUS_PARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* ignore all characters if CREAD is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) port->ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* update timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) baud = uart_get_baud_rate(port, termios, old, 0, 460800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const char *ulite_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return port->type == PORT_UARTLITE ? "uartlite" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void ulite_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) release_mem_region(port->mapbase, ULITE_REGION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ulite_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) port, (unsigned long long) port->mapbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(port->dev, "Memory region busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) port->membase = ioremap(port->mapbase, ULITE_REGION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!port->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(port->dev, "Unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) release_mem_region(port->mapbase, ULITE_REGION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pdata->reg_ops = &uartlite_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = uart_in32(ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = uart_in32(ULITE_STATUS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Endianess detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pdata->reg_ops = &uartlite_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void ulite_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!ulite_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) port->type = PORT_UARTLITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* we don't want the core code to modify any port params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void ulite_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int ulite_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return uart_in32(ULITE_RX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* write char to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) uart_out32(ch, ULITE_TX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct uart_ops ulite_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .tx_empty = ulite_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .set_mctrl = ulite_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .get_mctrl = ulite_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .stop_tx = ulite_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .start_tx = ulite_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .stop_rx = ulite_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .break_ctl = ulite_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .startup = ulite_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .shutdown = ulite_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .set_termios = ulite_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .type = ulite_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .release_port = ulite_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .request_port = ulite_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .config_port = ulite_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .verify_port = ulite_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pm = ulite_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .poll_get_char = ulite_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .poll_put_char = ulite_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Console driver operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void ulite_console_wait_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Spin waiting for TX fifo to have space available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * When using the Microblaze Debug Module this can take up to 1s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val = uart_in32(ULITE_STATUS, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if ((val & ULITE_STATUS_TXFULL) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_warn(port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "timeout waiting for TX buffer empty\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void ulite_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ulite_console_wait_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uart_out32(ch, ULITE_TX, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void ulite_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct uart_port *port = console_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (oops_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) locked = spin_trylock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* save and disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) uart_out32(0, ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uart_console_write(port, s, count, ulite_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ulite_console_wait_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* restore interrupt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int ulite_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct uart_port *port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (co->index >= 0 && co->index < ULITE_NR_UARTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) port = ulite_ports + co->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Has the device been initialized yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!port || !port->mapbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pr_debug("console on ttyUL%i not present\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) console_port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* not initialized yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!port->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ulite_request_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct uart_driver ulite_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct console ulite_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = ULITE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .write = ulite_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .setup = ulite_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .data = &ulite_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void early_uartlite_putc(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Limit how many times we'll spin waiting for TX FIFO status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * This will prevent lockups if the base address is incorrectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * set, or any other issue on the UARTLITE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * This limit is pretty arbitrary, unless we are at about 10 baud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * we'll never timeout on a working UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned retries = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* read status bit - 0x8 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) while (--retries && (readl(port->membase + 8) & (1 << 3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Only attempt the iowrite if we didn't timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* write to TX_FIFO - 0x4 offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) writel(c & 0xff, port->membase + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void early_uartlite_write(struct console *console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct earlycon_device *device = console->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) uart_console_write(&device->port, s, n, early_uartlite_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int __init early_uartlite_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) const char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) device->con->write = early_uartlite_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) EARLYCON_DECLARE(uartlite, early_uartlite_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct uart_driver ulite_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .driver_name = "uartlite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .dev_name = ULITE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .major = ULITE_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .minor = ULITE_MINOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .nr = ULITE_NR_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .cons = &ulite_console,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Port assignment functions (mapping devices to uart_port structures)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /** ulite_assign: register a uartlite device with the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * @dev: pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * @id: requested id number. Pass -1 for automatic port assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * @base: base address of uartlite registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * @irq: irq number for uartlite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * @pdata: private data for uartlite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Returns: 0 on success, <0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct uartlite_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* if id = -1; then scan for a free id and use that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) for (id = 0; id < ULITE_NR_UARTS; id++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ulite_ports[id].mapbase == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (id < 0 || id >= ULITE_NR_UARTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev, "cannot assign to %s%i; it is already in use\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ULITE_NAME, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) port = &ulite_ports[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) port->fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) port->regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) port->iobase = 1; /* mark port in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) port->mapbase = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) port->ops = &ulite_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) port->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) port->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) port->type = PORT_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) port->line = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) port->private_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_set_drvdata(dev, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Register the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rc = uart_add_one_port(&ulite_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) port->mapbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /** ulite_release: register a uartlite device with the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @dev: pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int ulite_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rc = uart_remove_one_port(&ulite_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_set_drvdata(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) port->mapbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * ulite_suspend - Stop the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * @dev: handle to the device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Return: 0 always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int __maybe_unused ulite_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) uart_suspend_port(&ulite_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * ulite_resume - Resume the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @dev: handle to the device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * Return: 0 on success, errno otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int __maybe_unused ulite_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) uart_resume_port(&ulite_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * Platform bus binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static SIMPLE_DEV_PM_OPS(ulite_pm_ops, ulite_suspend, ulite_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Match table for of_platform binding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const struct of_device_id ulite_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { .compatible = "xlnx,opb-uartlite-1.00.b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { .compatible = "xlnx,xps-uartlite-1.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) MODULE_DEVICE_TABLE(of, ulite_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int ulite_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct uartlite_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) const __be32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) id = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (PTR_ERR(pdata->clk) != -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return PTR_ERR(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Clock framework support is optional, continue on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * anyways if we don't find a matching clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pdata->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(&pdev->dev, "Failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!ulite_uart_driver.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = uart_register_driver(&ulite_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_err(&pdev->dev, "Failed to register driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int ulite_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct uart_port *port = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct uartlite_data *pdata = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return ulite_release(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MODULE_ALIAS("platform:uartlite");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct platform_driver ulite_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .probe = ulite_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .remove = ulite_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .name = "uartlite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .of_match_table = of_match_ptr(ulite_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .pm = &ulite_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * Module setup/teardown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int __init ulite_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) pr_debug("uartlite: calling platform_driver_register()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return platform_driver_register(&ulite_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void __exit ulite_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) platform_driver_unregister(&ulite_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ulite_uart_driver.state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) uart_unregister_driver(&ulite_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) module_init(ulite_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) module_exit(ulite_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_DESCRIPTION("Xilinx uartlite serial driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags