^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TCU_MBOX_BYTE(i, x) ((x) << (i * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TCU_MBOX_BYTE_V(x, i) (((x) >> (i * 8)) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TCU_MBOX_NUM_BYTES(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TCU_MBOX_NUM_BYTES_V(x) (((x) >> 24) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct tegra_tcu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct uart_driver driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct console console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mbox_client tx_client, rx_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mbox_chan *tx, *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned int tegra_tcu_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void tegra_tcu_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned int tegra_tcu_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void tegra_tcu_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void tegra_tcu_write_one(struct tegra_tcu *tcu, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) value |= TCU_MBOX_NUM_BYTES(count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) msg = (void *)(unsigned long)value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mbox_send_message(tcu->tx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mbox_flush(tcu->tx, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void tegra_tcu_write(struct tegra_tcu *tcu, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int written = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool insert_nl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (i < count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (insert_nl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) value |= TCU_MBOX_BYTE(written++, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) insert_nl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } else if (s[i] == '\n') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) value |= TCU_MBOX_BYTE(written++, '\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) insert_nl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value |= TCU_MBOX_BYTE(written++, s[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (written == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tegra_tcu_write_one(tcu, value, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) value = written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (written)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tegra_tcu_write_one(tcu, value, written);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void tegra_tcu_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct tegra_tcu *tcu = port->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tegra_tcu_write(tcu, &xmit->buf[xmit->tail], count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void tegra_tcu_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void tegra_tcu_uart_break_ctl(struct uart_port *port, int ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int tegra_tcu_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void tegra_tcu_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void tegra_tcu_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct uart_ops tegra_tcu_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .tx_empty = tegra_tcu_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .set_mctrl = tegra_tcu_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .get_mctrl = tegra_tcu_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .stop_tx = tegra_tcu_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .start_tx = tegra_tcu_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .stop_rx = tegra_tcu_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .break_ctl = tegra_tcu_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .startup = tegra_tcu_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .shutdown = tegra_tcu_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .set_termios = tegra_tcu_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void tegra_tcu_console_write(struct console *cons, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct tegra_tcu *tcu = container_of(cons, struct tegra_tcu, console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tegra_tcu_write(tcu, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int tegra_tcu_console_setup(struct console *cons, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void tegra_tcu_receive(struct mbox_client *cl, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct tegra_tcu *tcu = container_of(cl, struct tegra_tcu, rx_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct tty_port *port = &tcu->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 value = (u32)(unsigned long)msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int num_bytes, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) num_bytes = TCU_MBOX_NUM_BYTES_V(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < num_bytes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tty_insert_flip_char(port, TCU_MBOX_BYTE_V(value, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int tegra_tcu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct tegra_tcu *tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tcu = devm_kzalloc(&pdev->dev, sizeof(*tcu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!tcu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tcu->tx_client.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tcu->rx_client.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tcu->rx_client.rx_callback = tegra_tcu_receive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tcu->tx = mbox_request_channel_byname(&tcu->tx_client, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (IS_ERR(tcu->tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) err = PTR_ERR(tcu->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(&pdev->dev, "failed to get tx mailbox: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tcu->rx = mbox_request_channel_byname(&tcu->rx_client, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ERR(tcu->rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = PTR_ERR(tcu->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&pdev->dev, "failed to get rx mailbox: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) goto free_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* setup the console */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) strcpy(tcu->console.name, "ttyTCU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tcu->console.device = uart_console_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tcu->console.flags = CON_PRINTBUFFER | CON_ANYTIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tcu->console.index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tcu->console.write = tegra_tcu_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tcu->console.setup = tegra_tcu_console_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tcu->console.data = &tcu->driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* setup the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tcu->driver.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tcu->driver.driver_name = "tegra-tcu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tcu->driver.dev_name = "ttyTCU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tcu->driver.cons = &tcu->console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tcu->driver.nr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) err = uart_register_driver(&tcu->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(&pdev->dev, "failed to register UART driver: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) goto free_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* setup the port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) port = &tcu->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) port->type = PORT_TEGRA_TCU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) port->ops = &tegra_tcu_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) port->fifosize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) port->private_data = tcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) err = uart_add_one_port(&tcu->driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(&pdev->dev, "failed to add UART port: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto unregister_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) platform_set_drvdata(pdev, tcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) register_console(&tcu->console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unregister_uart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) uart_unregister_driver(&tcu->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) free_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mbox_free_channel(tcu->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) free_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mbox_free_channel(tcu->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int tegra_tcu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct tegra_tcu *tcu = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #if IS_ENABLED(CONFIG_SERIAL_TEGRA_TCU_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unregister_console(&tcu->console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uart_remove_one_port(&tcu->driver, &tcu->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uart_unregister_driver(&tcu->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mbox_free_channel(tcu->rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mbox_free_channel(tcu->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct of_device_id tegra_tcu_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { .compatible = "nvidia,tegra194-tcu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct platform_driver tegra_tcu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .name = "tegra-tcu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .of_match_table = tegra_tcu_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .probe = tegra_tcu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .remove = tegra_tcu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) module_platform_driver(tegra_tcu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DESCRIPTION("NVIDIA Tegra Combined UART driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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