^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SUNZILOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SUNZILOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct zilog_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) volatile unsigned char control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) volatile unsigned char __pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) volatile unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) volatile unsigned char __pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct zilog_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct zilog_channel channelB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct zilog_channel channelA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NUM_ZSREGS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R7p 16 /* Written as R7 with P15 bit 0 set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Conversion routines to/from brg time constants from/to bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* The Zilog register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FLAG 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Write Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R0 0 /* Register selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NULLCODE 0 /* Null Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define POINT_HIGH 0x8 /* Select upper half of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SEND_ABORT 0x18 /* HDLC Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RES_Tx_P 0x28 /* Reset TxINT Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ERR_RES 0x30 /* Error Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RES_H_IUS 0x38 /* Reset highest IUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RES_EOM_L 0xC0 /* Reset EOM latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Write Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TxINT_ENAB 0x2 /* Tx Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PAR_SPEC 0x4 /* Parity is special condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RxINT_DISAB 0 /* Rx Int Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define INT_ERR_Rx 0x18 /* Int on error only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RxINT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Write Register #2 (Interrupt Vector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Write Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RxENAB 0x1 /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ENT_HM 0x10 /* Enter Hunt Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AUTO_ENAB 0x20 /* Auto Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define Rx5 0x0 /* Rx 5 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define Rx7 0x40 /* Rx 7 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define Rx6 0x80 /* Rx 6 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define Rx8 0xc0 /* Rx 8 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RxN_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Write Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PAR_ENAB 0x1 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PAR_EVEN 0x2 /* Parity Even/Odd* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SYNC_ENAB 0 /* Sync Modes Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SB1 0x4 /* 1 stop bit/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SB15 0x8 /* 1.5 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SB2 0xc /* 2 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MONSYNC 0 /* 8 Bit Sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BISYNC 0x10 /* 16 bit sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EXTSYNC 0x30 /* External Sync Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define X1CLK 0x0 /* x1 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define X16CLK 0x40 /* x16 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define X32CLK 0x80 /* x32 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define X64CLK 0xC0 /* x64 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XCLK_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Write Register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RTS 0x2 /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TxENAB 0x8 /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SND_BRK 0x10 /* Send Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define Tx5 0x0 /* Tx 5 bits (or less)/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define Tx7 0x20 /* Tx 7 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define Tx6 0x40 /* Tx 6 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define Tx8 0x60 /* Tx 8 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TxN_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DTR 0x80 /* DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Write Register 7' (ESCC Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AUTO_TxFLAG 1 /* Automatic Tx SDLC Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AUTO_EOM_RST 2 /* Automatic EOM Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AUTOnRTS 4 /* Automatic /RTS pin deactivation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RxFIFO_LVL 8 /* Receive FIFO interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define nDTRnREQ 0x10 /* /DTR/REQ timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TxFIFO_LVL 0x20 /* Transmit FIFO interrupt level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EXT_RD_EN 0x40 /* Extended read register enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Write Register 8 (transmit buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Write Register 9 (Master interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VIS 1 /* Vector Includes Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NV 2 /* No Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DLC 4 /* Disable Lower Chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MIE 8 /* Master Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define STATHI 0x10 /* Status high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SWIACK 0x20 /* Software Interrupt Ack (not on NMOS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define NORESET 0 /* No reset on write to R9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CHRB 0x40 /* Reset channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CHRA 0x80 /* Reset channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FHWRES 0xc0 /* Force hardware reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Write Register 10 (misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BIT6 1 /* 6 bit/8bit sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LOOPMODE 2 /* SDLC Loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MARKIDLE 8 /* Mark/flag on idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GAOP 0x10 /* Go active on poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NRZ 0 /* NRZ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NRZI 0x20 /* NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FM1 0x40 /* FM1 (transition = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FM0 0x60 /* FM0 (transition = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CRCPS 0x80 /* CRC Preset I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Write Register 11 (Clock Mode control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TRxCXT 0 /* TRxC = Xtal output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TRxCTC 1 /* TRxC = Transmit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TRxCBR 2 /* TRxC = BR Generator Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TRxCDP 3 /* TRxC = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TRxCOI 4 /* TRxC O/I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TCRTxCP 0 /* Transmit clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TCTRxCP 8 /* Transmit clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TCBR 0x10 /* Transmit clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TCDPLL 0x18 /* Transmit clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RCRTxCP 0 /* Receive clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RCBR 0x40 /* Receive clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RCDPLL 0x60 /* Receive clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Write Register 12 (lower byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Write Register 13 (upper byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Write Register 14 (Misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BRENAB 1 /* Baud rate generator enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BRSRC 2 /* Baud rate generator source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DTRREQ 4 /* DTR/Request function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AUTOECHO 8 /* Auto Echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LOOPBAK 0x10 /* Local loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SEARCH 0x20 /* Enter search mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RMC 0x40 /* Reset missing clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DISDPLL 0x60 /* Disable DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SSBR 0x80 /* Set DPLL source = BR generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SFMM 0xc0 /* Set FM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SNRZI 0xe0 /* Set NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Write Register 15 (external/status interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define WR7pEN 1 /* WR7' Enable (ESCC only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ZCIE 2 /* Zero count IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FIFOEN 4 /* FIFO Enable (ESCC only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DCDIE 8 /* DCD IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SYNCIE 0x10 /* Sync/hunt IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CTSIE 0x20 /* CTS IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TxUIE 0x40 /* Tx Underrun/EOM IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BRKIE 0x80 /* Break/Abort IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Read Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define Rx_CH_AV 0x1 /* Rx Character Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ZCOUNT 0x2 /* Zero count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DCD 0x8 /* DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SYNC 0x10 /* Sync/hunt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CTS 0x20 /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TxEOM 0x40 /* Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BRK_ABRT 0x80 /* Break/Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Read Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define ALL_SNT 0x1 /* All sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Residue Data for 8 Rx bits/char programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RES3 0x8 /* 0/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RES4 0x4 /* 0/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RES5 0xc /* 0/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RES6 0x2 /* 0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RES7 0xa /* 0/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RES8 0x6 /* 0/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RES18 0xe /* 1/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RES28 0x0 /* 2/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Special Rx Condition Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PAR_ERR 0x10 /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define Rx_OVR 0x20 /* Rx Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CRC_ERR 0x40 /* CRC/Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define END_FR 0x80 /* End of Frame (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Read Register 2 (channel b only) - Interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CHB_Tx_EMPTY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CHB_EXT_STAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CHB_Rx_AVAIL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CHB_SPECIAL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CHA_Tx_EMPTY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CHA_EXT_STAT 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CHA_Rx_AVAIL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CHA_SPECIAL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STATUS_MASK 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Read Register 3 (interrupt pending register) ch a only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CHBTxIP 0x2 /* Channel B Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CHBRxIP 0x4 /* Channel B Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CHATxIP 0x10 /* Channel A Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CHARxIP 0x20 /* Channel A Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Read Register 6 (LSB frame byte count [Not on NMOS]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Read Register 7 (MSB frame byte count and FIFO status [Not on NMOS]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Read Register 8 (receive data register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Read Register 10 (misc status bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ONLOOP 2 /* On loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LOOPSEND 0x10 /* Loop sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK2MIS 0x40 /* Two clocks missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK1MIS 0x80 /* One clock missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Read Register 12 (lower byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Read Register 13 (upper byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Read Register 15 (value of WR 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Misc macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) udelay(5); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) udelay(5); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) udelay(2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sbus_readb(&channel->data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udelay(2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sbus_readb(&channel->data); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) udelay(2); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif /* _SUNZILOG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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