^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Maxim Krasnyanskiy <maxk@qualcomm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * rates to be programmed into the UART. Also eliminated a lot of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * duplicated code in the console setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Ported to new 2.5.x UART layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * David S. Miller <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/sunserialcore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "sunsab.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct uart_sunsab_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct uart_port port; /* Generic UART port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) union sab82532_async_regs __iomem *regs; /* Chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long irqflags; /* IRQ state flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int dsr; /* Current DSR state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int cec_timeout; /* Chip poll timeout... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int tec_timeout; /* likewise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned char interrupt_mask0;/* ISR0 masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char interrupt_mask1;/* ISR1 masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int gis_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int type; /* SAB82532 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Setting configuration bits while the transmitter is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * can cause garbage characters to get emitted by the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Therefore, we cache such writes here and do the real register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * write the next time the transmitter becomes idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int cached_ebrg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned char cached_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned char cached_pvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned char cached_dafo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * This assumes you have a 29.4912 MHz clock for your UART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SAB_BASE_BAUD ( 29491200 / 16 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static char *sab82532_version[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "V1.0", "V2.0", "V3.2", "V(0x03)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SAB82532_XMIT_FIFO_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int timeout = up->tec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int timeout = up->cec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct tty_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) receive_chars(struct uart_sunsab_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) union sab82532_irq_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct tty_port *port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char buf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int saw_console_brk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int free_fifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (up->port.state != NULL) /* Unopened serial console */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) port = &up->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Read number of BYTES (Character + Status) available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) count = SAB82532_RECV_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) free_fifo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) free_fifo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Issue a FIFO read command in case we where idle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) free_fifo++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Read the FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) buf[i] = readb(&up->regs->r.rfifo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Issue Receive Message Complete command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (free_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Count may be zero for BRK, so we check for it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (up->port.line == up->port.cons->index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) saw_console_brk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SAB82532_ISR0_FERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) up->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) uart_handle_break(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned char ch = buf[i], flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SAB82532_ISR0_FERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SAB82532_ISR0_RFO)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * For statistics only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SAB82532_ISR0_FERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) up->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * We do the SysRQ and SAK checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * here because otherwise the break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * may get masked by ignore_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * or read_status_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (uart_handle_break(&up->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) up->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) up->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) up->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Mask off conditions which should be ingored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (uart_handle_sysrq_char(&up->port, ch) || !port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tty_insert_flip_char(port, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tty_insert_flip_char(port, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (saw_console_brk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sun_do_break();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void sunsab_stop_tx(struct uart_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void sunsab_tx_idle(struct uart_sunsab_port *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void transmit_chars(struct uart_sunsab_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) union sab82532_irq_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) set_bit(SAB82532_ALLS, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #if 0 /* bde@nwlink.com says this check causes problems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) set_bit(SAB82532_XPR, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sunsab_tx_idle(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) up->interrupt_mask1 |= SAB82532_IMR1_XPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clear_bit(SAB82532_ALLS, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Stuff 32 bytes into Transmit FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clear_bit(SAB82532_XPR, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (i = 0; i < up->port.fifosize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writeb(xmit->buf[xmit->tail],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &up->regs->w.xfifo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Issue a Transmit Frame command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) uart_write_wakeup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sunsab_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void check_status(struct uart_sunsab_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) union sab82532_irq_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uart_handle_dcd_change(&up->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uart_handle_cts_change(&up->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) up->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) wake_up_interruptible(&up->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct uart_sunsab_port *up = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct tty_port *port = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) union sab82532_irq_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned char gis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) status.stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) gis = readb(&up->regs->r.gis) >> up->gis_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (gis & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) status.sreg.isr0 = readb(&up->regs->r.isr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (gis & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) status.sreg.isr1 = readb(&up->regs->r.isr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (status.stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (status.sreg.isr1 & SAB82532_ISR1_BRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) port = receive_chars(up, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (status.sreg.isr1 & SAB82532_ISR1_CSC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) check_status(up, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) transmit_chars(up, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static unsigned int sunsab_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Do not need a lock for a state test like this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (test_bit(SAB82532_ALLS, &up->irqflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* port->lock held by caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (mctrl & TIOCM_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) up->cached_mode &= ~SAB82532_MODE_FRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) up->cached_mode |= SAB82532_MODE_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) up->cached_mode |= (SAB82532_MODE_FRTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SAB82532_MODE_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (mctrl & TIOCM_DTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) up->cached_pvr &= ~(up->pvr_dtr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) up->cached_pvr |= up->pvr_dtr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) set_bit(SAB82532_REGS_PENDING, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (test_bit(SAB82532_XPR, &up->irqflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sunsab_tx_idle(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* port->lock is held by caller and interrupts are disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static unsigned int sunsab_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val = readb(&up->regs->r.pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val = readb(&up->regs->r.vstr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val = readb(&up->regs->r.star);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* port->lock held by caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void sunsab_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) up->interrupt_mask1 |= SAB82532_IMR1_XPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* port->lock held by caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void sunsab_tx_idle(struct uart_sunsab_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writeb(up->cached_mode, &up->regs->rw.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writeb(up->cached_pvr, &up->regs->rw.pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writeb(up->cached_dafo, &up->regs->w.dafo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tmp = readb(&up->regs->rw.ccr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tmp &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tmp |= (up->cached_ebrg >> 2) & 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) writeb(tmp, &up->regs->rw.ccr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* port->lock held by caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void sunsab_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (uart_circ_empty(xmit) || uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!test_bit(SAB82532_XPR, &up->irqflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clear_bit(SAB82532_ALLS, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clear_bit(SAB82532_XPR, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (i = 0; i < up->port.fifosize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writeb(xmit->buf[xmit->tail],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &up->regs->w.xfifo[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Issue a Transmit Frame command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void sunsab_send_xchar(struct uart_port *port, char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ch == __DISABLED_CHAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) sunsab_tec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writeb(ch, &up->regs->w.tic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* port->lock held by caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void sunsab_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) up->interrupt_mask0 |= SAB82532_IMR0_TCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writeb(up->interrupt_mask1, &up->regs->w.imr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void sunsab_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val = up->cached_dafo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val |= SAB82532_DAFO_XBRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val &= ~SAB82532_DAFO_XBRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) up->cached_dafo = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) set_bit(SAB82532_REGS_PENDING, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (test_bit(SAB82532_XPR, &up->irqflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sunsab_tx_idle(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int sunsab_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int err = request_irq(up->port.irq, sunsab_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) IRQF_SHARED, "sab", up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Wait for any commands or immediate characters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sunsab_tec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Clear the FIFO buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) sunsab_cec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Clear the interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (void) readb(&up->regs->r.isr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) (void) readb(&up->regs->r.isr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Now, initialize the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writeb(0, &up->regs->w.ccr0); /* power-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SAB82532_CCR2_TOE, &up->regs->w.ccr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) writeb(0, &up->regs->w.ccr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SAB82532_MODE_RAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) writeb(up->cached_mode, &up->regs->w.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tmp = readb(&up->regs->rw.ccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tmp |= SAB82532_CCR0_PU; /* power-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writeb(tmp, &up->regs->rw.ccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Finally, enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SAB82532_IMR0_PLLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) writeb(up->interrupt_mask0, &up->regs->w.imr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SAB82532_IMR1_XPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) set_bit(SAB82532_ALLS, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) set_bit(SAB82532_XPR, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static void sunsab_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Disable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) up->interrupt_mask0 = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) writeb(up->interrupt_mask0, &up->regs->w.imr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) up->interrupt_mask1 = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Disable break condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) up->cached_dafo = readb(&up->regs->rw.dafo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) up->cached_dafo &= ~SAB82532_DAFO_XBRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writeb(up->cached_dafo, &up->regs->rw.dafo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Disable Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) up->cached_mode &= ~SAB82532_MODE_RAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writeb(up->cached_mode, &up->regs->rw.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * XXX FIXME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * If the chip is powered down here the system hangs/crashes during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * reboot or shutdown. This needs to be investigated further,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * similar behaviour occurs in 2.4 when the driver is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * as a module only. One hint may be that data is sometimes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * transmitted at 9600 baud during shutdown (regardless of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * speed the chip was configured for when the port was open).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Power Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tmp = readb(&up->regs->rw.ccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tmp &= ~SAB82532_CCR0_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) writeb(tmp, &up->regs->rw.ccr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) free_irq(up->port.irq, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * This is used to figure out the divisor speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * with 0 <= N < 64 and 0 <= M < 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void calc_ebrg(int baud, int *n_ret, int *m_ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int n, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (baud == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *n_ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *m_ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * We scale numbers by 10 so that we get better accuracy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * without having to use floating point. Here we increment m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * until n is within the valid range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) n = (SAB_BASE_BAUD * 10) / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) while (n >= 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) n = n / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) m++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) n = (n+5) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * We try very hard to avoid speeds with M == 0 since they may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * not work correctly for XTAL frequences above 10 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if ((m == 0) && ((n & 1) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) n = n / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) m++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) *n_ret = n - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *m_ret = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Internal routine, port->lock is held and local interrupts are disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned int iflag, unsigned int baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned int quot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned char dafo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int bits, n, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) switch (cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Never happens, but GCC is too dumb to figure it out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (cflag & CSTOPB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dafo |= SAB82532_DAFO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dafo |= SAB82532_DAFO_PARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (cflag & PARODD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dafo |= SAB82532_DAFO_PAR_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dafo |= SAB82532_DAFO_PAR_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) up->cached_dafo = dafo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) calc_ebrg(baud, &n, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) up->cached_ebrg = n | (m << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) up->tec_timeout = (10 * 1000000) / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) up->cec_timeout = up->tec_timeout >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* CTS flow control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* We encode read_status_mask and ignore_status_mask like so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * | ... | ISR1 | ISR0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * .. 15 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SAB82532_ISR0_CDSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) up->port.read_status_mask |= (SAB82532_ISR1_CSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SAB82532_ISR1_ALLS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SAB82532_ISR1_XPR) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) up->port.read_status_mask |= (SAB82532_ISR0_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SAB82532_ISR0_FERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Characteres to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) up->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SAB82532_ISR0_FERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * ignore all characters if CREAD is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if ((cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SAB82532_ISR0_TCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) uart_update_timeout(&up->port, cflag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (up->port.uartclk / (16 * quot)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Now schedule a register update when the chip's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * transmitter is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) up->cached_mode |= SAB82532_MODE_RAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) set_bit(SAB82532_REGS_PENDING, &up->irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (test_bit(SAB82532_XPR, &up->irqflags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) sunsab_tx_idle(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* port->lock is not held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int quot = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char *sunsab_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct uart_sunsab_port *up = (void *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static char buf[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void sunsab_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int sunsab_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void sunsab_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const struct uart_ops sunsab_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .tx_empty = sunsab_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .set_mctrl = sunsab_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .get_mctrl = sunsab_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .stop_tx = sunsab_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .start_tx = sunsab_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .send_xchar = sunsab_send_xchar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .stop_rx = sunsab_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .break_ctl = sunsab_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .startup = sunsab_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .shutdown = sunsab_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .set_termios = sunsab_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .type = sunsab_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .release_port = sunsab_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .request_port = sunsab_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .config_port = sunsab_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .verify_port = sunsab_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct uart_driver sunsab_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .driver_name = "sunsab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .dev_name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static struct uart_sunsab_port *sunsab_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void sunsab_console_putchar(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct uart_sunsab_port *up =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) container_of(port, struct uart_sunsab_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) sunsab_tec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) writeb(c, &up->regs->w.tic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void sunsab_console_write(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct uart_sunsab_port *up = &sunsab_ports[con->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (up->port.sysrq || oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) locked = spin_trylock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) uart_console_write(&up->port, s, n, sunsab_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sunsab_tec_wait(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int sunsab_console_setup(struct console *con, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct uart_sunsab_port *up = &sunsab_ports[con->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned int baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * The console framework calls us for each and every port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * registered. Defer the console setup until the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * port has been properly discovered. A bit of a hack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * though...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (up->port.type != PORT_SUNSAB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) printk("Console: ttyS%d (SAB82532)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) (sunsab_reg.minor - 64) + con->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sunserial_console_termios(con, up->port.dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) switch (con->cflag & CBAUD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) case B150: baud = 150; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case B300: baud = 300; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case B600: baud = 600; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case B1200: baud = 1200; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case B2400: baud = 2400; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case B4800: baud = 4800; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) default: case B9600: baud = 9600; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case B19200: baud = 19200; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case B38400: baud = 38400; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case B57600: baud = 57600; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case B115200: baud = 115200; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case B230400: baud = 230400; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case B460800: baud = 460800; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Temporary fix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_lock_init(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Initialize the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) sunsab_startup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * Finally, enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writeb(up->interrupt_mask0, &up->regs->w.imr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SAB82532_IMR1_XPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) writeb(up->interrupt_mask1, &up->regs->w.imr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) quot = uart_get_divisor(&up->port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct console sunsab_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .write = sunsab_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .setup = sunsab_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .data = &sunsab_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static inline struct console *SUNSAB_CONSOLE(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return &sunsab_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define SUNSAB_CONSOLE() (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define sunsab_console_init() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int sunsab_init_one(struct uart_sunsab_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct platform_device *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) up->port.line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) up->port.dev = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) up->port.mapbase = op->resource[0].start + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) up->port.membase = of_ioremap(&op->resource[0], offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) sizeof(union sab82532_async_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "sab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!up->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) up->port.irq = op->archdata.irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) up->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) up->port.ops = &sunsab_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) up->port.type = PORT_SUNSAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) up->port.uartclk = SAB_BASE_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) up->type = readb(&up->regs->r.vstr) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) writeb(0xff, &up->regs->w.pim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if ((up->port.line & 0x1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) up->pvr_dsr_bit = (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) up->pvr_dtr_bit = (1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) up->gis_shift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) up->pvr_dsr_bit = (1 << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) up->pvr_dtr_bit = (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) up->gis_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writeb(up->cached_pvr, &up->regs->w.pvr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) up->cached_mode = readb(&up->regs->rw.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) up->cached_mode |= SAB82532_MODE_FRTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) writeb(up->cached_mode, &up->regs->rw.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) up->cached_mode |= SAB82532_MODE_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) writeb(up->cached_mode, &up->regs->rw.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int sab_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct uart_sunsab_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) up = &sunsab_ports[inst * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err = sunsab_init_one(&up[0], op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) (inst * 2) + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) err = sunsab_init_one(&up[1], op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) sizeof(union sab82532_async_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) (inst * 2) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &sunsab_reg, up[0].port.line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) &sunsab_reg, up[1].port.line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) err = uart_add_one_port(&sunsab_reg, &up[0].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) err = uart_add_one_port(&sunsab_reg, &up[1].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) goto out3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) platform_set_drvdata(op, &up[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) inst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) out3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) uart_remove_one_port(&sunsab_reg, &up[0].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) of_iounmap(&op->resource[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) up[1].port.membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) sizeof(union sab82532_async_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) of_iounmap(&op->resource[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) up[0].port.membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) sizeof(union sab82532_async_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int sab_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct uart_sunsab_port *up = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) uart_remove_one_port(&sunsab_reg, &up[1].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) uart_remove_one_port(&sunsab_reg, &up[0].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) of_iounmap(&op->resource[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) up[1].port.membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sizeof(union sab82532_async_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) of_iounmap(&op->resource[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) up[0].port.membase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) sizeof(union sab82532_async_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const struct of_device_id sab_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .name = "se",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .name = "serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .compatible = "sab82532",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) MODULE_DEVICE_TABLE(of, sab_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static struct platform_driver sab_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .name = "sab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .of_match_table = sab_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .probe = sab_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .remove = sab_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static int __init sunsab_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) int num_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) for_each_node_by_name(dp, "se")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) num_channels += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) for_each_node_by_name(dp, "serial") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (of_device_is_compatible(dp, "sab82532"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) num_channels += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (num_channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sunsab_ports = kcalloc(num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) sizeof(struct uart_sunsab_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!sunsab_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) err = sunserial_register_minors(&sunsab_reg, num_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) kfree(sunsab_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sunsab_ports = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return platform_driver_register(&sab_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static void __exit sunsab_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) platform_driver_unregister(&sab_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (sunsab_reg.nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) kfree(sunsab_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) sunsab_ports = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) module_init(sunsab_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) module_exit(sunsab_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags