Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) Maxime Coquelin 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) STMicroelectronics SA 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *	     Gerald Baeza <gerald_baeza@yahoo.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define DRIVER_NAME "stm32-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) struct stm32_usart_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	u8 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	u8 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	u8 cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	u8 brr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	u8 gtpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	u8 rtor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	u8 rqr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u8 icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u8 rdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8 tdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct stm32_usart_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u8 uart_enable_bit; /* USART_CR1_UE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	bool has_7bits_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	bool has_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	bool has_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct stm32_usart_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct stm32_usart_offsets ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct stm32_usart_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define UNDEF_REG 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct stm32_usart_info stm32f4_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.ofs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.isr	= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.rdr	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.tdr	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.brr	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.cr1	= 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.cr2	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.cr3	= 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.gtpr	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.rtor	= UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.rqr	= UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.icr	= UNDEF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.uart_enable_bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.has_7bits_data = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.fifosize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct stm32_usart_info stm32f7_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.ofs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.cr1	= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.cr2	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.cr3	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.brr	= 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.gtpr	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.rtor	= 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.rqr	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.isr	= 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.icr	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.rdr	= 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.tdr	= 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.uart_enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.has_7bits_data = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.fifosize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct stm32_usart_info stm32h7_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.ofs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.cr1	= 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.cr2	= 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.cr3	= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.brr	= 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.gtpr	= 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.rtor	= 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.rqr	= 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.isr	= 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.icr	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.rdr	= 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.tdr	= 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.uart_enable_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.has_7bits_data = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.has_wakeup = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.has_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* USART_SR (F4) / USART_ISR (F7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define USART_SR_PE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define USART_SR_FE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define USART_SR_NF		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define USART_SR_ORE		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define USART_SR_IDLE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USART_SR_RXNE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USART_SR_TC		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define USART_SR_TXE		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USART_SR_CTSIF		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USART_SR_CTS		BIT(10)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define USART_SR_RTOF		BIT(11)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USART_SR_EOBF		BIT(12)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USART_SR_ABRE		BIT(14)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USART_SR_ABRF		BIT(15)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USART_SR_BUSY		BIT(16)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USART_SR_CMF		BIT(17)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USART_SR_SBKF		BIT(18)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USART_SR_WUF		BIT(20)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USART_SR_TEACK		BIT(21)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define USART_SR_ERR_MASK	(USART_SR_ORE | USART_SR_FE | USART_SR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Dummy bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define USART_SR_DUMMY_RX	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* USART_DR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define USART_DR_MASK		GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* USART_BRR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define USART_BRR_DIV_F_MASK	GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USART_BRR_DIV_M_MASK	GENMASK(15, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define USART_BRR_DIV_M_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USART_BRR_04_R_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* USART_CR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define USART_CR1_SBK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define USART_CR1_RWU		BIT(1)		/* F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define USART_CR1_UESM		BIT(1)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define USART_CR1_RE		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define USART_CR1_TE		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define USART_CR1_IDLEIE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define USART_CR1_RXNEIE	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define USART_CR1_TCIE		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define USART_CR1_TXEIE		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define USART_CR1_PEIE		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define USART_CR1_PS		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define USART_CR1_PCE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define USART_CR1_WAKE		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USART_CR1_M0		BIT(12)		/* F7 (CR1_M for F4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USART_CR1_MME		BIT(13)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define USART_CR1_CMIE		BIT(14)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define USART_CR1_OVER8		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define USART_CR1_DEDT_MASK	GENMASK(20, 16)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define USART_CR1_DEAT_MASK	GENMASK(25, 21)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define USART_CR1_RTOIE		BIT(26)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USART_CR1_EOBIE		BIT(27)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USART_CR1_M1		BIT(28)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define USART_CR1_IE_MASK	(GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define USART_CR1_FIFOEN	BIT(29)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USART_CR1_DEAT_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define USART_CR1_DEDT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* USART_CR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define USART_CR2_ADD_MASK	GENMASK(3, 0)	/* F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define USART_CR2_ADDM7		BIT(4)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define USART_CR2_LBCL		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define USART_CR2_CPHA		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define USART_CR2_CPOL		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define USART_CR2_CLKEN		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define USART_CR2_STOP_2B	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define USART_CR2_STOP_MASK	GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define USART_CR2_LINEN		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USART_CR2_SWAP		BIT(15)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define USART_CR2_RXINV		BIT(16)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define USART_CR2_TXINV		BIT(17)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define USART_CR2_DATAINV	BIT(18)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define USART_CR2_MSBFIRST	BIT(19)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define USART_CR2_ABREN		BIT(20)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define USART_CR2_ABRMOD_MASK	GENMASK(22, 21)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define USART_CR2_RTOEN		BIT(23)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define USART_CR2_ADD_F7_MASK	GENMASK(31, 24)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* USART_CR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define USART_CR3_EIE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define USART_CR3_IREN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define USART_CR3_IRLP		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define USART_CR3_HDSEL		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define USART_CR3_NACK		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define USART_CR3_SCEN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define USART_CR3_DMAR		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define USART_CR3_DMAT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define USART_CR3_RTSE		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define USART_CR3_CTSE		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define USART_CR3_CTSIE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define USART_CR3_ONEBIT	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define USART_CR3_OVRDIS	BIT(12)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define USART_CR3_DDRE		BIT(13)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define USART_CR3_DEM		BIT(14)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define USART_CR3_DEP		BIT(15)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define USART_CR3_SCARCNT_MASK	GENMASK(19, 17)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define USART_CR3_WUS_MASK	GENMASK(21, 20)	/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define USART_CR3_WUS_START_BIT	BIT(21)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define USART_CR3_WUFIE		BIT(22)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define USART_CR3_TXFTIE	BIT(23)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define USART_CR3_TCBGTIE	BIT(24)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define USART_CR3_RXFTCFG_MASK	GENMASK(27, 25)	/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define USART_CR3_RXFTCFG_SHIFT	25		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define USART_CR3_RXFTIE	BIT(28)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define USART_CR3_TXFTCFG_MASK	GENMASK(31, 29)	/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define USART_CR3_TXFTCFG_SHIFT	29		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* TX FIFO threashold set to half of its depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define USART_CR3_TXFTCFG_HALF	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* RX FIFO threashold set to half of its depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define USART_CR3_RXFTCFG_HALF	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* USART_GTPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define USART_GTPR_PSC_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define USART_GTPR_GT_MASK	GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* USART_RTOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define USART_RTOR_RTO_MASK	GENMASK(23, 0)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define USART_RTOR_BLEN_MASK	GENMASK(31, 24)	/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* USART_RQR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define USART_RQR_ABRRQ		BIT(0)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define USART_RQR_SBKRQ		BIT(1)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define USART_RQR_MMRQ		BIT(2)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define USART_RQR_RXFRQ		BIT(3)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define USART_RQR_TXFRQ		BIT(4)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* USART_ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define USART_ICR_PECF		BIT(0)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define USART_ICR_FECF		BIT(1)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define USART_ICR_ORECF		BIT(3)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define USART_ICR_IDLECF	BIT(4)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define USART_ICR_TCCF		BIT(6)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define USART_ICR_CTSCF		BIT(9)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define USART_ICR_RTOCF		BIT(11)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define USART_ICR_EOBCF		BIT(12)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define USART_ICR_CMCF		BIT(17)		/* F7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define USART_ICR_WUCF		BIT(20)		/* H7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STM32_SERIAL_NAME "ttySTM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define STM32_MAX_PORTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_BUF_L 200		 /* dma rx buffer length     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RX_BUF_P RX_BUF_L	 /* dma rx buffer period     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TX_BUF_L 200		 /* dma tx buffer length     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct stm32_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	const struct stm32_usart_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct dma_chan *rx_ch;  /* dma rx channel            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned char *rx_buf;   /* dma rx buffer cpu address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	struct dma_chan *tx_ch;  /* dma tx channel            */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	unsigned char *tx_buf;   /* dma tx buffer cpu address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u32 cr1_irq;		 /* USART_CR1_RXNEIE or RTOIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u32 cr3_irq;		 /* USART_CR3_RXFTIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int last_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	bool tx_dma_busy;	 /* dma tx busy               */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	bool hw_flow_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	bool fifoen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	int rdr_mask;		/* receive data register mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct mctrl_gpios *gpios; /* modem control gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct stm32_port stm32_ports[STM32_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct uart_driver stm32_usart_driver;