^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * st-asc.c: ST Asynchronous serial controller (ASC) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003-2013 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_NAME "st-asc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ASC_SERIAL_NAME "ttyAS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASC_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASC_MAX_PORTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Pinctrl states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NO_HW_FLOWCTRL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct asc_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_desc *rts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct pinctrl_state *states[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int hw_flow_control:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int force_m1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct asc_port asc_ports[ASC_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct uart_driver asc_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*---- UART Register definitions ------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ASC_BAUDRATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ASC_TXBUF 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ASC_RXBUF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ASC_CTL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ASC_INTEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ASC_STA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ASC_GUARDTIME 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ASC_TIMEOUT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ASC_TXRESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ASC_RXRESET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ASC_RETRIES 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* ASC_RXBUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ASC_RXBUF_PE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ASC_RXBUF_FE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Some of status comes from higher bits of the character and some come from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * the status register. Combining both of them in to single status using dummy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASC_RXBUF_DUMMY_RX 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ASC_RXBUF_DUMMY_BE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ASC_RXBUF_DUMMY_OE 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* ASC_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ASC_CTL_MODE_MSK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ASC_CTL_MODE_8BIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ASC_CTL_MODE_7BIT_PAR 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ASC_CTL_MODE_9BIT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ASC_CTL_MODE_8BIT_WKUP 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ASC_CTL_MODE_8BIT_PAR 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ASC_CTL_STOP_MSK 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASC_CTL_STOP_HALFBIT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ASC_CTL_STOP_1BIT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASC_CTL_STOP_1_HALFBIT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ASC_CTL_STOP_2BIT 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ASC_CTL_PARITYODD 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ASC_CTL_LOOPBACK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ASC_CTL_RUN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ASC_CTL_RXENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ASC_CTL_SCENABLE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ASC_CTL_FIFOENABLE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ASC_CTL_CTSENABLE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ASC_CTL_BAUDMODE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* ASC_GUARDTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ASC_GUARDTIME_MSK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* ASC_INTEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ASC_INTEN_RBE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ASC_INTEN_TE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ASC_INTEN_THE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ASC_INTEN_PE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ASC_INTEN_FE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ASC_INTEN_OE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ASC_INTEN_TNE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ASC_INTEN_TOI 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ASC_INTEN_RHF 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* ASC_RETRIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ASC_RETRIES_MSK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* ASC_RXBUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ASC_RXBUF_MSK 0x03FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* ASC_STA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ASC_STA_RBF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ASC_STA_TE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ASC_STA_THE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ASC_STA_PE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ASC_STA_FE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ASC_STA_OE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ASC_STA_TNE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ASC_STA_TOI 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ASC_STA_RHF 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ASC_STA_TF 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ASC_STA_NKD 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* ASC_TIMEOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ASC_TIMEOUT_MSK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* ASC_TXBUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ASC_TXBUF_MSK 0x01FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*---- Inline function definitions ---------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline struct asc_port *to_asc_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return container_of(port, struct asc_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline u32 asc_in(struct uart_port *port, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #ifdef readl_relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return readl_relaxed(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return readl(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline void asc_out(struct uart_port *port, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef writel_relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel_relaxed(value, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(value, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Some simple utility functions to enable and disable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Note that these need to be called with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline void asc_disable_tx_interrupts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 intenable = asc_in(port, ASC_INTEN) & ~ASC_INTEN_THE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) asc_out(port, ASC_INTEN, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (void)asc_in(port, ASC_INTEN); /* Defeat bus write posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void asc_enable_tx_interrupts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 intenable = asc_in(port, ASC_INTEN) | ASC_INTEN_THE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) asc_out(port, ASC_INTEN, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void asc_disable_rx_interrupts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 intenable = asc_in(port, ASC_INTEN) & ~ASC_INTEN_RBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) asc_out(port, ASC_INTEN, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (void)asc_in(port, ASC_INTEN); /* Defeat bus write posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static inline void asc_enable_rx_interrupts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 intenable = asc_in(port, ASC_INTEN) | ASC_INTEN_RBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) asc_out(port, ASC_INTEN, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static inline u32 asc_txfifo_is_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return asc_in(port, ASC_STA) & ASC_STA_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline u32 asc_txfifo_is_half_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return asc_in(port, ASC_STA) & ASC_STA_THE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline const char *asc_port_name(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return to_platform_device(port->dev)->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * This section contains code to support the use of the ASC as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * generic serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline unsigned asc_hw_txroom(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 status = asc_in(port, ASC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (status & ASC_STA_THE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return port->fifosize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else if (!(status & ASC_STA_TF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Start transmitting chars.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * This is called from both interrupt and task level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Either way interrupts are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void asc_transmit_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int txroom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) txroom = asc_hw_txroom(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if ((txroom != 0) && port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) c = port->x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) asc_out(port, ASC_TXBUF, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) txroom = asc_hw_txroom(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * We should try and stop the hardware here, but I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * don't think the ASC has any way to do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) asc_disable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) asc_disable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (txroom == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) c = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) asc_out(port, ASC_TXBUF, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) txroom--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } while ((txroom > 0) && (!uart_circ_empty(xmit)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) asc_disable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void asc_receive_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long status, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned long c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bool ignore_pe = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Datasheet states: If the MODE field selects an 8-bit frame then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * this [parity error] bit is undefined. Software should ignore this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * bit when reading 8-bit frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mode = asc_in(port, ASC_CTL) & ASC_CTL_MODE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (mode == ASC_CTL_MODE_8BIT || mode == ASC_CTL_MODE_8BIT_PAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ignore_pe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pm_wakeup_event(tport->tty->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while ((status = asc_in(port, ASC_STA)) & ASC_STA_RBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) c = asc_in(port, ASC_RXBUF) | ASC_RXBUF_DUMMY_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (status & ASC_STA_OE || c & ASC_RXBUF_FE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (c & ASC_RXBUF_PE && !ignore_pe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (c & ASC_RXBUF_FE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (c == (ASC_RXBUF_FE | ASC_RXBUF_DUMMY_RX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) c |= ASC_RXBUF_DUMMY_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else if (c & ASC_RXBUF_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Reading any data from the RX FIFO clears the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * overflow error condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (status & ASC_STA_OE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) c |= ASC_RXBUF_DUMMY_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) c &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (c & ASC_RXBUF_DUMMY_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else if (c & ASC_RXBUF_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else if (c & ASC_RXBUF_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (uart_handle_sysrq_char(port, c & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uart_insert_char(port, c, ASC_RXBUF_DUMMY_OE, c & 0xff, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Tell the rest of the system the news. New characters! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static irqreturn_t asc_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status = asc_in(port, ASC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (status & ASC_STA_RBF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Receive FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) asc_receive_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if ((status & ASC_STA_THE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (asc_in(port, ASC_INTEN) & ASC_INTEN_THE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Transmitter FIFO at least half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) asc_transmit_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * UART Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static unsigned int asc_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return asc_txfifo_is_empty(port) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void asc_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct asc_port *ascport = to_asc_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * This routine is used for seting signals of: DTR, DCD, CTS and RTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * We use ASC's hardware for CTS/RTS when hardware flow-control is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * enabled, however if the RTS line is required for another purpose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * commonly controlled using HUP from userspace, then we need to toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * it manually, using GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Some boards also have DTR and DCD implemented using PIO pins, code to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * do this should be hooked in here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!ascport->rts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* If HW flow-control is enabled, we can't fiddle with the RTS line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (asc_in(port, ASC_CTL) & ASC_CTL_CTSENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gpiod_set_value(ascport->rts, mctrl & TIOCM_RTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static unsigned int asc_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * This routine is used for geting signals of: DTR, DCD, DSR, RI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * and CTS/RTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* There are probably characters waiting to be transmitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void asc_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) asc_enable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Transmit stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static void asc_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) asc_disable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Receive stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void asc_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) asc_disable_rx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Handle breaks - ignored by us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void asc_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Nothing here yet .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Enable port for reception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int asc_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (request_irq(port->irq, asc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) asc_port_name(port), port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(port->dev, "cannot allocate irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) asc_transmit_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) asc_enable_rx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void asc_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) asc_disable_tx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) asc_disable_rx_interrupts(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) free_irq(port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void asc_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct asc_port *ascport = to_asc_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case UART_PM_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) clk_prepare_enable(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case UART_PM_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Disable the ASC baud rate generator, which is as close as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * we can come to turning it off. Note this is not called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * the port spinlock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ctl = asc_in(port, ASC_CTL) & ~ASC_CTL_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) asc_out(port, ASC_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) clk_disable_unprepare(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void asc_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct asc_port *ascport = to_asc_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tcflag_t cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Update termios to reflect hardware capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) termios->c_cflag &= ~(CMSPAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) (ascport->hw_flow_control ? 0 : CRTSCTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) port->uartclk = clk_get_rate(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) cflag = termios->c_cflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* read control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ctrl_val = asc_in(port, ASC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* stop serial port and reset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) asc_out(port, ASC_CTL, (ctrl_val & ~ASC_CTL_RUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ctrl_val = ASC_CTL_RXENABLE | ASC_CTL_FIFOENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* reset fifo rx & tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) asc_out(port, ASC_TXRESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) asc_out(port, ASC_RXRESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* set character length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if ((cflag & CSIZE) == CS7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ctrl_val |= ASC_CTL_MODE_7BIT_PAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ctrl_val |= (cflag & PARENB) ? ASC_CTL_MODE_8BIT_PAR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ASC_CTL_MODE_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* set stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ctrl_val |= (cflag & CSTOPB) ? ASC_CTL_STOP_2BIT : ASC_CTL_STOP_1BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* odd parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ctrl_val |= ASC_CTL_PARITYODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if ((cflag & CRTSCTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ctrl_val |= ASC_CTL_CTSENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* If flow-control selected, stop handling RTS manually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ascport->rts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) devm_gpiod_put(port->dev, ascport->rts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ascport->rts = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pinctrl_select_state(ascport->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ascport->states[DEFAULT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* If flow-control disabled, it's safe to handle RTS manually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!ascport->rts && ascport->states[NO_HW_FLOWCTRL]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pinctrl_select_state(ascport->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ascport->states[NO_HW_FLOWCTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) gpiod = devm_gpiod_get(port->dev, "rts", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!IS_ERR(gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) gpiod_set_consumer_name(gpiod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) port->dev->of_node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ascport->rts = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if ((baud < 19200) && !ascport->force_m1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) asc_out(port, ASC_BAUDRATE, (port->uartclk / (16 * baud)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * MODE 1: recommended for high bit rates (above 19.2K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * baudrate * 16 * 2^16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * ASCBaudRate = ------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * inputclock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * To keep maths inside 64bits, we divide inputclock by 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u64 dividend = (u64)baud * (1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) do_div(dividend, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) asc_out(port, ASC_BAUDRATE, dividend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ctrl_val |= ASC_CTL_BAUDMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) uart_update_timeout(port, cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ascport->port.read_status_mask = ASC_RXBUF_DUMMY_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ascport->port.read_status_mask |= ASC_RXBUF_FE | ASC_RXBUF_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ascport->port.read_status_mask |= ASC_RXBUF_DUMMY_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ascport->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ascport->port.ignore_status_mask |= ASC_RXBUF_FE | ASC_RXBUF_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ascport->port.ignore_status_mask |= ASC_RXBUF_DUMMY_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ascport->port.ignore_status_mask |= ASC_RXBUF_DUMMY_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Ignore all characters if CREAD is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!(termios->c_cflag & CREAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ascport->port.ignore_status_mask |= ASC_RXBUF_DUMMY_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Set the timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) asc_out(port, ASC_TIMEOUT, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* write final value and enable port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) asc_out(port, ASC_CTL, (ctrl_val | ASC_CTL_RUN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char *asc_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return (port->type == PORT_ASC) ? DRIVER_NAME : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static void asc_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int asc_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * Called when the port is opened, and UPF_BOOT_AUTOCONF flag is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * Set type field if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void asc_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if ((flags & UART_CONFIG_TYPE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) port->type = PORT_ASC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) asc_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* No user changeable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Console polling routines for writing and reading from the uart while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * in an interrupt or debug context (i.e. kgdb).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int asc_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!(asc_in(port, ASC_STA) & ASC_STA_RBF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return asc_in(port, ASC_RXBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void asc_put_poll_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) while (!asc_txfifo_is_half_empty(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) asc_out(port, ASC_TXBUF, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #endif /* CONFIG_CONSOLE_POLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*---------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct uart_ops asc_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .tx_empty = asc_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .set_mctrl = asc_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .get_mctrl = asc_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .start_tx = asc_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .stop_tx = asc_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .stop_rx = asc_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .break_ctl = asc_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .startup = asc_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .shutdown = asc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .set_termios = asc_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .type = asc_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .release_port = asc_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .request_port = asc_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .config_port = asc_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .verify_port = asc_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .pm = asc_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .poll_get_char = asc_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .poll_put_char = asc_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif /* CONFIG_CONSOLE_POLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int asc_init_port(struct asc_port *ascport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct uart_port *port = &ascport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) port->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) port->ops = &asc_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) port->fifosize = ASC_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) port->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) port->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ST_ASC_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) port->membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (IS_ERR(port->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return PTR_ERR(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) port->mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) spin_lock_init(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ascport->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (WARN_ON(IS_ERR(ascport->clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* ensure that clk rate is correct by enabling the clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) clk_prepare_enable(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ascport->port.uartclk = clk_get_rate(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) WARN_ON(ascport->port.uartclk == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) clk_disable_unprepare(ascport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ascport->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (IS_ERR(ascport->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = PTR_ERR(ascport->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(&pdev->dev, "Failed to get Pinctrl: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ascport->states[DEFAULT] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pinctrl_lookup_state(ascport->pinctrl, "default");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (IS_ERR(ascport->states[DEFAULT])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = PTR_ERR(ascport->states[DEFAULT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "Failed to look up Pinctrl state 'default': %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* "no-hw-flowctrl" state is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ascport->states[NO_HW_FLOWCTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pinctrl_lookup_state(ascport->pinctrl, "no-hw-flowctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (IS_ERR(ascport->states[NO_HW_FLOWCTRL]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ascport->states[NO_HW_FLOWCTRL] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct asc_port *asc_of_get_asc_port(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) id = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) id = of_alias_get_id(np, ASC_SERIAL_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (WARN_ON(id >= ASC_MAX_PORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) asc_ports[id].hw_flow_control = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "uart-has-rtscts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) asc_ports[id].force_m1 = of_property_read_bool(np, "st,force_m1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) asc_ports[id].port.line = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) asc_ports[id].rts = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return &asc_ports[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct of_device_id asc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { .compatible = "st,asc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MODULE_DEVICE_TABLE(of, asc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static int asc_serial_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct asc_port *ascport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ascport = asc_of_get_asc_port(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!ascport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = asc_init_port(ascport, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = uart_add_one_port(&asc_uart_driver, &ascport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) platform_set_drvdata(pdev, &ascport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int asc_serial_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct uart_port *port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return uart_remove_one_port(&asc_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int asc_serial_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return uart_suspend_port(&asc_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int asc_serial_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return uart_resume_port(&asc_uart_driver, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #ifdef CONFIG_SERIAL_ST_ASC_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static void asc_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned int timeout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* Wait for upto 1 second in case flow control is stopping us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) while (--timeout && !asc_txfifo_is_half_empty(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) asc_out(port, ASC_TXBUF, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * Print a string to the serial port trying not to disturb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * any possible real use of the port...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void asc_console_write(struct console *co, const char *s, unsigned count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct uart_port *port = &asc_ports[co->index].port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned long timeout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 intenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (port->sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) locked = 0; /* asc_interrupt has already claimed the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) locked = spin_trylock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * Disable interrupts so we don't get the IRQ line bouncing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * up and down while interrupts are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) intenable = asc_in(port, ASC_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) asc_out(port, ASC_INTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (void)asc_in(port, ASC_INTEN); /* Defeat bus write posting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) uart_console_write(port, s, count, asc_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) while (--timeout && !asc_txfifo_is_empty(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) asc_out(port, ASC_INTEN, intenable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int asc_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct asc_port *ascport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (co->index >= ASC_MAX_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ascport = &asc_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * This driver does not support early console initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * (use ARM early printk support instead), so we only expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * this to be called during the uart port registration when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * driver gets probed and the port should be mapped at that point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ascport->port.mapbase == 0 || ascport->port.membase == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return uart_set_options(&ascport->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static struct console asc_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = ASC_SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .write = asc_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .setup = asc_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .data = &asc_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define ASC_SERIAL_CONSOLE (&asc_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ASC_SERIAL_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #endif /* CONFIG_SERIAL_ST_ASC_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static struct uart_driver asc_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .driver_name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .dev_name = ASC_SERIAL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .nr = ASC_MAX_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .cons = ASC_SERIAL_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const struct dev_pm_ops asc_serial_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SET_SYSTEM_SLEEP_PM_OPS(asc_serial_suspend, asc_serial_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static struct platform_driver asc_serial_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .probe = asc_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .remove = asc_serial_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .pm = &asc_serial_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .of_match_table = of_match_ptr(asc_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int __init asc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const char banner[] __initconst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) KERN_INFO "STMicroelectronics ASC driver initialized\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) printk(banner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = uart_register_driver(&asc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = platform_driver_register(&asc_serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uart_unregister_driver(&asc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void __exit asc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) platform_driver_unregister(&asc_serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) uart_unregister_driver(&asc_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) module_init(asc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) module_exit(asc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) MODULE_AUTHOR("STMicroelectronics (R&D) Limited");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MODULE_DESCRIPTION("STMicroelectronics ASC serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags