^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma/sprd-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UART_NR_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_TTY_NAME "ttyS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_FIFO_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_DEF_RATE 26000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_BAUD_IO_LIMIT 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_TIMEOUT 256000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* the offset of serial registers and BITs for them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPRD_TXD 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_RXD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* line status register and its BITs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_LSR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_LSR_OE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_LSR_FE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_LSR_PE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPRD_LSR_BI BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_LSR_TX_OVER BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* data number in TX and RX fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_STS1 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* interrupt enable register and its BITs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPRD_IEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPRD_IEN_RX_FULL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPRD_IEN_TX_EMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPRD_IEN_BREAK_DETECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRD_IEN_TIMEOUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* interrupt clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRD_ICLR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRD_ICLR_TIMEOUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* line control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPRD_LCR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPRD_LCR_STOP_1BIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPRD_LCR_STOP_2BIT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPRD_LCR_DATA_LEN5 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPRD_LCR_DATA_LEN6 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPRD_LCR_DATA_LEN7 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPRD_LCR_DATA_LEN8 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPRD_LCR_PARITY (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPRD_LCR_PARITY_EN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPRD_LCR_EVEN_PAR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPRD_LCR_ODD_PAR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPRD_CTL1 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPRD_DMA_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPRD_LOOPBACK_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RX_HW_FLOW_CTL_THLD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RX_HW_FLOW_CTL_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TX_HW_FLOW_CTL_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RX_TOUT_THLD_DEF 0x3E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RX_HFC_THLD_DEF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* fifo threshold register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SPRD_CTL2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define THLD_TX_EMPTY 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define THLD_TX_EMPTY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define THLD_RX_FULL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define THLD_RX_FULL_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* config baud rate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPRD_CLKD0 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPRD_CLKD0_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPRD_CLKD1 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPRD_CLKD1_MASK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SPRD_CLKD1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* interrupt mask status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPRD_IMSR 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPRD_IMSR_RX_FIFO_FULL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPRD_IMSR_BREAK_DETECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPRD_IMSR_TIMEOUT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPRD_DEFAULT_SOURCE_CLK 26000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPRD_RX_DMA_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPRD_RX_FIFO_FULL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPRD_TX_FIFO_FULL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct sprd_uart_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct dma_chan *chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned char *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sprd_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sprd_uart_dma tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sprd_uart_dma rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dma_addr_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned char *rx_buf_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct sprd_uart_port *sprd_port[UART_NR_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int sprd_ports_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int sprd_start_dma_rx(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int sprd_tx_dma_config(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline unsigned int serial_in(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return readl_relaxed(port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void serial_out(struct uart_port *port, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel_relaxed(value, port->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static unsigned int sprd_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static unsigned int sprd_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return TIOCM_DSR | TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 val = serial_in(port, SPRD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= SPRD_LOOPBACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val &= ~SPRD_LOOPBACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) serial_out(port, SPRD_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void sprd_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int ien, iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (sp->rx_dma.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dmaengine_terminate_all(sp->rx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) iclr = serial_in(port, SPRD_ICLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ien = serial_in(port, SPRD_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) serial_out(port, SPRD_IEN, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) serial_out(port, SPRD_ICLR, iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 val = serial_in(port, SPRD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val |= SPRD_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val &= ~SPRD_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) serial_out(port, SPRD_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void sprd_stop_tx_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dmaengine_pause(sp->tx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (state.residue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) trans_len = state.residue - sp->tx_dma.phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) port->icount.tx += trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sp->tx_dma.trans_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dmaengine_terminate_all(sp->tx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sp->tx_dma.trans_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int sprd_tx_buf_remap(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) sp->tx_dma.trans_len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sp->tx_dma.phys_addr = dma_map_single(port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (void *)&(xmit->buf[xmit->tail]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) sp->tx_dma.trans_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void sprd_complete_tx_dma(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct uart_port *port = (struct uart_port *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) sp->tx_dma.trans_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) port->icount.tx += sp->tx_dma.trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sprd_tx_dma_config(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sp->tx_dma.trans_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int sprd_uart_dma_submit(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct sprd_uart_dma *ud, u32 trans_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dma_async_tx_callback callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct dma_async_tx_descriptor *dma_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SPRD_DMA_NO_TRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SPRD_DMA_FRAG_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SPRD_DMA_TRANS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) direction, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!dma_des)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_des->callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dma_des->callback_param = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ud->cookie = dmaengine_submit(dma_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (dma_submit_error(ud->cookie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return dma_submit_error(ud->cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dma_async_issue_pending(ud->chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int sprd_tx_dma_config(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct dma_slave_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .dst_addr = port->mapbase + SPRD_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .src_maxburst = burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DMA_MEM_TO_DEV, sprd_complete_tx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void sprd_start_tx_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) serial_out(port, SPRD_TXD, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sprd_stop_tx_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (sp->tx_dma.trans_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) sp->tx_dma.trans_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 val = serial_in(port, SPRD_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val &= ~THLD_RX_FULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val |= thld & THLD_RX_FULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) serial_out(port, SPRD_CTL2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) &sp->rx_dma.phys_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!sp->rx_dma.virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void sprd_rx_free_buf(struct sprd_uart_port *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (sp->rx_dma.virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sp->rx_dma.virt, sp->rx_dma.phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct dma_slave_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .src_addr = port->mapbase + SPRD_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .src_maxburst = burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void sprd_uart_dma_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct tty_port *tty = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) port->icount.rx += sp->rx_dma.trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tty_flip_buffer_push(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void sprd_uart_dma_irq(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) status = dmaengine_tx_status(sp->rx_dma.chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sp->rx_dma.cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (status == DMA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sprd_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!state.residue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sp->rx_dma.phys_addr - sp->pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) sp->pos = sp->rx_dma.phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sp->rx_dma.trans_len = state.residue - sp->pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sp->pos = state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sprd_uart_dma_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sp->rx_buf_tail += sp->rx_dma.trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void sprd_complete_rx_dma(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct uart_port *port = (struct uart_port *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) status = dmaengine_tx_status(sp->rx_dma.chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sp->rx_dma.cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (status != DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) sprd_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (sp->pos != sp->rx_dma.phys_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sp->rx_dma.phys_addr - sp->pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sprd_uart_dma_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) sp->rx_buf_tail += sp->rx_dma.trans_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (sprd_start_dma_rx(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sprd_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int sprd_start_dma_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!sp->rx_dma.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sp->pos = sp->rx_dma.phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sp->rx_buf_tail = sp->rx_dma.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DMA_DEV_TO_MEM, sprd_complete_rx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void sprd_release_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sprd_uart_dma_enable(port, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (sp->rx_dma.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dma_release_channel(sp->rx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (sp->tx_dma.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dma_release_channel(sp->tx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sp->tx_dma.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sp->rx_dma.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static void sprd_request_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct sprd_uart_port *sp =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sp->tx_dma.enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) sp->rx_dma.enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (IS_ERR(sp->tx_dma.chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PTR_ERR(sp->tx_dma.chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) sp->tx_dma.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(sp->rx_dma.chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PTR_ERR(sp->rx_dma.chn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sp->rx_dma.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void sprd_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int ien, iclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (sp->tx_dma.enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) sprd_stop_tx_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) iclr = serial_in(port, SPRD_ICLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ien = serial_in(port, SPRD_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) iclr |= SPRD_IEN_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ien &= ~SPRD_IEN_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) serial_out(port, SPRD_IEN, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) serial_out(port, SPRD_ICLR, iclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void sprd_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (sp->tx_dma.enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) sprd_start_tx_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ien = serial_in(port, SPRD_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!(ien & SPRD_IEN_TX_EMPTY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ien |= SPRD_IEN_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) serial_out(port, SPRD_IEN, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* The Sprd serial does not support this function. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void sprd_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int handle_lsr_errors(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int *flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int *lsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (*lsr & SPRD_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = uart_handle_break(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else if (*lsr & SPRD_LSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else if (*lsr & SPRD_LSR_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (*lsr & SPRD_LSR_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* mask off conditions which should be ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *lsr &= port->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (*lsr & SPRD_LSR_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) *flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else if (*lsr & SPRD_LSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else if (*lsr & SPRD_LSR_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static inline void sprd_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct tty_port *tty = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (sp->rx_dma.enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sprd_uart_dma_irq(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) max_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) lsr = serial_in(port, SPRD_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ch = serial_in(port, SPRD_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SPRD_LSR_FE | SPRD_LSR_OE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (handle_lsr_errors(port, &flag, &lsr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (uart_handle_sysrq_char(port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tty_flip_buffer_push(tty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static inline void sprd_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) serial_out(port, SPRD_TXD, port->x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sprd_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) count = THLD_TX_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) sprd_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* this handles the interrupt from one port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned int ims;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ims = serial_in(port, SPRD_IMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!ims) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ims & SPRD_IMSR_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ims & SPRD_IMSR_BREAK_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SPRD_IMSR_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sprd_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) sprd_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void sprd_uart_dma_startup(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct sprd_uart_port *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sprd_request_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!(sp->rx_dma.enable || sp->tx_dma.enable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = sprd_start_dma_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sp->rx_dma.enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dma_release_channel(sp->rx_dma.chn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_warn(port->dev, "fail to start RX dma mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) sprd_uart_dma_enable(port, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int sprd_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned int ien, fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct sprd_uart_port *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) serial_out(port, SPRD_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* clear rx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) timeout = SPRD_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) serial_in(port, SPRD_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* clear tx fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) timeout = SPRD_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) serial_out(port, SPRD_IEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) serial_out(port, SPRD_ICLR, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* allocate irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sp = container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) sprd_uart_dma_startup(port, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) IRQF_SHARED, sp->name, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) port->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fc = serial_in(port, SPRD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) serial_out(port, SPRD_CTL1, fc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ien = serial_in(port, SPRD_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!sp->rx_dma.enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ien |= SPRD_IEN_RX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) serial_out(port, SPRD_IEN, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void sprd_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sprd_release_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) serial_out(port, SPRD_IEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) serial_out(port, SPRD_ICLR, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) devm_free_irq(port->dev, port->irq, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static void sprd_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned int baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int lcr = 0, fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* ask the core to calculate the divisor for us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) quot = port->uartclk / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* set data length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) lcr |= SPRD_LCR_DATA_LEN5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) lcr |= SPRD_LCR_DATA_LEN6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) lcr |= SPRD_LCR_DATA_LEN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) lcr |= SPRD_LCR_DATA_LEN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* calculate stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) lcr |= SPRD_LCR_STOP_2BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) lcr |= SPRD_LCR_STOP_1BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* calculate parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) lcr &= ~SPRD_LCR_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) termios->c_cflag &= ~CMSPAR; /* no support mark/space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) lcr |= SPRD_LCR_PARITY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) lcr |= SPRD_LCR_ODD_PAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) lcr |= SPRD_LCR_EVEN_PAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* update the per-port timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) port->read_status_mask = SPRD_LSR_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) port->read_status_mask |= SPRD_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* characters to ignore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) port->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) port->ignore_status_mask |= SPRD_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) port->ignore_status_mask |= SPRD_LSR_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) fc = serial_in(port, SPRD_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) fc |= RX_HW_FLOW_CTL_THLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) fc |= RX_HW_FLOW_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) fc |= TX_HW_FLOW_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* clock divider bit0~bit15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* clock divider bit16~bit20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) serial_out(port, SPRD_CLKD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) serial_out(port, SPRD_LCR, lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) serial_out(port, SPRD_CTL1, fc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const char *sprd_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return "SPX";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void sprd_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int sprd_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void sprd_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) port->type = PORT_SPRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ser->type != PORT_SPRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (port->irq != ser->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (port->iotype != ser->io_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static void sprd_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct sprd_uart_port *sup =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) container_of(port, struct sprd_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case UART_PM_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) clk_prepare_enable(sup->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case UART_PM_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk_disable_unprepare(sup->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int sprd_poll_init(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (port->state->pm_state != UART_PM_STATE_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) sprd_pm(port, UART_PM_STATE_ON, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) port->state->pm_state = UART_PM_STATE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int sprd_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return serial_in(port, SPRD_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) serial_out(port, SPRD_TXD, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct uart_ops serial_sprd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .tx_empty = sprd_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .get_mctrl = sprd_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .set_mctrl = sprd_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .stop_tx = sprd_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .start_tx = sprd_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .stop_rx = sprd_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .break_ctl = sprd_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .startup = sprd_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .shutdown = sprd_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .set_termios = sprd_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .type = sprd_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .release_port = sprd_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .request_port = sprd_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .config_port = sprd_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .verify_port = sprd_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .pm = sprd_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .poll_init = sprd_poll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .poll_get_char = sprd_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .poll_put_char = sprd_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #ifdef CONFIG_SERIAL_SPRD_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static void wait_for_xmitr(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* wait up to 10ms for the character(s) to be sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) status = serial_in(port, SPRD_STS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } while (status & SPRD_TX_FIFO_CNT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static void sprd_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) serial_out(port, SPRD_TXD, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static void sprd_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct uart_port *port = &sprd_port[co->index]->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (port->sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) locked = spin_trylock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) uart_console_write(port, s, count, sprd_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* wait for transmitter to become empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) wait_for_xmitr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int sprd_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct sprd_uart_port *sprd_uart_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (co->index >= UART_NR_MAX || co->index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sprd_uart_port = sprd_port[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!sprd_uart_port || !sprd_uart_port->port.membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pr_info("serial port %d not yet initialized\n", co->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return uart_set_options(&sprd_uart_port->port, co, baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct uart_driver sprd_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static struct console sprd_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .name = SPRD_TTY_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .write = sprd_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .setup = sprd_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .data = &sprd_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int __init sprd_serial_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) register_console(&sprd_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) console_initcall(sprd_serial_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define SPRD_CONSOLE (&sprd_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Support for earlycon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static void sprd_putc(struct uart_port *port, int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned int timeout = SPRD_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) while (timeout-- &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) writeb(c, port->membase + SPRD_TXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static void sprd_early_write(struct console *con, const char *s, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct earlycon_device *dev = con->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) uart_console_write(&dev->port, s, n, sprd_putc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int __init sprd_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) device->con->write = sprd_early_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sprd_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #else /* !CONFIG_SERIAL_SPRD_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SPRD_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static struct uart_driver sprd_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .driver_name = "sprd_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .dev_name = SPRD_TTY_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .major = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .minor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .nr = UART_NR_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .cons = SPRD_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int sprd_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct sprd_uart_port *sup = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (sup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) uart_remove_one_port(&sprd_uart_driver, &sup->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) sprd_port[sup->port.line] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sprd_rx_free_buf(sup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) sprd_ports_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (!sprd_ports_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) uart_unregister_driver(&sprd_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static bool sprd_uart_is_console(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct console *cons = sprd_uart_driver.cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if ((cons && cons->index >= 0 && cons->index == uport->line) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int sprd_clk_init(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct clk *clk_uart, *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct sprd_uart_port *u = sprd_port[uport->line];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) clk_uart = devm_clk_get(uport->dev, "uart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (IS_ERR(clk_uart)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev_warn(uport->dev, "uart%d can't get uart clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) uport->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) clk_uart = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clk_parent = devm_clk_get(uport->dev, "source");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (IS_ERR(clk_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev_warn(uport->dev, "uart%d can't get source clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) uport->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) clk_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) uport->uartclk = clk_get_rate(clk_uart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u->clk = devm_clk_get(uport->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (IS_ERR(u->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (PTR_ERR(u->clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_warn(uport->dev, "uart%d can't get enable clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) uport->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* To keep console alive even if the error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!sprd_uart_is_console(uport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return PTR_ERR(u->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int sprd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct uart_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) index = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (index < 0 || index >= ARRAY_SIZE(sprd_port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (!sprd_port[index])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) up = &sprd_port[index]->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) up->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) up->line = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) up->type = PORT_SPRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) up->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) up->uartclk = SPRD_DEF_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) up->fifosize = SPRD_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) up->ops = &serial_sprd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) up->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = sprd_clk_init(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) up->membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (IS_ERR(up->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return PTR_ERR(up->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) up->mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) up->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * Allocate one dma buffer to prepare for receive transfer, in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * memory allocation failure at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = sprd_rx_alloc_buf(sprd_port[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (!sprd_ports_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = uart_register_driver(&sprd_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pr_err("Failed to register SPRD-UART driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) sprd_ports_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = uart_add_one_port(&sprd_uart_driver, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) sprd_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) platform_set_drvdata(pdev, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int sprd_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct sprd_uart_port *sup = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) uart_suspend_port(&sprd_uart_driver, &sup->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int sprd_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct sprd_uart_port *sup = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) uart_resume_port(&sprd_uart_driver, &sup->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const struct of_device_id serial_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {.compatible = "sprd,sc9836-uart",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) MODULE_DEVICE_TABLE(of, serial_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static struct platform_driver sprd_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .probe = sprd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .remove = sprd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .name = "sprd_serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .of_match_table = of_match_ptr(serial_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .pm = &sprd_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) module_platform_driver(sprd_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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