^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Drivers for CSR SiRFprimaII onboard UARTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct sirfsoc_uart_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) const char *uart_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) const char *port_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct sirfsoc_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* hardware uart specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 sirfsoc_line_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 sirfsoc_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* uart - usp common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 sirfsoc_tx_rx_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 sirfsoc_int_en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 sirfsoc_int_st_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 sirfsoc_int_en_clr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 sirfsoc_tx_dma_io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 sirfsoc_tx_dma_io_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 sirfsoc_tx_fifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 sirfsoc_tx_fifo_level_chk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 sirfsoc_tx_fifo_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 sirfsoc_tx_fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 sirfsoc_tx_fifo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 sirfsoc_rx_dma_io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sirfsoc_rx_dma_io_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 sirfsoc_rx_fifo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 sirfsoc_rx_fifo_level_chk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 sirfsoc_rx_fifo_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 sirfsoc_rx_fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 sirfsoc_rx_fifo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 sirfsoc_afc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 sirfsoc_swh_dma_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* hardware usp specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 sirfsoc_mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 sirfsoc_mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 sirfsoc_tx_frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 sirfsoc_rx_frame_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 sirfsoc_async_param_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) typedef u32 (*fifo_full_mask)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) typedef u32 (*fifo_empty_mask)(struct uart_port *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct sirfsoc_fifo_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) fifo_full_mask ff_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) fifo_empty_mask ff_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sirfsoc_int_en {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 sirfsoc_rx_done_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 sirfsoc_tx_done_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 sirfsoc_rx_oflow_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 sirfsoc_tx_allout_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 sirfsoc_rx_io_dma_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 sirfsoc_tx_io_dma_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 sirfsoc_rxfifo_full_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 sirfsoc_txfifo_empty_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 sirfsoc_rxfifo_thd_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 sirfsoc_txfifo_thd_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 sirfsoc_frm_err_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 sirfsoc_rxd_brk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 sirfsoc_rx_timeout_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 sirfsoc_parity_err_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 sirfsoc_cts_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 sirfsoc_rts_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct sirfsoc_int_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 sirfsoc_rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 sirfsoc_tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 sirfsoc_rx_oflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 sirfsoc_tx_allout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 sirfsoc_rx_io_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 sirfsoc_tx_io_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 sirfsoc_rxfifo_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 sirfsoc_txfifo_empty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 sirfsoc_rxfifo_thd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 sirfsoc_txfifo_thd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 sirfsoc_frm_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 sirfsoc_rxd_brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 sirfsoc_rx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 sirfsoc_parity_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 sirfsoc_cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 sirfsoc_rts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum sirfsoc_uart_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SIRF_REAL_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SIRF_USP_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct sirfsoc_uart_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct sirfsoc_register uart_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sirfsoc_int_en uart_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct sirfsoc_int_status uart_int_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sirfsoc_fifo_status fifo_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sirfsoc_uart_param uart_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum sirfsoc_uart_type uart_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u32 uart_usp_ff_full_mask(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 full_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) full_bit = ilog2(port->fifosize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (1 << full_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u32 uart_usp_ff_empty_mask(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 empty_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) empty_bit = ilog2(port->fifosize) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return (1 << empty_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct sirfsoc_uart_register sirfsoc_usp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .uart_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .sirfsoc_mode1 = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .sirfsoc_mode2 = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .sirfsoc_tx_frame_ctrl = 0x0008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .sirfsoc_rx_frame_ctrl = 0x000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .sirfsoc_tx_rx_en = 0x0010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .sirfsoc_int_en_reg = 0x0014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .sirfsoc_int_st_reg = 0x0018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .sirfsoc_async_param_reg = 0x0024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .sirfsoc_tx_dma_io_ctrl = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .sirfsoc_tx_dma_io_len = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .sirfsoc_tx_fifo_ctrl = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .sirfsoc_tx_fifo_level_chk = 0x010c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .sirfsoc_tx_fifo_op = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .sirfsoc_tx_fifo_status = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .sirfsoc_tx_fifo_data = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .sirfsoc_rx_dma_io_ctrl = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .sirfsoc_rx_dma_io_len = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .sirfsoc_rx_fifo_ctrl = 0x0128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .sirfsoc_rx_fifo_level_chk = 0x012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .sirfsoc_rx_fifo_op = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .sirfsoc_rx_fifo_status = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .sirfsoc_rx_fifo_data = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .sirfsoc_int_en_clr_reg = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .uart_int_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .sirfsoc_rx_done_en = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .sirfsoc_tx_done_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .sirfsoc_rx_oflow_en = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .sirfsoc_tx_allout_en = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .sirfsoc_rx_io_dma_en = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .sirfsoc_tx_io_dma_en = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .sirfsoc_rxfifo_full_en = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .sirfsoc_txfifo_empty_en = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .sirfsoc_rxfifo_thd_en = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .sirfsoc_txfifo_thd_en = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .sirfsoc_frm_err_en = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .sirfsoc_rx_timeout_en = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .sirfsoc_rxd_brk_en = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .uart_int_st = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .sirfsoc_rx_done = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .sirfsoc_tx_done = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .sirfsoc_rx_oflow = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .sirfsoc_tx_allout = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .sirfsoc_rx_io_dma = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .sirfsoc_tx_io_dma = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .sirfsoc_rxfifo_full = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .sirfsoc_txfifo_empty = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .sirfsoc_rxfifo_thd = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .sirfsoc_txfifo_thd = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .sirfsoc_frm_err = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .sirfsoc_rx_timeout = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .sirfsoc_rxd_brk = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .fifo_status = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .ff_full = uart_usp_ff_full_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .ff_empty = uart_usp_ff_empty_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .uart_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .uart_name = "ttySiRF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .port_name = "sirfsoc-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct sirfsoc_uart_register sirfsoc_uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .uart_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .sirfsoc_line_ctrl = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .sirfsoc_tx_rx_en = 0x004c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .sirfsoc_divisor = 0x0050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .sirfsoc_int_en_reg = 0x0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .sirfsoc_int_st_reg = 0x0058,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .sirfsoc_int_en_clr_reg = 0x0060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .sirfsoc_tx_dma_io_ctrl = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .sirfsoc_tx_dma_io_len = 0x0104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .sirfsoc_tx_fifo_ctrl = 0x0108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .sirfsoc_tx_fifo_level_chk = 0x010c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .sirfsoc_tx_fifo_op = 0x0110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .sirfsoc_tx_fifo_status = 0x0114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .sirfsoc_tx_fifo_data = 0x0118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .sirfsoc_rx_dma_io_ctrl = 0x0120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .sirfsoc_rx_dma_io_len = 0x0124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .sirfsoc_rx_fifo_ctrl = 0x0128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .sirfsoc_rx_fifo_level_chk = 0x012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .sirfsoc_rx_fifo_op = 0x0130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .sirfsoc_rx_fifo_status = 0x0134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .sirfsoc_rx_fifo_data = 0x0138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .sirfsoc_afc_ctrl = 0x0140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .sirfsoc_swh_dma_io = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .uart_int_en = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sirfsoc_rx_done_en = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .sirfsoc_tx_done_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .sirfsoc_rx_oflow_en = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .sirfsoc_tx_allout_en = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .sirfsoc_rx_io_dma_en = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .sirfsoc_tx_io_dma_en = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .sirfsoc_rxfifo_full_en = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .sirfsoc_txfifo_empty_en = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .sirfsoc_rxfifo_thd_en = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .sirfsoc_txfifo_thd_en = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .sirfsoc_frm_err_en = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .sirfsoc_rxd_brk_en = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .sirfsoc_rx_timeout_en = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .sirfsoc_parity_err_en = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .sirfsoc_cts_en = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .sirfsoc_rts_en = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .uart_int_st = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .sirfsoc_rx_done = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .sirfsoc_tx_done = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .sirfsoc_rx_oflow = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .sirfsoc_tx_allout = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .sirfsoc_rx_io_dma = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .sirfsoc_tx_io_dma = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .sirfsoc_rxfifo_full = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .sirfsoc_txfifo_empty = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .sirfsoc_rxfifo_thd = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .sirfsoc_txfifo_thd = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .sirfsoc_frm_err = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .sirfsoc_rxd_brk = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .sirfsoc_rx_timeout = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .sirfsoc_parity_err = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .sirfsoc_cts = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .sirfsoc_rts = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .fifo_status = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .ff_full = uart_usp_ff_full_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .ff_empty = uart_usp_ff_empty_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .uart_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .uart_name = "ttySiRF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .port_name = "sirfsoc_uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* uart io ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SIRFUART_DATA_BIT_LEN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SIRFUART_DATA_BIT_LEN_5 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SIRFUART_DATA_BIT_LEN_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SIRFUART_DATA_BIT_LEN_7 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SIRFUART_DATA_BIT_LEN_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SIRFUART_STOP_BIT_LEN_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SIRFUART_STOP_BIT_LEN_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SIRFUART_PARITY_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SIRFUART_EVEN_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SIRFUART_STICK_BIT_MASK (7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SIRFUART_STICK_BIT_NONE (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SIRFUART_STICK_BIT_EVEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SIRFUART_STICK_BIT_ODD (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SIRFUART_STICK_BIT_MARK (5 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SIRFUART_STICK_BIT_SPACE (7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SIRFUART_SET_BREAK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SIRFUART_LOOP_BACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SIRFUART_PARITY_MASK (7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SIRFUART_DUMMY_READ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SIRFUART_AFC_CTRL_RX_THD 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SIRFUART_AFC_RX_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SIRFUART_AFC_TX_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SIRFUART_AFC_CTS_CTRL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SIRFUART_AFC_RTS_CTRL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SIRFUART_AFC_CTS_STATUS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SIRFUART_AFC_RTS_STATUS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* UART FIFO Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SIRFUART_FIFO_STOP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SIRFUART_FIFO_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SIRFUART_FIFO_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SIRFUART_RX_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SIRFUART_TX_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SIRFUART_IO_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SIRFUART_DMA_MODE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SIRFUART_RX_DMA_FLUSH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SIRFUART_CLEAR_RX_ADDR_EN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Baud Rate Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SIRF_USP_MIN_SAMPLE_DIV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SIRF_MIN_SAMPLE_DIV 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SIRF_MAX_SAMPLE_DIV 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SIRF_IOCLK_DIV_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SIRF_SAMPLE_DIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SIRF_IOCLK_DIV_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SIRF_SAMPLE_DIV_MASK 0x3f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SIRF_BAUD_RATE_SUPPORT_NR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* USP SPEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SIRFSOC_USP_ENDIAN_CTRL_LSBF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SIRFSOC_USP_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SIRFSOC_USP_TX_DATA_LEN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SIRFSOC_USP_TX_SYNC_LEN_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SIRFSOC_USP_TX_FRAME_LEN_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SIRFSOC_USP_RX_DATA_LEN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SIRFSOC_USP_RX_FRAME_LEN_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SIRFSOC_USP_ASYNC_DIV2_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SIRFSOC_USP_ASYNC_DIV2_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SIRFSOC_USP_LOOP_BACK_CTRL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SIRFSOC_USP_FRADDR_CLR_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* USP-UART Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SIRFUART_RECV_TIMEOUT_VALUE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SIRFUART_USP_RECV_TIMEOUT(x) (x & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SIRFUART_UART_RECV_TIMEOUT(x) ((x & 0xFFFF) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SIRFUART_ERR_INT_STAT(unit_st, uart_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) (uint_st->sirfsoc_rx_oflow | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uint_st->sirfsoc_frm_err | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) uint_st->sirfsoc_rxd_brk | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ((uart_type != SIRF_REAL_UART) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0 : uint_st->sirfsoc_parity_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SIRFUART_RX_IO_INT_EN(uint_en, uart_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (uint_en->sirfsoc_rx_done_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) uint_en->sirfsoc_rxfifo_thd_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) uint_en->sirfsoc_rxfifo_full_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) uint_en->sirfsoc_frm_err_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint_en->sirfsoc_rx_oflow_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) uint_en->sirfsoc_rxd_brk_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ((uart_type != SIRF_REAL_UART) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0 : uint_en->sirfsoc_parity_err_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SIRFUART_RX_IO_INT_ST(uint_st) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (uint_st->sirfsoc_rxfifo_thd |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) uint_st->sirfsoc_rxfifo_full|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) uint_st->sirfsoc_rx_done |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uint_st->sirfsoc_rx_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SIRFUART_CTS_INT_ST(uint_st) (uint_st->sirfsoc_cts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SIRFUART_RX_DMA_INT_EN(uint_en, uart_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (uint_en->sirfsoc_frm_err_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint_en->sirfsoc_rx_oflow_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uint_en->sirfsoc_rxd_brk_en |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ((uart_type != SIRF_REAL_UART) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0 : uint_en->sirfsoc_parity_err_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Generic Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SIRFSOC_UART_NAME "ttySiRF"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SIRFSOC_UART_MAJOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SIRFSOC_UART_MINOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SIRFUART_PORT_NAME "sirfsoc-uart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SIRFUART_MAP_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SIRFSOC_UART_NR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SIRFSOC_PORT_TYPE 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Uart Common Use Macro*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SIRFSOC_RX_DMA_BUF_SIZE (1024 * 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define BYTES_TO_ALIGN(dma_addr) ((unsigned long)(dma_addr) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Uart Fifo Level Chk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SIRFUART_TX_FIFO_SC_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SIRFUART_TX_FIFO_LC_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SIRFUART_TX_FIFO_HC_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SIRFUART_TX_FIFO_CHK_SC(line, value) ((((line) == 1) ? (value & 0x3) :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (value & 0x1f)) << SIRFUART_TX_FIFO_SC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SIRFUART_TX_FIFO_CHK_LC(line, value) ((((line) == 1) ? (value & 0x3) :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (value & 0x1f)) << SIRFUART_TX_FIFO_LC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SIRFUART_TX_FIFO_CHK_HC(line, value) ((((line) == 1) ? (value & 0x3) :\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) (value & 0x1f)) << SIRFUART_TX_FIFO_HC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SIRFUART_RX_FIFO_CHK_SC SIRFUART_TX_FIFO_CHK_SC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SIRFUART_RX_FIFO_CHK_LC SIRFUART_TX_FIFO_CHK_LC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SIRFUART_RX_FIFO_CHK_HC SIRFUART_TX_FIFO_CHK_HC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SIRFUART_RX_FIFO_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Indicate how many buffers used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* For Fast Baud Rate Calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct sirfsoc_baudrate_to_regv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int baud_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) enum sirfsoc_tx_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) TX_DMA_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) TX_DMA_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) TX_DMA_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct sirfsoc_rx_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct circ_buf xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct sirfsoc_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool hw_flow_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bool ms_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool is_atlas7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sirfsoc_uart_register *uart_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct dma_chan *rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct dma_chan *tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dma_addr_t tx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct dma_async_tx_descriptor *tx_dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum sirfsoc_tx_state tx_dma_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int cts_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int rts_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct sirfsoc_rx_buffer rx_dma_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct hrtimer hrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bool is_hrt_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned long rx_period_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long rx_last_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long pio_fetch_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Register Access Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define portaddr(port, reg) ((port)->membase + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* UART Port Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SIRFUART_FIFOLEVEL_MASK(port) ((port->fifosize - 1) & 0xFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SIRFUART_FIFOFULL_MASK(port) (port->fifosize & 0xFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SIRFUART_FIFOEMPTY_MASK(port) ((port->fifosize & 0xFFF) << 1)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags