^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define SCI_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define SCI_MINOR_START 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * SCI register subset common for all port types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Not all registers will exist on all parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) SCSMR, /* Serial Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SCBRR, /* Bit Rate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) SCSCR, /* Serial Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) SCxSR, /* Serial Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) SCFCR, /* FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SCFDR, /* FIFO Data Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SCxTDR, /* Transmit (FIFO) Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SCxRDR, /* Receive (FIFO) Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SCLSR, /* Line Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SCTFDR, /* Transmit FIFO Data Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SCRFDR, /* Receive FIFO Data Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SCSPTR, /* Serial Port Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) HSSRR, /* Sampling Rate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SCPCR, /* Serial Port Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SCPDR, /* Serial Port Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SCDL, /* BRG Frequency Division Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SCCKS, /* BRG Clock Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) HSRTRGR, /* Rx FIFO Data Count Trigger Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) HSTTRGR, /* Tx FIFO Data Count Trigger Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SCIx_NR_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* SCSMR (Serial Mode Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCSMR_C_A BIT(7) /* Communication Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCSMR_ASYNC 0 /* - Asynchronous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCSMR_PE BIT(5) /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCSMR_ODD BIT(4) /* Odd Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCSMR_STOP BIT(3) /* Stop Bit Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCSMR_CKS 0x0003 /* Clock Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Serial Mode Register, SCIFA/SCIFB only bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Serial Control Register, SCIFA/SCIFB only bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Serial Control Register, HSCIF-only bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HSSCR_TOT_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* SCxSR (Serial Status Register) on SCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCI_RDRF BIT(6) /* Receive Data Register Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SCI_ORER BIT(5) /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCI_FER BIT(4) /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCI_PER BIT(3) /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SCI_TEND BIT(2) /* Transmit End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCI_RESERVED 0x03 /* All reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCIF_ER BIT(7) /* Receive Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCIF_TEND BIT(6) /* Transmission End */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCIF_BRK BIT(4) /* Break Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCIF_FER BIT(3) /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCIF_PER BIT(2) /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCIF_DR BIT(0) /* Receive Data Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* SCIF only (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCIF_PERC 0xf000 /* Number of Parity Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCIF_FERC 0x0f00 /* Number of Framing Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCIFA_ORER BIT(9) /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SCFCR (FIFO Control Register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SCFCR_RTRG0 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCFCR_TTRG0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCFCR_MCE BIT(3) /* Modem Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCFCR_LOOP BIT(0) /* Loopback Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* SCLSR (Line Status Register) on (H)SCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCLSR_TO BIT(2) /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCLSR_ORER BIT(0) /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* SCSPTR (Serial Port Register), optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* HSSRR HSCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HSCIF_SRHP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HSCIF_SRHP_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * BRG Clock Select Register (Some SCIF and HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * The Baud Rate Generator for external clock can provide a clock source for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * the sampling clock. It outputs either its frequency divided clock, or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * (undivided) (H)SCK external clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SCxSR_RDxF_CLEAR(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SCxSR_ERROR_CLEAR(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (to_sci_port(port)->params->error_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SCxSR_TDxE_CLEAR(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SCxSR_BREAK_CLEAR(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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