^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 - 2011 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * based off of the old drivers/char/sh-sci.c by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1999, 2000 Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2000 Sugioka Toshinobu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Modified to support multiple serial ports. Stuart Menefy (May 2000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Modified to support SecureEdge. David McCullough (2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Removed SH7300 support (Jul 2007).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/serial_sci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/sh_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/sh_bios.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/platform_early.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "sh-sci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Offsets into the sci_port->irqs array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SCIx_ERI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SCIx_RXI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SCIx_TXI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SCIx_BRI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SCIx_DRI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SCIx_TEI_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SCIx_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCIx_IRQ_IS_MUXED(port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ((port)->irqs[SCIx_ERI_IRQ] == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (port)->irqs[SCIx_RXI_IRQ]) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ((port)->irqs[SCIx_ERI_IRQ] && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((port)->irqs[SCIx_RXI_IRQ] < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum SCI_CLKS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SCI_FCK, /* Functional Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SCI_SCK, /* Optional External Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SCI_BRG_INT, /* Optional BRG Internal Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SCI_SCIF_CLK, /* Optional BRG External Clock Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SCI_NUM_CLKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Bit x set means sampling rate x + 1 is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCI_SR(x) BIT((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SCI_SR(19) | SCI_SR(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define min_sr(_port) ffs((_port)->sampling_rate_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define max_sr(_port) fls((_port)->sampling_rate_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Iterate over all supported sampling rates, from high to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define for_each_sr(_sr, _port) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct plat_sci_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 offset, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sci_port_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct plat_sci_reg regs[SCIx_NR_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int overrun_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int overrun_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int sampling_rate_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int error_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int error_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sci_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Platform configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct sci_port_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct plat_sci_port *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int sampling_rate_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) resource_size_t reg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct mctrl_gpios *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *clks[SCI_NUM_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long clk_rates[SCI_NUM_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int irqs[SCIx_NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) char *irqstr[SCIx_NR_IRQS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct dma_chan *chan_tx_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct dma_chan *chan_rx_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dma_cookie_t cookie_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dma_cookie_t cookie_rx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dma_cookie_t active_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dma_addr_t tx_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int tx_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct scatterlist sg_rx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void *rx_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) size_t buf_len_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct work_struct work_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct hrtimer rx_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int rx_timeout; /* microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int rx_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int rx_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct timer_list rx_fifo_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int rx_fifo_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 hscif_tot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool has_rtscts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool autorts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct sci_port sci_ports[SCI_NPORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static unsigned long sci_ports_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct uart_driver sci_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline struct sci_port *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) to_sci_port(struct uart_port *uart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return container_of(uart, struct sci_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Common SCI definitions, dependent on the port's regshift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [SCIx_SCI_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [SCSMR] = { 0x00, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [SCBRR] = { 0x01, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [SCSCR] = { 0x02, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [SCxTDR] = { 0x03, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [SCxSR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [SCxRDR] = { 0x05, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .fifosize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .overrun_reg = SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .overrun_mask = SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Common definitions for legacy IrDA ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [SCIx_IRDA_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [SCSMR] = { 0x00, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [SCBRR] = { 0x02, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [SCSCR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [SCxTDR] = { 0x06, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [SCxSR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [SCxRDR] = { 0x0a, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [SCFCR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [SCFDR] = { 0x0e, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .fifosize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .overrun_reg = SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .overrun_mask = SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Common SCIFA definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [SCIx_SCIFA_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [SCxTDR] = { 0x20, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [SCxSR] = { 0x14, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [SCxRDR] = { 0x24, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [SCPCR] = { 0x30, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [SCPDR] = { 0x34, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .fifosize = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .overrun_reg = SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .overrun_mask = SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .sampling_rate_mask = SCI_SR_SCIFAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Common SCIFB definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [SCIx_SCIFB_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [SCxTDR] = { 0x40, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [SCxSR] = { 0x14, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [SCxRDR] = { 0x60, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [SCTFDR] = { 0x38, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [SCRFDR] = { 0x3c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [SCPCR] = { 0x30, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [SCPDR] = { 0x34, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .fifosize = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .overrun_reg = SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .overrun_mask = SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .sampling_rate_mask = SCI_SR_SCIFAB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Common SH-2(A) SCIF definitions for ports with FIFO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * count registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [SCSPTR] = { 0x20, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [SCLSR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * The "SCIFA" that is in RZ/T and RZ/A2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * It looks like a normal SCIF with FIFO data, but with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * compressed address space. Also, the break out of interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * are different: ERI/BRI, RXI, TXI, TEI, DRI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [SCIx_RZ_SCIFA_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [SCBRR] = { 0x02, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [SCSCR] = { 0x04, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [SCxTDR] = { 0x06, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [SCxSR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [SCxRDR] = { 0x0A, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [SCFCR] = { 0x0C, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [SCFDR] = { 0x0E, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) [SCSPTR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [SCLSR] = { 0x12, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Common SH-3 SCIF definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [SCIx_SH3_SCIF_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [SCSMR] = { 0x00, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [SCBRR] = { 0x02, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [SCSCR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [SCxTDR] = { 0x06, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [SCxSR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [SCxRDR] = { 0x0a, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [SCFCR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [SCFDR] = { 0x0e, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Common SH-4(A) SCIF(B) definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [SCIx_SH4_SCIF_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [SCSPTR] = { 0x20, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [SCLSR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Common SCIF definitions for ports with a Baud Rate Generator for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * External Clock (BRG).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [SCIx_SH4_SCIF_BRG_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [SCSPTR] = { 0x20, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [SCLSR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [SCDL] = { 0x30, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [SCCKS] = { 0x34, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Common HSCIF definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) [SCIx_HSCIF_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [SCSPTR] = { 0x20, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [SCLSR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [HSSRR] = { 0x40, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [SCDL] = { 0x30, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [SCCKS] = { 0x34, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [HSRTRGR] = { 0x54, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [HSTTRGR] = { 0x58, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .fifosize = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .sampling_rate_mask = SCI_SR_RANGE(8, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) [SCLSR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * count registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [SCxTDR] = { 0x0c, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [SCxSR] = { 0x10, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [SCxRDR] = { 0x14, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [SCRFDR] = { 0x20, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [SCSPTR] = { 0x24, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [SCLSR] = { 0x28, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .fifosize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .overrun_reg = SCLSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .overrun_mask = SCLSR_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .sampling_rate_mask = SCI_SR(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .error_mask = SCIF_DEFAULT_ERROR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .error_clear = SCIF_ERROR_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [SCIx_SH7705_SCIF_REGTYPE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [SCSMR] = { 0x00, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [SCBRR] = { 0x04, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [SCSCR] = { 0x08, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [SCxTDR] = { 0x20, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [SCxSR] = { 0x14, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [SCxRDR] = { 0x24, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [SCFCR] = { 0x18, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [SCFDR] = { 0x1c, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .fifosize = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .overrun_reg = SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .overrun_mask = SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .sampling_rate_mask = SCI_SR(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * The "offset" here is rather misleading, in that it refers to an enum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * value relative to the port mapping rather than the fixed offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * itself, which needs to be manually retrieved from the platform's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * register map for the given port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static unsigned int sci_serial_in(struct uart_port *p, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct plat_sci_reg *reg = sci_getreg(p, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (reg->size == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ioread8(p->membase + (reg->offset << p->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) else if (reg->size == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ioread16(p->membase + (reg->offset << p->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) WARN(1, "Invalid register access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void sci_serial_out(struct uart_port *p, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct plat_sci_reg *reg = sci_getreg(p, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (reg->size == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) iowrite8(value, p->membase + (reg->offset << p->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) else if (reg->size == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) iowrite16(value, p->membase + (reg->offset << p->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) WARN(1, "Invalid register access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void sci_port_enable(struct sci_port *sci_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!sci_port->port.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pm_runtime_get_sync(sci_port->port.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (i = 0; i < SCI_NUM_CLKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) clk_prepare_enable(sci_port->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void sci_port_disable(struct sci_port *sci_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!sci_port->port.dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) for (i = SCI_NUM_CLKS; i-- > 0; )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_disable_unprepare(sci_port->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pm_runtime_put_sync(sci_port->port.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static inline unsigned long port_rx_irq_mask(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Not all ports (such as SCIFA) will support REIE. Rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * special-casing the port type, we check the port initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * IRQ enable mask to see whether the IRQ is desired at all. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * it's unset, it's logically inferred that there's no point in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * testing for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void sci_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned short ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u16 new, scr = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (s->chan_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) new = scr | SCSCR_TDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) new = scr & ~SCSCR_TDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (new != scr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) serial_port_out(port, SCSCR, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dma_submit_error(s->cookie_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) s->cookie_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) schedule_work(&s->work_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void sci_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned short ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ctrl &= ~SCSCR_TDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ctrl &= ~SCSCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) serial_port_out(port, SCSCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (to_sci_port(port)->chan_tx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) !dma_submit_error(to_sci_port(port)->cookie_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dmaengine_terminate_async(to_sci_port(port)->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) to_sci_port(port)->cookie_tx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void sci_start_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned short ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ctrl &= ~SCSCR_RDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) serial_port_out(port, SCSCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void sci_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned short ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ctrl &= ~SCSCR_RDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ctrl &= ~port_rx_irq_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) serial_port_out(port, SCSCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (port->type == PORT_SCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Just store the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) serial_port_out(port, SCxSR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Only clear the status bits we want to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) serial_port_out(port, SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) serial_port_in(port, SCxSR) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Store the mask, clear parity/framing errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int sci_poll_get_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (status & SCxSR_ERRORS(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!(status & SCxSR_RDxF(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return NO_POLL_CHAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) c = serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void sci_poll_put_char(struct uart_port *port, unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } while (!(status & SCxSR_TDxE(port)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) serial_port_out(port, SCxTDR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CONFIG_SERIAL_SH_SCI_EARLYCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void sci_init_pins(struct uart_port *port, unsigned int cflag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Use port-specific handler if provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (s->cfg->ops && s->cfg->ops->init_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) s->cfg->ops->init_pins(port, cflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u16 data = serial_port_in(port, SCPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u16 ctrl = serial_port_in(port, SCPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Enable RXD and TXD pin functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (to_sci_port(port)->has_rtscts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* RTS# is output, active low, unless autorts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!(port->mctrl & TIOCM_RTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ctrl |= SCPCR_RTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) data |= SCPDR_RTSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else if (!s->autorts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ctrl |= SCPCR_RTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) data &= ~SCPDR_RTSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Enable RTS# pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ctrl &= ~SCPCR_RTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Enable CTS# pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ctrl &= ~SCPCR_CTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) serial_port_out(port, SCPDR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) serial_port_out(port, SCPCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else if (sci_getreg(port, SCSPTR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u16 status = serial_port_in(port, SCSPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* RTS# is always output; and active low, unless autorts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) status |= SCSPTR_RTSIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (!(port->mctrl & TIOCM_RTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) status |= SCSPTR_RTSDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else if (!s->autorts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) status &= ~SCSPTR_RTSDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* CTS# and SCK are inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) serial_port_out(port, SCSPTR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int sci_txfill(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg = sci_getreg(port, SCTFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return serial_port_in(port, SCTFDR) & fifo_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) reg = sci_getreg(port, SCFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return serial_port_in(port, SCFDR) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return !(serial_port_in(port, SCxSR) & SCI_TDRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int sci_txroom(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return port->fifosize - sci_txfill(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int sci_rxfill(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) reg = sci_getreg(port, SCRFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return serial_port_in(port, SCRFDR) & fifo_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) reg = sci_getreg(port, SCFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return serial_port_in(port, SCFDR) & fifo_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* ********************************************************************** *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * the interrupt related routines *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * ********************************************************************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static void sci_transmit_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) unsigned int stopped = uart_tx_stopped(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) unsigned short ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!(status & SCxSR_TDxE(port))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ctrl &= ~SCSCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ctrl |= SCSCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) serial_port_out(port, SCSCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) count = sci_txroom(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) c = port->x_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) } else if (!uart_circ_empty(xmit) && !stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) c = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) serial_port_out(port, SCxTDR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) sci_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* On SH3, SCIF may read end-of-break as a space->mark char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static void sci_receive_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int i, count, copied = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned char flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!(status & SCxSR_RDxF(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Don't copy more bytes than there is room for in the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) count = tty_buffer_request_room(tport, sci_rxfill(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* If for any reason we can't copy more data, we're done! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (port->type == PORT_SCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) char c = serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (uart_handle_sysrq_char(port, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) tty_insert_flip_char(tport, c, TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (port->type == PORT_SCIF ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) port->type == PORT_HSCIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) c = serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) c = serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (uart_handle_sysrq_char(port, c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) count--; i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Store data and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (status & SCxSR_FER(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_notice(port->dev, "frame error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } else if (status & SCxSR_PER(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_notice(port->dev, "parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) tty_insert_flip_char(tport, c, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) serial_port_in(port, SCxSR); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) copied += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) port->icount.rx += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (copied) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Tell the rest of the system the news. New characters! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* TTY buffers full; read from RX reg to prevent lockup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) serial_port_in(port, SCxSR); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int sci_handle_errors(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int copied = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned short status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Handle overruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (status & s->params->overrun_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* overrun error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) copied++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev_notice(port->dev, "overrun error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (status & SCxSR_FER(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* frame error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (tty_insert_flip_char(tport, 0, TTY_FRAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) copied++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_notice(port->dev, "frame error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (status & SCxSR_PER(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (tty_insert_flip_char(tport, 0, TTY_PARITY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) copied++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev_notice(port->dev, "parity error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (copied)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int sci_handle_fifo_overrun(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) int copied = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) reg = sci_getreg(port, s->params->overrun_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (!reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) status = serial_port_in(port, s->params->overrun_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (status & s->params->overrun_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) status &= ~s->params->overrun_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) serial_port_out(port, s->params->overrun_reg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) tty_insert_flip_char(tport, 0, TTY_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_dbg(port->dev, "overrun error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) copied++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int sci_handle_breaks(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int copied = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned short status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (uart_handle_break(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (status & SCxSR_BRK(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) port->icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Notify of BREAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (tty_insert_flip_char(tport, 0, TTY_BREAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) copied++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_dbg(port->dev, "BREAK detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (copied)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) tty_flip_buffer_push(tport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) copied += sci_handle_fifo_overrun(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int scif_set_rtrg(struct uart_port *port, int rx_trig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (rx_trig >= port->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) rx_trig = port->fifosize - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (rx_trig < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) rx_trig = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* HSCIF can be set to an arbitrary level. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (sci_getreg(port, HSRTRGR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) serial_port_out(port, HSRTRGR, rx_trig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return rx_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) switch (port->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case PORT_SCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (rx_trig < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rx_trig = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) } else if (rx_trig < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) bits = SCFCR_RTRG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rx_trig = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) } else if (rx_trig < 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bits = SCFCR_RTRG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) rx_trig = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) bits = SCFCR_RTRG0 | SCFCR_RTRG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) rx_trig = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case PORT_SCIFA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case PORT_SCIFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (rx_trig < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) rx_trig = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) } else if (rx_trig < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) bits = SCFCR_RTRG0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) rx_trig = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) } else if (rx_trig < 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) bits = SCFCR_RTRG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) rx_trig = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bits = SCFCR_RTRG0 | SCFCR_RTRG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) rx_trig = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) WARN(1, "unknown FIFO configuration");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) serial_port_out(port, SCFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) (serial_port_in(port, SCFCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return rx_trig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int scif_rtrg_enabled(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (sci_getreg(port, HSRTRGR)->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return serial_port_in(port, HSRTRGR) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return (serial_port_in(port, SCFCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void rx_fifo_timer_fn(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct sci_port *s = from_timer(s, t, rx_fifo_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_dbg(port->dev, "Rx timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) scif_set_rtrg(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static ssize_t rx_fifo_trigger_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct sci_port *sci = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return sprintf(buf, "%d\n", sci->rx_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static ssize_t rx_fifo_trigger_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct sci_port *sci = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret = kstrtol(buf, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) sci->rx_trigger = scif_set_rtrg(port, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) scif_set_rtrg(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static DEVICE_ATTR_RW(rx_fifo_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static ssize_t rx_fifo_timeout_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct sci_port *sci = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (port->type == PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) v = sci->rx_fifo_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return sprintf(buf, "%d\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static ssize_t rx_fifo_timeout_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct uart_port *port = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct sci_port *sci = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = kstrtol(buf, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (port->type == PORT_HSCIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (r < 0 || r > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) sci->hscif_tot = r << HSSCR_TOT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) sci->rx_fifo_timeout = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) scif_set_rtrg(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (r > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static DEVICE_ATTR_RW(rx_fifo_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static void sci_dma_tx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct sci_port *s = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) xmit->tail += s->tx_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) xmit->tail &= UART_XMIT_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) port->icount.tx += s->tx_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) s->cookie_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) schedule_work(&s->work_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) s->cookie_tx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u16 ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Locking: called with port lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct tty_port *tport = &port->state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) copied = tty_insert_flip_string(tport, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (copied < count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) port->icount.buf_overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) port->icount.rx += copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return copied;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static int sci_dma_rx_find_active(struct sci_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (s->active_rx == s->cookie_rx[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static void sci_dma_rx_chan_invalidate(struct sci_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) s->chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) s->cookie_rx[i] = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) s->active_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static void sci_dma_rx_release(struct sci_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct dma_chan *chan = s->chan_rx_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) s->chan_rx_saved = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) sci_dma_rx_chan_invalidate(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dmaengine_terminate_sync(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sg_dma_address(&s->sg_rx[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) long sec = usec / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) long nsec = (usec % 1000000) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ktime_t t = ktime_set(sec, nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) hrtimer_start(hrt, t, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static void sci_dma_rx_reenable_irq(struct sci_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) u16 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /* Direct new serial port interrupts back to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) scr = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) scr &= ~SCSCR_RDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) enable_irq(s->irqs[SCIx_RXI_IRQ]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) serial_port_out(port, SCSCR, scr | SCSCR_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static void sci_dma_rx_complete(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct sci_port *s = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct dma_chan *chan = s->chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int active, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) s->active_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) active = sci_dma_rx_find_active(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (active >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) start_hrtimer_us(&s->rx_timer, s->rx_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) desc->callback = sci_dma_rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) desc->callback_param = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) s->cookie_rx[active] = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (dma_submit_error(s->cookie_rx[active]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) s->active_rx = s->cookie_rx[!active];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) __func__, s->cookie_rx[active], active, s->active_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Switch to PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dmaengine_terminate_async(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sci_dma_rx_chan_invalidate(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) sci_dma_rx_reenable_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static void sci_dma_tx_release(struct sci_port *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct dma_chan *chan = s->chan_tx_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) cancel_work_sync(&s->work_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) s->chan_tx_saved = s->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) s->cookie_tx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dmaengine_terminate_sync(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct dma_chan *chan = s->chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct scatterlist *sg = &s->sg_rx[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) desc = dmaengine_prep_slave_sg(chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) sg, 1, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) desc->callback = sci_dma_rx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) desc->callback_param = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) s->cookie_rx[i] = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (dma_submit_error(s->cookie_rx[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) s->active_rx = s->cookie_rx[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* Switch to PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (!port_lock_held)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dmaengine_terminate_async(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) sci_dma_rx_chan_invalidate(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) sci_start_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (!port_lock_held)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static void sci_dma_tx_work_fn(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct sci_port *s = container_of(work, struct sci_port, work_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct dma_chan *chan = s->chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dma_addr_t buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) int head, tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * DMA is idle now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * Port xmit buffer is already mapped, and it is one page... Just adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * offsets and lengths. Since it is a circular buffer, we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * transmit till the end, and then the rest. Take the port lock to get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * consistent xmit buffer state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) spin_lock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) head = xmit->head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) tail = xmit->tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) s->tx_dma_len = min_t(unsigned int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) CIRC_CNT(head, tail, UART_XMIT_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (!s->tx_dma_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* Transmit buffer has been flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) goto switch_to_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) desc->callback = sci_dma_tx_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) desc->callback_param = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) s->cookie_tx = dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (dma_submit_error(s->cookie_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) goto switch_to_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) spin_unlock_irq(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) __func__, xmit->buf, tail, head, s->cookie_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) switch_to_pio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) s->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sci_start_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct sci_port *s = container_of(t, struct sci_port, rx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct dma_chan *chan = s->chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct uart_port *port = &s->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) unsigned int read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) int active, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dev_dbg(port->dev, "DMA Rx timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) active = sci_dma_rx_find_active(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (active < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (status == DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) s->active_rx, active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* Let packet complete handler take care of the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dmaengine_pause(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * sometimes DMA transfer doesn't stop even if it is stopped and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * data keeps on coming until transaction is complete so check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * for DMA_COMPLETE again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * Let packet complete handler take care of the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (status == DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Handle incomplete DMA receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) dmaengine_terminate_async(s->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) read = sg_dma_len(&s->sg_rx[active]) - state.residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) count = sci_dma_rx_push(s, s->rx_buf[active], read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) sci_dma_rx_submit(s, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) sci_dma_rx_reenable_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return HRTIMER_NORESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) chan = dma_request_slave_channel(port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dir == DMA_MEM_TO_DEV ? "tx" : "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (!chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_dbg(port->dev, "dma_request_slave_channel failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) cfg.direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) cfg.dst_addr = port->mapbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) (sci_getreg(port, SCxTDR)->offset << port->regshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) cfg.src_addr = port->mapbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) (sci_getreg(port, SCxRDR)->offset << port->regshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static void sci_request_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * DMA on console may interfere with Kernel log messages which use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) * plain putchar(). So, simply don't use it with a console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (uart_console(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (!port->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) s->cookie_tx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * Don't request a dma channel if no channel was specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (!of_find_property(port->dev->of_node, "dmas", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* UART circular tx buffer is an aligned page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) s->tx_dma_addr = dma_map_single(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) port->state->xmit.buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) UART_XMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) __func__, UART_XMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) port->state->xmit.buf, &s->tx_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) s->chan_tx_saved = s->chan_tx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_warn(port->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) "Failed to allocate Rx dma buffer, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct scatterlist *sg = &s->sg_rx[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) sg_init_table(sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) s->rx_buf[i] = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) sg_dma_address(sg) = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) sg_dma_len(sg) = s->buf_len_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) buf += s->buf_len_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dma += s->buf_len_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) s->rx_timer.function = sci_dma_rx_timer_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) s->chan_rx_saved = s->chan_rx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) sci_dma_rx_submit(s, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static void sci_free_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (s->chan_tx_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sci_dma_tx_release(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (s->chan_rx_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) sci_dma_rx_release(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static void sci_flush_buffer(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * In uart_flush_buffer(), the xmit circular buffer has just been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * cleared, so we have to reset tx_dma_len accordingly, and stop any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) * pending transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) s->tx_dma_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (s->chan_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) dmaengine_terminate_async(s->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) s->cookie_tx = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #else /* !CONFIG_SERIAL_SH_SCI_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static inline void sci_request_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static inline void sci_free_dma(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define sci_flush_buffer NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (s->chan_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u16 scr = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u16 ssr = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* Disable future Rx interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) scr |= SCSCR_RDRQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (sci_dma_rx_submit(s, false) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) goto handle_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) scr &= ~SCSCR_RIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) serial_port_out(port, SCSCR, scr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Clear current interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) serial_port_out(port, SCxSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) jiffies, s->rx_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) start_hrtimer_us(&s->rx_timer, s->rx_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) handle_pio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!scif_rtrg_enabled(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) scif_set_rtrg(port, s->rx_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* I think sci_receive_chars has to be called irrespective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * of whether the I_IXOFF is set, otherwise, how is the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) * to be disabled?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) sci_receive_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) sci_transmit_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static irqreturn_t sci_br_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* Handle BREAKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) sci_handle_breaks(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* drop invalid character received before break was detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) serial_port_in(port, SCxRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static irqreturn_t sci_er_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* Break and Error interrupts are muxed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) unsigned short ssr_status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* Break Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (ssr_status & SCxSR_BRK(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) sci_br_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* Break only? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!(ssr_status & SCxSR_ERRORS(port)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* Handle errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (port->type == PORT_SCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (sci_handle_errors(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* discard character in rx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) sci_handle_fifo_overrun(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (!s->chan_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) sci_receive_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* Kick the transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!s->chan_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) sci_tx_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct uart_port *port = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ssr_status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) scr_status = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (s->params->overrun_reg == SCxSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) orer_status = ssr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) else if (sci_getreg(port, s->params->overrun_reg)->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) orer_status = serial_port_in(port, s->params->overrun_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) err_enabled = scr_status & port_rx_irq_mask(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* Tx Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) !s->chan_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = sci_tx_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) * DR flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) (scr_status & SCSCR_RIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ret = sci_rx_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret = sci_er_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* Break Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) (ssr_status & SCxSR_BRK(port)) && err_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ret = sci_br_interrupt(irq, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* Overrun Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (orer_status & s->params->overrun_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) sci_handle_fifo_overrun(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const struct sci_irq_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) irq_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } sci_irq_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * Split out handlers, the default case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) [SCIx_ERI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .desc = "rx err",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .handler = sci_er_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) [SCIx_RXI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .desc = "rx full",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .handler = sci_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) [SCIx_TXI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .desc = "tx empty",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .handler = sci_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) [SCIx_BRI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .desc = "break",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .handler = sci_br_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) [SCIx_DRI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .desc = "rx ready",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .handler = sci_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) [SCIx_TEI_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .desc = "tx end",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .handler = sci_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) * Special muxed handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) [SCIx_MUX_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .desc = "mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .handler = sci_mpxed_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static int sci_request_irq(struct sci_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) struct uart_port *up = &port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) int i, j, w, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) const struct sci_irq_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Check if already registered (muxed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) for (w = 0; w < i; w++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (port->irqs[w] == port->irqs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) w = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (w > i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (SCIx_IRQ_IS_MUXED(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) i = SCIx_MUX_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) irq = up->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) irq = port->irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * Certain port types won't support all of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * available interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (unlikely(irq < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) desc = sci_irq_desc + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) dev_name(up->dev), desc->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!port->irqstr[j]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) goto out_nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ret = request_irq(irq, desc->handler, up->irqflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) port->irqstr[j], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) goto out_noirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) out_noirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) free_irq(port->irqs[i], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) out_nomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) while (--j >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) kfree(port->irqstr[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static void sci_free_irq(struct sci_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * Intentionally in reverse order so we iterate over the muxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * IRQ first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) for (i = 0; i < SCIx_NR_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) int irq = port->irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * Certain port types won't support all of the available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (unlikely(irq < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* Check if already freed (irq was muxed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) if (port->irqs[j] == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) j = i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (j > i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) free_irq(port->irqs[i], port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) kfree(port->irqstr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (SCIx_IRQ_IS_MUXED(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* If there's only one IRQ, we're done. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static unsigned int sci_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) unsigned short status = serial_port_in(port, SCxSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) unsigned short in_tx_fifo = sci_txfill(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static void sci_set_rts(struct uart_port *port, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) u16 data = serial_port_in(port, SCPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) data &= ~SCPDR_RTSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) data |= SCPDR_RTSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) serial_port_out(port, SCPDR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* RTS# is output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) serial_port_out(port, SCPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) serial_port_in(port, SCPCR) | SCPCR_RTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) } else if (sci_getreg(port, SCSPTR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) u16 ctrl = serial_port_in(port, SCSPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ctrl &= ~SCSPTR_RTSDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ctrl |= SCSPTR_RTSDT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) serial_port_out(port, SCSPTR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static bool sci_get_cts(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) } else if (sci_getreg(port, SCSPTR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * CTS/RTS is supported in hardware by at least one port and controlled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * handled via the ->init_pins() op, which is a bit of a one-way street,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) * lacking any ability to defer pin control -- this will later be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) * converted over to the GPIO framework).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) * Other modes (such as loopback) are supported generically on certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) * port types, but not others. For these it's sufficient to test for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) * existence of the support register and simply ignore the port type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (mctrl & TIOCM_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * Standard loopback mode for SCFCR ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) reg = sci_getreg(port, SCFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) serial_port_out(port, SCFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) serial_port_in(port, SCFCR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) SCFCR_LOOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) mctrl_gpio_set(s->gpios, mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (!s->has_rtscts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (!(mctrl & TIOCM_RTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* Disable Auto RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) serial_port_out(port, SCFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) serial_port_in(port, SCFCR) & ~SCFCR_MCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* Clear RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) sci_set_rts(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) } else if (s->autorts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* Enable RTS# pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) serial_port_out(port, SCPCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) /* Enable Auto RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) serial_port_out(port, SCFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) serial_port_in(port, SCFCR) | SCFCR_MCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* Set RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) sci_set_rts(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) static unsigned int sci_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) struct mctrl_gpios *gpios = s->gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) unsigned int mctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) mctrl_gpio_get(gpios, &mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) * CTS/RTS is handled in hardware when supported, while nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * else is wired up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if (s->autorts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (sci_get_cts(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) mctrl |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) mctrl |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static void sci_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static void sci_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) unsigned short scscr, scsptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* check wheter the port has SCSPTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (!sci_getreg(port, SCSPTR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * Not supported by hardware. Most parts couple break and rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * interrupts together, with break detection always enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) scsptr = serial_port_in(port, SCSPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) scscr = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (break_state == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) scscr &= ~SCSCR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) scscr |= SCSCR_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) serial_port_out(port, SCSPTR, scsptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) serial_port_out(port, SCSCR, scscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static int sci_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) sci_request_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ret = sci_request_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) sci_free_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static void sci_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) u16 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) s->autorts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) sci_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) sci_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * Stop RX and TX, disable related interrupts, keep clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * and HSCIF TOT bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) scr = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) serial_port_out(port, SCSCR, scr &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (s->chan_rx_saved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) hrtimer_cancel(&s->rx_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) del_timer_sync(&s->rx_fifo_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) sci_free_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) sci_free_dma(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) static int sci_sck_calc(struct sci_port *s, unsigned int bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) unsigned int *srr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) unsigned long freq = s->clk_rates[SCI_SCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) int err, min_err = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (s->port.type != PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) freq *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) for_each_sr(sr, s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) err = DIV_ROUND_CLOSEST(freq, sr) - bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (abs(err) >= abs(min_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) *srr = sr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) *srr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) return min_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static int sci_brg_calc(struct sci_port *s, unsigned int bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) unsigned long freq, unsigned int *dlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) unsigned int *srr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) int err, min_err = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) unsigned int sr, dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) if (s->port.type != PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) freq *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) for_each_sr(sr, s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dl = DIV_ROUND_CLOSEST(freq, sr * bps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) dl = clamp(dl, 1U, 65535U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (abs(err) >= abs(min_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) *dlr = dl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) *srr = sr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) min_err, *dlr, *srr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) return min_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* calculate sample rate, BRR, and clock select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) unsigned int *brr, unsigned int *srr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) unsigned int *cks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) unsigned long freq = s->clk_rates[SCI_FCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) unsigned int sr, br, prediv, scrate, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) int err, min_err = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (s->port.type != PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) freq *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) * Find the combination of sample rate and clock select with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) * smallest deviation from the desired baud rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) * Prefer high sample rates to maximise the receive margin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * M: Receive margin (%)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) * N: Ratio of bit rate to clock (N = sampling rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) * D: Clock duty (D = 0 to 1.0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) * L: Frame length (L = 9 to 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) * F: Absolute value of clock frequency deviation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) * (|D - 0.5| / N * (1 + F))|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) for_each_sr(sr, s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) for (c = 0; c <= 3; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) /* integerized formulas from HSCIF documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) prediv = sr * (1 << (2 * c + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) * We need to calculate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) * br = freq / (prediv * bps) clamped to [1..256]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) * err = freq / (br * prediv) - bps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) * Watch out for overflow when calculating the desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) * sampling clock rate!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (bps > UINT_MAX / prediv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) scrate = prediv * bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) br = DIV_ROUND_CLOSEST(freq, scrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) br = clamp(br, 1U, 256U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) if (abs(err) >= abs(min_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) *brr = br - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) *srr = sr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) *cks = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) min_err, *brr, *srr + 1, *cks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) return min_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static void sci_reset(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) reg = sci_getreg(port, SCFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (reg->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) sci_clear_SCxSR(port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) SCxSR_BREAK_CLEAR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (sci_getreg(port, SCLSR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) status = serial_port_in(port, SCLSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) status &= ~(SCLSR_TO | SCLSR_ORER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) serial_port_out(port, SCLSR, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (s->rx_trigger > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (s->rx_fifo_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) scif_set_rtrg(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) if (port->type == PORT_SCIFA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) scif_set_rtrg(port, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) scif_set_rtrg(port, s->rx_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) struct sci_port *s = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) const struct plat_sci_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) int min_err = INT_MAX, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) unsigned long max_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) int best_clk = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if ((termios->c_cflag & CSIZE) == CS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) smr_val |= SCSMR_CHR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) smr_val |= SCSMR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) smr_val |= SCSMR_PE | SCSMR_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) smr_val |= SCSMR_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) * earlyprintk comes here early on with port->uartclk set to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) * the clock framework is not up and running at this point so here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) * we assume that 115200 is the maximum baud rate. please note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) * the baud rate is not programmed during earlyprintk - it is assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) * that the previous boot loader has enabled required clocks and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) * setup the baud rate generator hardware for us already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (!port->uartclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) baud = uart_get_baud_rate(port, termios, old, 0, 115200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) for (i = 0; i < SCI_NUM_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) max_freq = max(max_freq, s->clk_rates[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (!baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * There can be multiple sources for the sampling clock. Find the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) * that gives us the smallest deviation from the desired baud rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) /* Optional Undivided External Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) port->type != PORT_SCIFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) err = sci_sck_calc(s, baud, &srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (abs(err) < abs(min_err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) best_clk = SCI_SCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) scr_val = SCSCR_CKE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) sccks = SCCKS_CKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) srr = srr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* Optional BRG Frequency Divided External Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) &srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) if (abs(err) < abs(min_err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) best_clk = SCI_SCIF_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) scr_val = SCSCR_CKE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) sccks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) dl = dl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) srr = srr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) /* Optional BRG Frequency Divided Internal Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) &srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (abs(err) < abs(min_err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) best_clk = SCI_BRG_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) scr_val = SCSCR_CKE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) sccks = SCCKS_XIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) dl = dl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) srr = srr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (!min_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) /* Divided Functional Clock using standard Bit Rate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (abs(err) < abs(min_err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) best_clk = SCI_FCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) scr_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) brr = brr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) srr = srr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) cks = cks1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (best_clk >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) s->clks[best_clk], baud, min_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) sci_port_enable(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) * Program the optional External Baud Rate Generator (BRG) first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) * It controls the mux to select (H)SCK or frequency divided clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) serial_port_out(port, SCDL, dl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) serial_port_out(port, SCCKS, sccks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) sci_reset(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /* byte size and parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) bits = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (best_clk >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) switch (srr + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) case 5: smr_val |= SCSMR_SRC_5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) case 7: smr_val |= SCSMR_SRC_7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) case 11: smr_val |= SCSMR_SRC_11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) case 13: smr_val |= SCSMR_SRC_13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) case 16: smr_val |= SCSMR_SRC_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) case 17: smr_val |= SCSMR_SRC_17; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) case 19: smr_val |= SCSMR_SRC_19; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) case 27: smr_val |= SCSMR_SRC_27; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) smr_val |= cks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) serial_port_out(port, SCSMR, smr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) serial_port_out(port, SCBRR, brr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (sci_getreg(port, HSSRR)->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) unsigned int hssrr = srr | HSCIF_SRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* Calculate deviation from intended rate at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) * center of the last stop bit in sampling clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) int last_stop = bits * 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) (int)(srr + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) 2 * (int)baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (abs(deviation) >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /* At least two sampling clocks off at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) * last stop bit; we can increase the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) * margin by shifting the sampling point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) int shift = clamp(deviation / 2, -8, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) hssrr |= (shift << HSCIF_SRHP_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) HSCIF_SRHP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) hssrr |= HSCIF_SRDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) serial_port_out(port, HSSRR, hssrr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) /* Wait one bit interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) udelay((1000000 + (baud - 1)) / baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* Don't touch the bit rate configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) smr_val |= serial_port_in(port, SCSMR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) serial_port_out(port, SCSMR, smr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) sci_init_pins(port, termios->c_cflag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) port->status &= ~UPSTAT_AUTOCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) s->autorts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) reg = sci_getreg(port, SCFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (reg->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) unsigned short ctrl = serial_port_in(port, SCFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if ((port->flags & UPF_HARD_FLOW) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) (termios->c_cflag & CRTSCTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* There is no CTS interrupt to restart the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) port->status |= UPSTAT_AUTOCTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* MCE is enabled when RTS is raised */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) s->autorts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) * As we've done a sci_reset() above, ensure we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * interfere with the FIFOs while toggling MCE. As the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) * reset values could still be set, simply mask them out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) serial_port_out(port, SCFCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (port->flags & UPF_HARD_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* Refresh (Auto) RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) sci_set_mctrl(port, port->mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) scr_val |= SCSCR_RE | SCSCR_TE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) if ((srr + 1 == 5) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) * In asynchronous mode, when the sampling rate is 1/5, first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) * received data may become invalid on some SCIFA and SCIFB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) * To avoid this problem wait more than 1 serial data time (1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) * bit time x serial data number) after setting SCSCR.RE = 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) udelay(DIV_ROUND_UP(10 * 1000000, baud));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) * Calculate delay for 2 DMA buffers (4 FIFO).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) * See serial_core.c::uart_update_timeout().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) * function calculates 1 jiffie for the data plus 5 jiffies for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) * buffers (4 FIFO sizes), but when performing a faster transfer, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) * value obtained by this formula is too small. Therefore, if the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) * is smaller than 20ms, use 20ms as the timeout value for DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) s->rx_frame = (10000 * bits) / (baud / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #ifdef CONFIG_SERIAL_SH_SCI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (s->rx_timeout < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) s->rx_timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) if ((termios->c_cflag & CREAD) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) sci_start_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) sci_port_disable(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) if (UART_ENABLE_MS(port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) sci_enable_ms(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static void sci_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) struct sci_port *sci_port = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) case UART_PM_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) sci_port_disable(sci_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) sci_port_enable(sci_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static const char *sci_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) switch (port->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) case PORT_IRDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return "irda";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) case PORT_SCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return "sci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) case PORT_SCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return "scif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) case PORT_SCIFA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return "scifa";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) case PORT_SCIFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) return "scifb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) case PORT_HSCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return "hscif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static int sci_remap_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) struct sci_port *sport = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) * Nothing to do if there's already an established membase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) if (port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) port->membase = ioremap(port->mapbase, sport->reg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (unlikely(!port->membase)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) dev_err(port->dev, "can't remap port#%d\n", port->line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) * For the simple (and majority of) cases where we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * need to do any remapping, just cast the cookie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) * directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) port->membase = (void __iomem *)(uintptr_t)port->mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static void sci_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) struct sci_port *sport = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) iounmap(port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) release_mem_region(port->mapbase, sport->reg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static int sci_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) struct sci_port *sport = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) res = request_mem_region(port->mapbase, sport->reg_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) dev_name(port->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (unlikely(res == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) dev_err(port->dev, "request_mem_region failed.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) ret = sci_remap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (unlikely(ret != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static void sci_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) struct sci_port *sport = to_sci_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) port->type = sport->cfg->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) sci_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (ser->baud_base < 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) /* No paper tape reader for Mitch.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) static const struct uart_ops sci_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .tx_empty = sci_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .set_mctrl = sci_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .get_mctrl = sci_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) .start_tx = sci_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .stop_tx = sci_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .stop_rx = sci_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .enable_ms = sci_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .break_ctl = sci_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .startup = sci_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .shutdown = sci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .flush_buffer = sci_flush_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .set_termios = sci_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) .pm = sci_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .type = sci_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .release_port = sci_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .request_port = sci_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .config_port = sci_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .verify_port = sci_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .poll_get_char = sci_poll_get_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .poll_put_char = sci_poll_put_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) const char *clk_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) [SCI_FCK] = "fck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) [SCI_SCK] = "sck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) [SCI_BRG_INT] = "brg_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) [SCI_SCIF_CLK] = "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) if (sci_port->cfg->type == PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) clk_names[SCI_SCK] = "hsck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) for (i = 0; i < SCI_NUM_CLKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) clk = devm_clk_get(dev, clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) if (PTR_ERR(clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) if (IS_ERR(clk) && i == SCI_FCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) * "fck" used to be called "sci_ick", and we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * maintain DT backward compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) clk = devm_clk_get(dev, "sci_ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) if (PTR_ERR(clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) * Not all SH platforms declare a clock lookup entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) * for SCI devices, in which case we need to get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) * global "peripheral_clk" clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) clk = devm_clk_get(dev, "peripheral_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) clk, clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) static const struct sci_port_params *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) sci_probe_regmap(const struct plat_sci_port *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) unsigned int regtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) if (cfg->regtype != SCIx_PROBE_REGTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) return &sci_port_params[cfg->regtype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) switch (cfg->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) case PORT_SCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) regtype = SCIx_SCI_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) case PORT_IRDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) regtype = SCIx_IRDA_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) case PORT_SCIFA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) regtype = SCIx_SCIFA_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) case PORT_SCIFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) regtype = SCIx_SCIFB_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) case PORT_SCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) * The SH-4 is a bit of a misnomer here, although that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) * where this particular port layout originated. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) * configuration (or some slight variation thereof)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) * remains the dominant model for all SCIFs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) regtype = SCIx_SH4_SCIF_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) case PORT_HSCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) regtype = SCIx_HSCIF_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) pr_err("Can't probe register map for given port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) return &sci_port_params[regtype];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) static int sci_init_single(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) struct sci_port *sci_port, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) const struct plat_sci_port *p, bool early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) struct uart_port *port = &sci_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) const struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) sci_port->cfg = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) port->ops = &sci_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) port->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) port->line = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) if (res == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) port->mapbase = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) sci_port->reg_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) sci_port->irqs[i] = platform_get_irq_optional(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) sci_port->irqs[i] = platform_get_irq(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) /* The SCI generates several interrupts. They can be muxed together or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) * connected to different interrupt lines. In the muxed case only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) * interrupt resource is specified as there is only one interrupt ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) * In the non-muxed case, up to 6 interrupt signals might be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) * from the SCI, however those signals might have their own individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) * interrupt ID numbers, or muxed together with another interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (sci_port->irqs[0] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) if (sci_port->irqs[1] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) sci_port->irqs[i] = sci_port->irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) sci_port->params = sci_probe_regmap(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) if (unlikely(sci_port->params == NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) switch (p->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) case PORT_SCIFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) sci_port->rx_trigger = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) case PORT_HSCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) sci_port->rx_trigger = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) case PORT_SCIFA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) sci_port->rx_trigger = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) case PORT_SCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /* RX triggering not implemented for this IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) sci_port->rx_trigger = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) sci_port->rx_trigger = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) sci_port->rx_trigger = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) sci_port->rx_fifo_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) sci_port->hscif_tot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) * match the SoC datasheet, this should be investigated. Let platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) * data override the sampling rate for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) sci_port->sampling_rate_mask = p->sampling_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) ? SCI_SR(p->sampling_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) : sci_port->params->sampling_rate_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) if (!early) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) ret = sci_init_clocks(sci_port, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) port->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) pm_runtime_enable(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) port->type = p->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) port->fifosize = sci_port->params->fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) if (port->type == PORT_SCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) if (sci_port->reg_size >= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) port->regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) port->regshift = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) * The UART port needs an IRQ value, so we peg this to the RX IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) * for the multi-IRQ ports, which is where we are primarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) * concerned with the shutdown path synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) * For the muxed case there's nothing more to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) port->irq = sci_port->irqs[SCIx_RXI_IRQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) port->irqflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) port->serial_in = sci_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) port->serial_out = sci_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) static void sci_cleanup_single(struct sci_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) pm_runtime_disable(port->port.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) static void serial_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) sci_poll_put_char(port, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) * Print a string to the serial port trying not to disturb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) * any possible real use of the port...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) static void serial_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) unsigned count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) struct sci_port *sci_port = &sci_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) struct uart_port *port = &sci_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) unsigned short bits, ctrl, ctrl_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) if (port->sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) locked = spin_trylock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) /* first save SCSCR then disable interrupts, keep clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) ctrl = serial_port_in(port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) ctrl_temp = SCSCR_RE | SCSCR_TE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) uart_console_write(port, s, count, serial_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* wait until fifo is empty and last bit has been transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) while ((serial_port_in(port, SCxSR) & bits) != bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) /* restore the SCSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) serial_port_out(port, SCSCR, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) static int serial_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) struct sci_port *sci_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) struct uart_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) * Refuse to handle any bogus ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) if (co->index < 0 || co->index >= SCI_NPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) sci_port = &sci_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) port = &sci_port->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) * Refuse to handle uninitialized ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) if (!port->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) ret = sci_remap_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (unlikely(ret != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) return uart_set_options(port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) static struct console serial_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) .name = "ttySC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .write = serial_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .setup = serial_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .data = &sci_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct console early_serial_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .name = "early_ttySC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) .write = serial_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) static char early_serial_buf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static int sci_probe_earlyprintk(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) if (early_serial_console.data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) early_serial_console.index = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) serial_console_setup(&early_serial_console, early_serial_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (!strstr(early_serial_buf, "keep"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) early_serial_console.flags |= CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) register_console(&early_serial_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) #define SCI_CONSOLE (&serial_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) static inline int sci_probe_earlyprintk(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) #define SCI_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) static DEFINE_MUTEX(sci_uart_registration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) static struct uart_driver sci_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) .driver_name = "sci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) .dev_name = "ttySC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) .major = SCI_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .minor = SCI_MINOR_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .nr = SCI_NPORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .cons = SCI_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) static int sci_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) struct sci_port *port = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) unsigned int type = port->port.type; /* uart_remove_... clears it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) sci_ports_in_use &= ~BIT(port->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) uart_remove_one_port(&sci_uart_driver, &port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) sci_cleanup_single(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) if (port->port.fifosize > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static const struct of_device_id of_sci_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) /* SoC-specific types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) .compatible = "renesas,scif-r7s72100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .compatible = "renesas,scif-r7s9210",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) /* Family-specific types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .compatible = "renesas,rcar-gen1-scif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .compatible = "renesas,rcar-gen2-scif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) .compatible = "renesas,rcar-gen3-scif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) /* Generic types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) .compatible = "renesas,scif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .compatible = "renesas,scifa",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) .compatible = "renesas,scifb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) .compatible = "renesas,hscif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .compatible = "renesas,sci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) /* Terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) MODULE_DEVICE_TABLE(of, of_sci_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) unsigned int *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) struct plat_sci_port *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) struct sci_port *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) const void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) if (!IS_ENABLED(CONFIG_OF) || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* Get the line number from the aliases node. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) id = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) if (id < 0 && ~sci_ports_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) id = ffz(sci_ports_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) if (id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) if (id >= ARRAY_SIZE(sci_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) dev_err(&pdev->dev, "serial%d out of range\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) sp = &sci_ports[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) *dev_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) p->type = SCI_OF_TYPE(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) p->regtype = SCI_OF_REGTYPE(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) static int sci_probe_single(struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) struct plat_sci_port *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) struct sci_port *sciport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (unlikely(index >= SCI_NPORTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) index+1, SCI_NPORTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) if (sci_ports_in_use & BIT(index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) mutex_lock(&sci_uart_registration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) if (!sci_uart_driver.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) ret = uart_register_driver(&sci_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) mutex_unlock(&sci_uart_registration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) mutex_unlock(&sci_uart_registration_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) ret = sci_init_single(dev, sciport, index, p, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) if (IS_ERR(sciport->gpios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) return PTR_ERR(sciport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) if (sciport->has_rtscts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) sciport->port.flags |= UPF_HARD_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) sci_cleanup_single(sciport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) static int sci_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) struct plat_sci_port *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) struct sci_port *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) unsigned int dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) * If we've come here via earlyprintk initialization, head off to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) * the special early probe. We don't have sufficient device state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) * to make it beyond this yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) #ifdef CONFIG_SUPERH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (is_sh_early_platform_device(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) return sci_probe_earlyprintk(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) if (dev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) p = sci_parse_dt(dev, &dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) p = dev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (p == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) dev_err(&dev->dev, "no platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) dev_id = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) sp = &sci_ports[dev_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) platform_set_drvdata(dev, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) ret = sci_probe_single(dev, dev_id, p, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) if (sp->port.fifosize > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) sp->port.type == PORT_HSCIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) if (sp->port.fifosize > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) device_remove_file(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) &dev_attr_rx_fifo_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) #ifdef CONFIG_SH_STANDARD_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) sh_bios_gdb_detach();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) sci_ports_in_use |= BIT(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) static __maybe_unused int sci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) struct sci_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) uart_suspend_port(&sci_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) static __maybe_unused int sci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) struct sci_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) uart_resume_port(&sci_uart_driver, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) static struct platform_driver sci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) .probe = sci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) .remove = sci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) .name = "sh-sci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) .pm = &sci_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) .of_match_table = of_match_ptr(of_sci_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) static int __init sci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) pr_info("%s\n", banner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) return platform_driver_register(&sci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static void __exit sci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) platform_driver_unregister(&sci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) if (sci_uart_driver.state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) uart_unregister_driver(&sci_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) sh_early_platform_init_buffer("earlyprintk", &sci_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) early_serial_buf, ARRAY_SIZE(early_serial_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) static struct plat_sci_port port_cfg __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) static int __init early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) device->port.serial_in = sci_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) device->port.serial_out = sci_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) device->port.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) port_cfg.type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) sci_ports[0].cfg = &port_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) sci_ports[0].params = sci_probe_regmap(&port_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) sci_serial_out(&sci_ports[0].port, SCSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) SCSCR_RE | SCSCR_TE | port_cfg.scscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) device->con->write = serial_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) static int __init sci_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) return early_console_setup(device, PORT_SCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) static int __init scif_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) return early_console_setup(device, PORT_SCIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) static int __init rzscifa_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) return early_console_setup(device, PORT_SCIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static int __init scifa_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) return early_console_setup(device, PORT_SCIFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) static int __init scifb_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) return early_console_setup(device, PORT_SCIFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) static int __init hscif_early_console_setup(struct earlycon_device *device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) return early_console_setup(device, PORT_HSCIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) module_init(sci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) module_exit(sci_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) MODULE_ALIAS("platform:sh-sci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) MODULE_AUTHOR("Paul Mundt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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