^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for the asynchronous serial interface (DUART) included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Derived from drivers/char/sb1250_duart.c for which the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * copyright applies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/major.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/refcount.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/sibyte/sb1250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/sibyte/sb1250_uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/sibyte/swarm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/sibyte/bcm1480_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/sibyte/bcm1480_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <asm/sibyte/sb1250_int.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SBD_INT(line) (K_INT_UART_0 + (line))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #error invalid SB1250 UART configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DUART_MAX_CHIP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DUART_MAX_SIDE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Per-port state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct sbd_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sbd_duart *duart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char __iomem *memctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int tx_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int initialised;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Per-DUART state for the shared register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sbd_duart {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sbd_port sport[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long mapctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) refcount_t map_guard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define to_sport(uport) container_of(uport, struct sbd_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Reading and writing SB1250 DUART registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * There are three register spaces: two per-channel ones and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * a shared one. We have to define accessors appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * All registers are 64-bit and all but the Baud Rate Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * registers only define 8 least significant bits. There is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * also a workaround to take into account. Raw accessors use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * the full register width, but cooked ones truncate it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * intentionally so that the rest of the driver does not care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u64 __read_sbdchn(struct sbd_port *sport, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *csr = sport->port.membase + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return __raw_readq(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static u64 __read_sbdshr(struct sbd_port *sport, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *csr = sport->memctrl + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return __raw_readq(csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *csr = sport->port.membase + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writeq(value, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *csr = sport->memctrl + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __raw_writeq(value, csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * In bug 1956, we get glitches that can mess up uart registers. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * "read-mode-reg after any register access" is an accepted workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void __war_sbd1956(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __read_sbdchn(sport, R_DUART_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __read_sbdchn(sport, R_DUART_MODE_REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned char retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) retval = __read_sbdchn(sport, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __war_sbd1956(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned char retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) retval = __read_sbdshr(sport, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __war_sbd1956(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __write_sbdchn(sport, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __war_sbd1956(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __write_sbdshr(sport, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __war_sbd1956(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int sbd_receive_ready(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int sbd_receive_drain(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) while (sbd_receive_ready(sport) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) read_sbdchn(sport, R_DUART_RX_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) while (!sbd_transmit_ready(sport) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int sbd_transmit_empty(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int sbd_line_drain(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int loops = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) while (!sbd_transmit_empty(sport) && --loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static unsigned int sbd_tx_empty(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static unsigned int sbd_get_mctrl(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int mctrl, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) status = read_sbdshr(sport, R_DUART_IN_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) status >>= (uport->line) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int clr = 0, set = 0, mode2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (mctrl & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) set |= M_DUART_SET_OPR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clr |= M_DUART_CLR_OPR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) set |= M_DUART_SET_OPR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) clr |= M_DUART_CLR_OPR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clr <<= (uport->line) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) set <<= (uport->line) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mode2 &= ~M_DUART_CHAN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mode2 |= V_DUART_CHAN_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) write_sbdshr(sport, R_DUART_SET_OPR, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void sbd_stop_tx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sport->tx_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void sbd_start_tx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Enable tx interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mask |= M_DUART_IMR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Go!, go!, go!... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sport->tx_stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void sbd_stop_rx(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void sbd_enable_ms(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) write_sbdchn(sport, R_DUART_AUXCTL_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void sbd_break_ctl(struct uart_port *uport, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void sbd_receive_chars(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct uart_icount *icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int status, ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (count = 16; count; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) status = read_sbdchn(sport, R_DUART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!(status & M_DUART_RX_RDY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ch = read_sbdchn(sport, R_DUART_RX_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) icount = &uport->icount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) icount->rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (unlikely(status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (status & M_DUART_RCVD_BRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) icount->brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (uart_handle_break(uport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) } else if (status & M_DUART_FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) icount->frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else if (status & M_DUART_PARITY_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) icount->parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (status & M_DUART_OVRUN_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) icount->overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status &= uport->read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (status & M_DUART_RCVD_BRK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else if (status & M_DUART_FRM_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else if (status & M_DUART_PARITY_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (uart_handle_sysrq_char(uport, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) tty_flip_buffer_push(&uport->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void sbd_transmit_chars(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct circ_buf *xmit = &sport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int stop_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* XON/XOFF chars. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (sport->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) sport->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* If nothing to do or stopped or hardware stopped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Send char. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!stop_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) uart_write_wakeup(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Are we are done? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (stop_tx || uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Disable tx interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mask &= ~M_DUART_IMR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void sbd_status_handle(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) delta >>= (uport->line) % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) uport->icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) S_DUART_IN_PIN_CHNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) wake_up_interruptible(&uport->state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static irqreturn_t sbd_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct sbd_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) irqreturn_t status = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) for (count = 16; count; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) intstat = read_sbdshr(sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) R_DUART_ISRREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) intstat &= read_sbdshr(sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) R_DUART_IMRREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) intstat &= M_DUART_ISR_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!intstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (intstat & M_DUART_ISR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sbd_receive_chars(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (intstat & M_DUART_ISR_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) sbd_status_handle(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (intstat & M_DUART_ISR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) sbd_transmit_chars(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) status = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int sbd_startup(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int mode1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = request_irq(sport->port.irq, sbd_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) IRQF_SHARED, "sb1250-duart", sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Clear the receive FIFO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sbd_receive_drain(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Clear the interrupt registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Set rx/tx interrupt to FIFO available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Disable tx, enable rx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) sport->tx_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Enable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) M_DUART_IMR_IN | M_DUART_IMR_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void sbd_shutdown(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) sport->tx_stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) free_irq(sport->port.irq, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void sbd_init_port(struct sbd_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (sport->initialised)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* There is no DUART reset feature, so just set some sane defaults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) write_sbdchn(sport, R_DUART_FULL_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) write_sbdchn(sport, R_DUART_OPCR_X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) sport->initialised = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ktermios *old_termios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int mode1 = 0, mode2 = 0, aux = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int oldmode1, oldmode2, oldaux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int baud, brg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) M_DUART_BITS_PER_CHAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) auxmask |= ~M_DUART_CTS_CHNG_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* Byte size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Unsupported, leave unchanged. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mode1mask |= M_DUART_PARITY_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mode1 |= V_DUART_BITS_PER_CHAR_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mode1 |= V_DUART_BITS_PER_CHAR_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Parity and stop bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mode2 |= M_DUART_STOP_BIT_LEN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mode2 |= M_DUART_STOP_BIT_LEN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mode1 |= V_DUART_PARITY_MODE_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mode1 |= V_DUART_PARITY_MODE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mode1 |= M_DUART_PARITY_TYPE_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mode1 |= M_DUART_PARITY_TYPE_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) brg = V_DUART_BAUD_RATE(baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* The actual lower bound is 1221bps, so compensate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (brg > M_DUART_CLK_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) brg = M_DUART_CLK_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) uart_update_timeout(uport, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) uport->read_status_mask = M_DUART_OVRUN_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) uport->read_status_mask |= M_DUART_FRM_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) M_DUART_PARITY_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) uport->read_status_mask |= M_DUART_RCVD_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) uport->ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) uport->ignore_status_mask |= M_DUART_FRM_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) M_DUART_PARITY_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uport->ignore_status_mask |= M_DUART_RCVD_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (termios->c_cflag & CREAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) command = M_DUART_RX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) command = M_DUART_RX_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (termios->c_cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) aux |= M_DUART_CTS_CHNG_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) aux &= ~M_DUART_CTS_CHNG_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) spin_lock(&uport->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (sport->tx_stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) command |= M_DUART_TX_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) command |= M_DUART_TX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!sport->tx_stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) sbd_line_drain(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) write_sbdchn(sport, R_DUART_CLK_SEL, brg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) write_sbdchn(sport, R_DUART_CMD, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_unlock(&uport->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char *sbd_type(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return "SB1250 DUART";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void sbd_release_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct sbd_duart *duart = sport->duart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) iounmap(sport->memctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sport->memctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) iounmap(uport->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uport->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if(refcount_dec_and_test(&duart->map_guard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int sbd_map_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct sbd_duart *duart = sport->duart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!uport->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) uport->membase = ioremap(uport->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!uport->membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) printk(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!sport->memctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sport->memctrl = ioremap(duart->mapctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!sport->memctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) printk(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) iounmap(uport->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) uport->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int sbd_request_port(struct uart_port *uport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct sbd_duart *duart = to_sport(uport)->duart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "sb1250-duart")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) printk(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) refcount_inc(&duart->map_guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (refcount_read(&duart->map_guard) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "sb1250-duart")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) refcount_dec(&duart->map_guard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) printk(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = sbd_map_port(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (refcount_dec_and_test(&duart->map_guard))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) release_mem_region(duart->mapctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void sbd_config_port(struct uart_port *uport, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (sbd_request_port(uport))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) uport->type = PORT_SB1250_DUART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) sbd_init_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ser->irq != uport->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ser->baud_base != uport->uartclk / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const struct uart_ops sbd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .tx_empty = sbd_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .set_mctrl = sbd_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .get_mctrl = sbd_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .stop_tx = sbd_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .start_tx = sbd_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .stop_rx = sbd_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .enable_ms = sbd_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .break_ctl = sbd_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .startup = sbd_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .shutdown = sbd_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .set_termios = sbd_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .type = sbd_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .release_port = sbd_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .request_port = sbd_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .config_port = sbd_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .verify_port = sbd_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Initialize SB1250 DUART port structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void __init sbd_probe_duarts(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int probed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int chip, side;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int max_lines, line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (probed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Set the number of available units based on the SOC type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) switch (soc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case K_SYS_SOC_TYPE_BCM1x55:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case K_SYS_SOC_TYPE_BCM1x80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) max_lines = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Assume at least two serial ports at the normal address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) max_lines = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) probed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) chip++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) side++, line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct sbd_port *sport = &sbd_duarts[chip].sport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sport->duart = &sbd_duarts[chip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) uport->irq = SBD_INT(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) uport->uartclk = 100000000 / 20 * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) uport->fifosize = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) uport->iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uport->flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) uport->ops = &sbd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) uport->line = line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) uport->mapbase = SBD_CHANREGS(line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SB1250_DUART_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Serial console stuff. Very basic, polling driver for doing serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * console output. The console_lock is held by the caller, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * shouldn't be interrupted for more console activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static void sbd_console_putchar(struct uart_port *uport, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct sbd_port *sport = to_sport(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) sbd_transmit_drain(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) write_sbdchn(sport, R_DUART_TX_HOLD, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void sbd_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int chip = co->index / DUART_MAX_SIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int side = co->index % DUART_MAX_SIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct sbd_port *sport = &sbd_duarts[chip].sport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Disable transmit interrupts and enable the transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) spin_lock_irqsave(&uport->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mask & ~M_DUART_IMR_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) spin_unlock_irqrestore(&uport->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uart_console_write(&sport->port, s, count, sbd_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Restore transmit interrupts and the transmitter enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) spin_lock_irqsave(&uport->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) sbd_line_drain(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (sport->tx_stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) spin_unlock_irqrestore(&uport->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int __init sbd_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int chip = co->index / DUART_MAX_SIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int side = co->index % DUART_MAX_SIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct sbd_port *sport = &sbd_duarts[chip].sport[side];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int baud = 115200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!sport->duart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ret = sbd_map_port(uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) sbd_init_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return uart_set_options(uport, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static struct uart_driver sbd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct console sbd_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "duart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .write = sbd_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .setup = sbd_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .data = &sbd_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int __init sbd_serial_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) sbd_probe_duarts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) register_console(&sbd_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) console_initcall(sbd_serial_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define SERIAL_SB1250_DUART_CONSOLE &sbd_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define SERIAL_SB1250_DUART_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct uart_driver sbd_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .driver_name = "sb1250_duart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .dev_name = "duart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .minor = SB1250_DUART_MINOR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .cons = SERIAL_SB1250_DUART_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Set up the driver and register it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int __init sbd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) sbd_probe_duarts();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = uart_register_driver(&sbd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (sport->duart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uart_add_one_port(&sbd_reg, uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Unload the driver. Unregister stuff, get ready to go away. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void __exit sbd_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct uart_port *uport = &sport->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (sport->duart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) uart_remove_one_port(&sbd_reg, uport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) uart_unregister_driver(&sbd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) module_init(sbd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) module_exit(sbd_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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