^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for SA11x0 serial ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2000 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/sa11x0-serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "serial_mctrl_gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* We've been assigned a range on the "Low-density serial ports" major */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SERIAL_SA1100_MAJOR 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MINOR_START 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NR_PORTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SA1100_ISR_PASS_LIMIT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Convert from ignore_status_mask or read_status_mask to UTSR[01]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SM_TO_UTSR0(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SM_TO_UTSR1(x) ((x) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UTSR0_TO_SM(x) ((x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UTSR1_TO_SM(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * This is the size of our serial port register set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UART_PORT_SIZE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This determines how often we check the modem status signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * for any change. They generally aren't connected to an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * so we have to poll them. We also check immediately before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * filling the TX fifo incase CTS has been dropped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCTRL_TIMEOUT (250*HZ/1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct sa1100_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mctrl_gpios *gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Handle any change of modem status signal since we were last called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void sa1100_mctrl_check(struct sa1100_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int status, changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) status = sport->port.ops->get_mctrl(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) changed = status ^ sport->old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (changed == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sport->old_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (changed & TIOCM_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sport->port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (changed & TIOCM_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sport->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (changed & TIOCM_CAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (changed & TIOCM_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * This is our per-port timeout handler, for checking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * modem status signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void sa1100_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct sa1100_port *sport = from_timer(sport, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (sport->port.state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sa1100_mctrl_check(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * interrupts disabled on entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void sa1100_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 utcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * port locked and interrupts disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void sa1100_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 utcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Interrupts enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void sa1100_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 utcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Set the modem control timer to fire immediately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void sa1100_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mod_timer(&sport->timer, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mctrl_gpio_enable_ms(sport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sa1100_rx_chars(struct sa1100_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int status, ch, flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) UTSR0_TO_SM(UART_GET_UTSR0(sport));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) while (status & UTSR1_TO_SM(UTSR1_RNE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ch = UART_GET_CHAR(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sport->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) flg = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * note that the error handling code is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * out of the main execution path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (status & UTSR1_TO_SM(UTSR1_PRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sport->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else if (status & UTSR1_TO_SM(UTSR1_FRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sport->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (status & UTSR1_TO_SM(UTSR1_ROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sport->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) status &= sport->port.read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (status & UTSR1_TO_SM(UTSR1_PRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) flg = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else if (status & UTSR1_TO_SM(UTSR1_FRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) flg = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sport->port.sysrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (uart_handle_sysrq_char(&sport->port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ignore_char:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) UTSR0_TO_SM(UART_GET_UTSR0(sport));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_unlock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tty_flip_buffer_push(&sport->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_lock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void sa1100_tx_chars(struct sa1100_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct circ_buf *xmit = &sport->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (sport->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) UART_PUT_CHAR(sport, sport->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sport->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Check the modem control lines before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * transmitting anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sa1100_mctrl_check(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sa1100_stop_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Tried using FIFO (not checking TNF) for fifo fill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * still had the '4 bytes repeated' problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sport->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) uart_write_wakeup(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sa1100_stop_tx(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static irqreturn_t sa1100_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sa1100_port *sport = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int status, pass_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) status = UART_GET_UTSR0(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (status & (UTSR0_RFS | UTSR0_RID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Clear the receiver idle bit, if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (status & UTSR0_RID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) UART_PUT_UTSR0(sport, UTSR0_RID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) sa1100_rx_chars(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Clear the relevant break bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (status & (UTSR0_RBB | UTSR0_REB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (status & UTSR0_RBB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sport->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status & UTSR0_REB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uart_handle_break(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (status & UTSR0_TFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sa1100_tx_chars(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) status = UART_GET_UTSR0(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) status &= SM_TO_UTSR0(sport->port.read_status_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ~UTSR0_TFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_unlock(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Return TIOCSER_TEMT when transmitter is not busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static unsigned int sa1100_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static unsigned int sa1100_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mctrl_gpio_get(sport->gpios, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mctrl_gpio_set(sport->gpios, mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Interrupts always disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void sa1100_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int utcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) utcr3 |= UTCR3_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) utcr3 &= ~UTCR3_BRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) UART_PUT_UTCR3(sport, utcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int sa1100_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Allocate the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) retval = request_irq(sport->port.irq, sa1100_int, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "sa11x0-uart", sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Finally, clear and enable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) UART_PUT_UTSR0(sport, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Enable modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_lock_irq(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sa1100_enable_ms(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spin_unlock_irq(&sport->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void sa1100_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Stop our timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) del_timer_sync(&sport->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * Free the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) free_irq(sport->port.irq, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Disable all interrupts, port and break condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) UART_PUT_UTCR3(sport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int utcr0, old_utcr3, baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * We only support CS7 and CS8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) while ((termios->c_cflag & CSIZE) != CS7 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) (termios->c_cflag & CSIZE) != CS8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) termios->c_cflag &= ~CSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) termios->c_cflag |= old_csize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) old_csize = CS8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((termios->c_cflag & CSIZE) == CS8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) utcr0 = UTCR0_DSS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) utcr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) utcr0 |= UTCR0_SBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) utcr0 |= UTCR0_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) utcr0 |= UTCR0_OES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Ask the core to calculate the divisor for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) quot = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spin_lock_irqsave(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sport->port.read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (termios->c_iflag & (BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) sport->port.read_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sport->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sport->port.ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sport->port.ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sport->port.ignore_status_mask |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) UTSR1_TO_SM(UTSR1_ROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) del_timer_sync(&sport->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * Update the per-port timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * disable interrupts and drain transmitter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) old_utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) while (UART_GET_UTSR1(sport) & UTSR1_TBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* then, disable everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) UART_PUT_UTCR3(sport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* set the parity, stop bits and data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) UART_PUT_UTCR0(sport, utcr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* set the baud rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) quot -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) UART_PUT_UTCR2(sport, (quot & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) UART_PUT_UTSR0(sport, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) UART_PUT_UTCR3(sport, old_utcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sa1100_enable_ms(&sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) spin_unlock_irqrestore(&sport->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const char *sa1100_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Release the memory region(s) being used by 'port'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void sa1100_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Request the memory region(s) being used by 'port'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int sa1100_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "sa11x0-uart") != NULL ? 0 : -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Configure/autoconfigure the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void sa1100_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (flags & UART_CONFIG_TYPE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) sa1100_request_port(&sport->port) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) sport->port.type = PORT_SA1100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Verify the new serial_struct (for TIOCSSERIAL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * The only change we allow are to the flags and type, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * even then only between PORT_SA1100 and PORT_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (sport->port.irq != ser->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ser->io_type != SERIAL_IO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (sport->port.uartclk / 16 != ser->baud_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if ((void *)sport->port.mapbase != ser->iomem_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (sport->port.iobase != ser->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ser->hub6 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct uart_ops sa1100_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .tx_empty = sa1100_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .set_mctrl = sa1100_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .get_mctrl = sa1100_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .stop_tx = sa1100_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .start_tx = sa1100_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .stop_rx = sa1100_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enable_ms = sa1100_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .break_ctl = sa1100_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .startup = sa1100_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .shutdown = sa1100_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .set_termios = sa1100_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .type = sa1100_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .release_port = sa1100_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .request_port = sa1100_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .config_port = sa1100_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .verify_port = sa1100_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct sa1100_port sa1100_ports[NR_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Setup the SA1100 serial ports. Note that we don't include the IrDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * port here since we have our own SIR/FIR driver (see drivers/net/irda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Which serial port this ends up being depends on the machine you're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * running this kernel on. I'm not convinced that this is a good idea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * but that's the way it traditionally works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * used here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void __init sa1100_init_ports(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int first = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < NR_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sa1100_ports[i].port.uartclk = 3686400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) sa1100_ports[i].port.ops = &sa1100_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sa1100_ports[i].port.fifosize = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) sa1100_ports[i].port.line = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) sa1100_ports[i].port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * make transmit lines outputs, so that when the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * is closed, the output is in the MARK state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PPDR |= PPC_TXD1 | PPC_TXD3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PPSR |= PPC_TXD1 | PPC_TXD3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (fns->get_mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) sa1100_pops.get_mctrl = fns->get_mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (fns->set_mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) sa1100_pops.set_mctrl = fns->set_mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) sa1100_pops.pm = fns->pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * FIXME: fns->set_wake is unused - this should be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * the suspend() callback if device_may_wakeup(dev)) is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void __init sa1100_register_uart(int idx, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (idx >= NR_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sa1100_ports[idx].port.irq = IRQ_Ser1UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) sa1100_ports[idx].port.irq = IRQ_Ser3UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #ifdef CONFIG_SERIAL_SA1100_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static void sa1100_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct sa1100_port *sport =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) container_of(port, struct sa1100_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) UART_PUT_CHAR(sport, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * Interrupts are disabled on entering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) sa1100_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct sa1100_port *sport = &sa1100_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned int old_utcr3, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * First, save UTCR3 and then disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) old_utcr3 = UART_GET_UTCR3(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) UTCR3_TXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) uart_console_write(&sport->port, s, count, sa1100_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * and restore UTCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) status = UART_GET_UTSR1(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } while (status & UTSR1_TBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) UART_PUT_UTCR3(sport, old_utcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * If the port was already initialised (eg, by a boot loader),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * try to determine the current setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) sa1100_console_get_options(struct sa1100_port *sport, int *baud,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int *parity, int *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int utcr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* ok, the port was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned int utcr0, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) utcr0 = UART_GET_UTCR0(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (utcr0 & UTCR0_PE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (utcr0 & UTCR0_OES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *parity = 'e';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) *parity = 'o';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (utcr0 & UTCR0_DSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) quot &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *baud = sport->port.uartclk / (16 * (quot + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sa1100_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct sa1100_port *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Check whether an invalid uart number has been specified, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * if so, search for the first available port that does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * console support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (co->index == -1 || co->index >= NR_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) sport = &sa1100_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sa1100_console_get_options(sport, &baud, &parity, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return uart_set_options(&sport->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct uart_driver sa1100_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct console sa1100_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "ttySA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .write = sa1100_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .setup = sa1100_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .data = &sa1100_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int __init sa1100_rs_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) sa1100_init_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) register_console(&sa1100_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) console_initcall(sa1100_rs_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define SA1100_CONSOLE &sa1100_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define SA1100_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct uart_driver sa1100_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .driver_name = "ttySA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .dev_name = "ttySA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .major = SERIAL_SA1100_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .minor = MINOR_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .nr = NR_PORTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .cons = SA1100_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct sa1100_port *sport = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) uart_suspend_port(&sa1100_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int sa1100_serial_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct sa1100_port *sport = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uart_resume_port(&sa1100_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) sport->port.dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) // mctrl_gpio_init() requires that the GPIO driver supports interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) // but we need to support GPIO drivers for hardware that has no such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) // interrupts. Use mctrl_gpio_init_noauto() instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (IS_ERR(sport->gpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int err = PTR_ERR(sport->gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) sport->gpios = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) platform_set_drvdata(dev, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return uart_add_one_port(&sa1100_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int sa1100_serial_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) for (i = 0; i < NR_PORTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (sa1100_ports[i].port.mapbase == res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (i == NR_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) sa1100_serial_add_one_port(&sa1100_ports[i], dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int sa1100_serial_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct sa1100_port *sport = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uart_remove_one_port(&sa1100_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static struct platform_driver sa11x0_serial_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .probe = sa1100_serial_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .remove = sa1100_serial_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .suspend = sa1100_serial_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .resume = sa1100_serial_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "sa11x0-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int __init sa1100_serial_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) printk(KERN_INFO "Serial: SA11x0 driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) sa1100_init_ports();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = uart_register_driver(&sa1100_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = platform_driver_register(&sa11x0_serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) uart_unregister_driver(&sa1100_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void __exit sa1100_serial_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) platform_driver_unregister(&sa11x0_serial_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) uart_unregister_driver(&sa1100_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) module_init(sa1100_serial_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) module_exit(sa1100_serial_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) MODULE_AUTHOR("Deep Blue Solutions Ltd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MODULE_DESCRIPTION("SA1100 generic serial port driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_ALIAS("platform:sa11x0-uart");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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