^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Inspired by, and loosely based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ar933x_uart.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * rocketport_infinity_express-linux-1.20.tar.gz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2004-2011 Comtrol, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_NAME "rp2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RP2_FW_NAME "rp2.fw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RP2_UCODE_BYTES 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PORTS_PER_ASIC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UART_CLOCK 44236800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FIFO_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* BAR0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RP2_FPGA_CTL0 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RP2_FPGA_CTL1 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RP2_IRQ_MASK 0x1ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RP2_IRQ_MASK_EN_m BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RP2_IRQ_STATUS 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* BAR1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RP2_ASIC_SPACING 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RP2_PORT_BASE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RP2_PORT_SPACING 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RP2_UCODE_BASE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RP2_UCODE_SPACING 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RP2_CLK_PRESCALER 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RP2_CH_IRQ_STAT 0xc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RP2_CH_IRQ_MASK 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RP2_ASIC_IRQ 0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RP2_ASIC_IRQ_EN_m BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RP2_GLOBAL_CMD 0xd0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RP2_ASIC_CFG 0xd04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* port registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RP2_DATA_DWORD 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RP2_DATA_BYTE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RP2_DATA_BYTE_BREAK_m BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* This lets uart_insert_char() drop bytes received on a !CREAD port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RP2_DUMMY_READ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RP2_DATA_BYTE_ERR_OVERRUN_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RP2_DATA_BYTE_ERR_FRAMING_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RP2_DATA_BYTE_BREAK_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RP2_RX_FIFO_COUNT 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RP2_TX_FIFO_COUNT 0x00e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RP2_CHAN_STAT 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RP2_CHAN_STAT_RXDATA_m BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RP2_CHAN_STAT_DCD_m BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RP2_CHAN_STAT_DSR_m BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RP2_CHAN_STAT_CTS_m BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RP2_CHAN_STAT_RI_m BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RP2_CHAN_STAT_OVERRUN_m BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RP2_CHAN_STAT_CTS_CHANGED_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) RP2_CHAN_STAT_CD_CHANGED_m | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) RP2_CHAN_STAT_RI_CHANGED_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RP2_TXRX_CTL 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RP2_TXRX_CTL_RXIRQ_m BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RP2_TXRX_CTL_RX_TRIG_s 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RP2_TXRX_CTL_RX_EN_m BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RP2_TXRX_CTL_TX_TRIG_s 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RP2_TXRX_CTL_TXIRQ_m BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RP2_TXRX_CTL_TX_EN_m BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RP2_TXRX_CTL_RTS_m BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RP2_TXRX_CTL_DTR_m BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RP2_TXRX_CTL_LOOP_m BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RP2_TXRX_CTL_BREAK_m BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RP2_TXRX_CTL_CMSPAR_m BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RP2_TXRX_CTL_nPARODD_m BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RP2_TXRX_CTL_PARENB_m BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RP2_UART_CTL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RP2_UART_CTL_MODE_s 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RP2_UART_CTL_FLUSH_RX_m BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RP2_UART_CTL_FLUSH_TX_m BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RP2_UART_CTL_RESET_CH_m BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RP2_UART_CTL_XMIT_EN_m BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RP2_UART_CTL_DATABITS_s 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RP2_UART_CTL_STOPBITS_m BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RP2_BAUD 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* ucode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RP2_TX_SWFLOW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RP2_TX_SWFLOW_ena 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RP2_TX_SWFLOW_dis 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RP2_RX_SWFLOW 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RP2_RX_SWFLOW_ena 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RP2_RX_SWFLOW_dis 0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RP2_RX_FIFO 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RP2_RX_FIFO_ena 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RP2_RX_FIFO_dis 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct uart_driver rp2_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .driver_name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .dev_name = "ttyRP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .nr = CONFIG_SERIAL_RP2_NR_UARTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct rp2_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct rp2_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ignore_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rp2_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *asic_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *ucode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct rp2_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct rp2_uart_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int n_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int initialized_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int minor_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int smpte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __iomem *bar0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void __iomem *bar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spinlock_t card_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RP_ID(prod) PCI_VDEVICE(RP, (prod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void rp2_decode_cap(const struct pci_device_id *id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int *ports, int *smpte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *ports = id->driver_data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *smpte = id->driver_data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static DEFINE_SPINLOCK(rp2_minor_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int rp2_minor_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rp2_alloc_ports(int n_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock(&rp2_minor_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* sorry, no support for hot unplugging individual cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = rp2_minor_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rp2_minor_next += n_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_unlock(&rp2_minor_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return container_of(port, struct rp2_uart_port, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void rp2_rmw(struct rp2_uart_port *up, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 clr_bits, u32 set_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 tmp = readl(up->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tmp &= ~clr_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tmp |= set_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(tmp, up->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) rp2_rmw(up, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rp2_rmw(up, reg, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned long flags, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_lock_irqsave(&up->card->card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) irq_mask &= ~BIT(ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_mask |= BIT(ch_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) spin_unlock_irqrestore(&up->card->card_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static unsigned int rp2_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct rp2_uart_port *up = port_to_up(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long tx_fifo_bytes, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * This should probably check the transmitter, not the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct rp2_uart_port *up = port_to_up(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) status = readl(up->base + RP2_CHAN_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void rp2_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void rp2_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void rp2_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break_state ? RP2_TXRX_CTL_BREAK_m : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void rp2_uart_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void __rp2_uart_set_termios(struct rp2_uart_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long cfl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long ifl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int baud_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writew(baud_div - 1, up->base + RP2_BAUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* data bits and stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rp2_rmw(up, RP2_UART_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* parity and hardware flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rp2_rmw(up, RP2_TXRX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) RP2_TXRX_CTL_CTSFLOW_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) RP2_TXRX_CTL_CTSFLOW_m) : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* XON/XOFF software flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) up->ucode + RP2_TX_SWFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) up->ucode + RP2_RX_SWFLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void rp2_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct ktermios *new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct rp2_uart_port *up = port_to_up(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int baud, baud_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) baud_div = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (tty_termios_baud_rate(new))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tty_termios_encode_baud_rate(new, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* ignore all characters if CREAD is not set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uart_update_timeout(port, new->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void rp2_rx_chars(struct rp2_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct tty_port *port = &up->port.state->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (; bytes != 0; bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) char ch = byte & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!uart_handle_sysrq_char(&up->port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) uart_insert_char(&up->port, byte, 0, ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) TTY_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (byte & RP2_DATA_BYTE_BREAK_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) uart_insert_char(&up->port, byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tty_flip_buffer_push(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void rp2_tx_chars(struct rp2_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (uart_tx_stopped(&up->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rp2_uart_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (; max_tx != 0; max_tx--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (up->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) up->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rp2_uart_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) uart_write_wakeup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static void rp2_ch_interrupt(struct rp2_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * The IRQ status bits are clear-on-write. Other status bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * this register aren't, so it's harmless to write to them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) status = readl(up->base + RP2_CHAN_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) writel(status, up->base + RP2_CHAN_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (status & RP2_CHAN_STAT_RXDATA_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rp2_rx_chars(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (status & RP2_CHAN_STAT_TXEMPTY_m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rp2_tx_chars(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) wake_up_interruptible(&up->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ch, handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ~readl(base + RP2_CH_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rp2_ch_interrupt(&card->ports[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct rp2_card *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) handled = rp2_asic_interrupt(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (card->n_ports >= PORTS_PER_ASIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) handled += rp2_asic_interrupt(card, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline void rp2_flush_fifos(struct rp2_uart_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rp2_rmw_set(up, RP2_UART_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) readl(up->base + RP2_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rp2_rmw_clr(up, RP2_UART_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int rp2_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct rp2_uart_port *up = port_to_up(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) rp2_flush_fifos(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) RP2_TXRX_CTL_RX_TRIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rp2_mask_ch_irq(up, up->idx, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void rp2_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct rp2_uart_port *up = port_to_up(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) rp2_uart_break_ctl(port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rp2_mask_ch_irq(up, up->idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const char *rp2_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void rp2_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Nothing to release ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int rp2_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* UARTs always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void rp2_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (flags & UART_CONFIG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) port->type = PORT_RP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int rp2_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const struct uart_ops rp2_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .tx_empty = rp2_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .set_mctrl = rp2_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .get_mctrl = rp2_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .stop_tx = rp2_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .start_tx = rp2_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .stop_rx = rp2_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .enable_ms = rp2_uart_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .break_ctl = rp2_uart_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .startup = rp2_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .shutdown = rp2_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .set_termios = rp2_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .type = rp2_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .release_port = rp2_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .request_port = rp2_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .config_port = rp2_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .verify_port = rp2_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 clk_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) writew(1, base + RP2_GLOBAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) readw(base + RP2_GLOBAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) writel(0, base + RP2_CLK_PRESCALER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* TDM clock configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) clk_cfg = readw(base + RP2_ASIC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) writew(clk_cfg, base + RP2_ASIC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* IRQ routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void rp2_init_card(struct rp2_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) writel(4, card->bar0 + RP2_FPGA_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) writel(0, card->bar0 + RP2_FPGA_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rp2_reset_asic(card, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (card->n_ports >= PORTS_PER_ASIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rp2_reset_asic(card, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) readl(up->base + RP2_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) writel(0, up->base + RP2_TXRX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) writel(0, up->base + RP2_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) readl(up->base + RP2_UART_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rp2_flush_fifos(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writeb(fw->data[i], up->ucode + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) rp2_uart_set_mctrl(&up->port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) rp2_rmw_set(up, RP2_TXRX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void rp2_remove_ports(struct rp2_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) for (i = 0; i < card->initialized_ports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) card->initialized_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) resource_size_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int i, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) phys_base = pci_resource_start(card->pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) for (i = 0; i < card->n_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct rp2_uart_port *rp = &card->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct uart_port *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int j = (unsigned)i % PORTS_PER_ASIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rp->asic_base = card->bar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rp->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rp->idx = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) p = &rp->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) p->line = card->minor_start + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) p->dev = &card->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) p->type = PORT_RP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) p->iotype = UPIO_MEM32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) p->uartclk = UART_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) p->regshift = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) p->fifosize = FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) p->ops = &rp2_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) p->irq = card->pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) p->membase = rp->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (i >= PORTS_PER_ASIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) rp->asic_base += RP2_ASIC_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) rp->base += RP2_ASIC_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) rp->ucode += RP2_ASIC_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) p->mapbase += RP2_ASIC_SPACING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) rp2_init_port(rp, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) rc = uart_add_one_port(&rp2_uart_driver, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(&card->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "error registering port %d: %d\n", i, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rp2_remove_ports(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) card->initialized_ports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int rp2_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct rp2_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct rp2_uart_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) void __iomem * const *bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pci_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) spin_lock_init(&card->card_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rc = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) bars = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) card->bar0 = bars[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) card->bar1 = bars[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) card->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rp2_decode_cap(id, &card->n_ports, &card->smpte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) card->minor_start = rp2_alloc_ports(card->n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (card->minor_start < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rp2_init_card(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) card->ports = ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) RP2_FW_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rc = rp2_load_firmware(card, fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) IRQF_SHARED, DRV_NAME, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void rp2_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct rp2_card *card = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rp2_remove_ports(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct pci_device_id rp2_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* RocketPort INFINITY cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* RocketPort EXPRESS cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static struct pci_driver rp2_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .id_table = rp2_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .probe = rp2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .remove = rp2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int __init rp2_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) rc = uart_register_driver(&rp2_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) rc = pci_register_driver(&rp2_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) uart_unregister_driver(&rp2_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static void __exit rp2_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pci_unregister_driver(&rp2_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) uart_unregister_driver(&rp2_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) module_init(rp2_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) module_exit(rp2_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MODULE_FIRMWARE(RP2_FW_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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