^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RDA8810PL serial device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright RDA Microelectronics Company Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2018 Manivannan Sadhasivam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RDA_UART_PORT_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RDA_UART_DEV_NAME "ttyRDA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RDA_UART_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RDA_UART_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RDA_UART_RXTX_BUFFER 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RDA_UART_IRQ_MASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RDA_UART_IRQ_CAUSE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RDA_UART_IRQ_TRIGGERS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RDA_UART_CMD_SET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RDA_UART_CMD_CLR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* UART_CTRL Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RDA_UART_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RDA_UART_DBITS_8 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RDA_UART_TX_SBITS_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RDA_UART_PARITY_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RDA_UART_PARITY(x) (((x) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RDA_UART_PARITY_ODD RDA_UART_PARITY(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RDA_UART_PARITY_EVEN RDA_UART_PARITY(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RDA_UART_PARITY_SPACE RDA_UART_PARITY(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RDA_UART_PARITY_MARK RDA_UART_PARITY(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RDA_UART_DIV_MODE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RDA_UART_IRDA_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RDA_UART_DMA_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RDA_UART_FLOW_CNT_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RDA_UART_LOOP_BACK_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RDA_UART_RX_LOCK_ERR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RDA_UART_RX_BREAK_LEN(x) (((x) & 0xf) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* UART_STATUS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RDA_UART_RX_FIFO(x) (((x) & 0x7f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RDA_UART_RX_FIFO_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RDA_UART_TX_FIFO(x) (((x) & 0x1f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RDA_UART_TX_FIFO_MASK (0x1f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RDA_UART_TX_ACTIVE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RDA_UART_RX_ACTIVE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RDA_UART_RX_OVERFLOW_ERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RDA_UART_TX_OVERFLOW_ERR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RDA_UART_RX_PARITY_ERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RDA_UART_RX_FRAMING_ERR BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RDA_UART_RX_BREAK_INT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RDA_UART_DCTS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RDA_UART_CTS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RDA_UART_DTR BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RDA_UART_CLK_ENABLED BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* UART_RXTX_BUFFER Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RDA_UART_RX_DATA(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RDA_UART_TX_DATA(x) (((x) & 0xff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* UART_IRQ_MASK Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RDA_UART_TX_MODEM_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RDA_UART_RX_DATA_AVAILABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RDA_UART_TX_DATA_NEEDED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RDA_UART_RX_TIMEOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RDA_UART_RX_LINE_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RDA_UART_TX_DMA_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RDA_UART_RX_DMA_DONE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RDA_UART_RX_DMA_TIMEOUT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RDA_UART_DTR_RISE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RDA_UART_DTR_FALL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* UART_IRQ_CAUSE Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RDA_UART_TX_MODEM_STATUS_U BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RDA_UART_RX_DATA_AVAILABLE_U BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RDA_UART_TX_DATA_NEEDED_U BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RDA_UART_RX_TIMEOUT_U BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RDA_UART_RX_LINE_ERR_U BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RDA_UART_TX_DMA_DONE_U BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RDA_UART_RX_DMA_DONE_U BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RDA_UART_RX_DMA_TIMEOUT_U BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RDA_UART_DTR_RISE_U BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RDA_UART_DTR_FALL_U BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* UART_TRIGGERS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RDA_UART_RX_TRIGGER(x) (((x) & 0x1f) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RDA_UART_TX_TRIGGER(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RDA_UART_AFC_LEVEL(x) (((x) & 0x1f) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* UART_CMD_SET Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RDA_UART_RI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RDA_UART_DCD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RDA_UART_DSR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RDA_UART_TX_BREAK_CONTROL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RDA_UART_TX_FINISH_N_WAIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RDA_UART_RTS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RDA_UART_RX_FIFO_RESET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RDA_UART_TX_FIFO_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RDA_UART_TX_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct uart_driver rda_uart_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct rda_uart_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define to_rda_uart_port(port) container_of(port, struct rda_uart_port, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct rda_uart_port *rda_uart_ports[RDA_UART_PORT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void rda_uart_write(struct uart_port *port, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel(val, port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline u32 rda_uart_read(struct uart_port *port, unsigned int off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return readl(port->membase + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static unsigned int rda_uart_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val = rda_uart_read(port, RDA_UART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = (val & RDA_UART_TX_FIFO_MASK) ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned int rda_uart_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int mctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 cmd_set, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cmd_set = rda_uart_read(port, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) status = rda_uart_read(port, RDA_UART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (cmd_set & RDA_UART_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mctrl |= TIOCM_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!(status & RDA_UART_CTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mctrl |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return mctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void rda_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (mctrl & TIOCM_RTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = rda_uart_read(port, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Clear RTS to stop to receive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val = rda_uart_read(port, RDA_UART_CMD_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rda_uart_write(port, (val | RDA_UART_RTS), RDA_UART_CMD_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val = rda_uart_read(port, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val |= RDA_UART_LOOP_BACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val &= ~RDA_UART_LOOP_BACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rda_uart_write(port, val, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void rda_uart_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val &= ~RDA_UART_TX_DATA_NEEDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rda_uart_write(port, val, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val = rda_uart_read(port, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val |= RDA_UART_TX_FIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rda_uart_write(port, val, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void rda_uart_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) val = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val &= ~(RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rda_uart_write(port, val, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Read Rx buffer before reset to avoid Rx timeout interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = rda_uart_read(port, RDA_UART_RXTX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val = rda_uart_read(port, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val |= RDA_UART_RX_FIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rda_uart_write(port, val, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void rda_uart_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (uart_tx_stopped(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rda_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val |= RDA_UART_TX_DATA_NEEDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rda_uart_write(port, val, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void rda_uart_change_baudrate(struct rda_uart_port *rda_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long baud)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_set_rate(rda_port->clk, baud * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void rda_uart_set_termios(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct rda_uart_port *rda_port = to_rda_uart_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int ctrl, cmd_set, cmd_clr, triggers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) baud = uart_get_baud_rate(port, termios, old, 9600, port->uartclk / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rda_uart_change_baudrate(rda_port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ctrl = rda_uart_read(port, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cmd_set = rda_uart_read(port, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cmd_clr = rda_uart_read(port, RDA_UART_CMD_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_warn(port->dev, "bit size not supported, using 7 bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ctrl &= ~RDA_UART_DBITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ctrl |= RDA_UART_DBITS_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* stop bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ctrl |= RDA_UART_TX_SBITS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ctrl &= ~RDA_UART_TX_SBITS_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* parity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (termios->c_cflag & PARENB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctrl |= RDA_UART_PARITY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Mark or Space parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (termios->c_cflag & CMSPAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (termios->c_cflag & PARODD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ctrl |= RDA_UART_PARITY_MARK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ctrl |= RDA_UART_PARITY_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else if (termios->c_cflag & PARODD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ctrl |= RDA_UART_PARITY_ODD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ctrl |= RDA_UART_PARITY_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ctrl &= ~RDA_UART_PARITY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Hardware handshake (RTS/CTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (termios->c_cflag & CRTSCTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ctrl |= RDA_UART_FLOW_CNT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cmd_set |= RDA_UART_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ctrl &= ~RDA_UART_FLOW_CNT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cmd_clr |= RDA_UART_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ctrl |= RDA_UART_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ctrl &= ~RDA_UART_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) triggers = (RDA_UART_AFC_LEVEL(20) | RDA_UART_RX_TRIGGER(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rda_uart_write(port, triggers, RDA_UART_IRQ_TRIGGERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rda_uart_write(port, ctrl, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) rda_uart_write(port, cmd_set, RDA_UART_CMD_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rda_uart_write(port, cmd_clr, RDA_UART_CMD_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rda_uart_write(port, irq_mask, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Don't rewrite B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (tty_termios_baud_rate(termios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tty_termios_encode_baud_rate(termios, baud, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* update the per-port timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void rda_uart_send_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct circ_buf *xmit = &port->state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (uart_tx_stopped(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (port->x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) while (!(rda_uart_read(port, RDA_UART_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) RDA_UART_TX_FIFO_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rda_uart_write(port, port->x_char, RDA_UART_RXTX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) port->x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) while (rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ch = xmit->buf[xmit->tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rda_uart_write(port, ch, RDA_UART_RXTX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) port->icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) uart_write_wakeup(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!uart_circ_empty(xmit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Re-enable Tx FIFO interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) val |= RDA_UART_TX_DATA_NEEDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rda_uart_write(port, val, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void rda_uart_receive_chars(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 status, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) status = rda_uart_read(port, RDA_UART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) while ((status & RDA_UART_RX_FIFO_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) char flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (status & RDA_UART_RX_PARITY_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) port->icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (status & RDA_UART_RX_FRAMING_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) port->icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (status & RDA_UART_RX_OVERFLOW_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) port->icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) flag = TTY_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) val = rda_uart_read(port, RDA_UART_RXTX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) port->icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tty_insert_flip_char(&port->state->port, val, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) status = rda_uart_read(port, RDA_UART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tty_flip_buffer_push(&port->state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static irqreturn_t rda_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct uart_port *port = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 val, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Clear IRQ cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val = rda_uart_read(port, RDA_UART_IRQ_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rda_uart_write(port, val, RDA_UART_IRQ_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (val & (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) rda_uart_receive_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (val & (RDA_UART_TX_DATA_NEEDED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) irq_mask &= ~RDA_UART_TX_DATA_NEEDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rda_uart_write(port, irq_mask, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rda_uart_send_chars(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int rda_uart_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = request_irq(port->irq, rda_interrupt, IRQF_NO_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "rda-uart", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) val = rda_uart_read(port, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val |= RDA_UART_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rda_uart_write(port, val, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* enable rx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val |= (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rda_uart_write(port, val, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void rda_uart_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_lock_irqsave(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rda_uart_stop_tx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rda_uart_stop_rx(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val = rda_uart_read(port, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val &= ~RDA_UART_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rda_uart_write(port, val, RDA_UART_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) spin_unlock_irqrestore(&port->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char *rda_uart_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return (port->type == PORT_RDA) ? "rda-uart" : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int rda_uart_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!devm_request_mem_region(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) resource_size(res), dev_name(port->dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) port->membase = devm_ioremap(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void rda_uart_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (flags & UART_CONFIG_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) port->type = PORT_RDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rda_uart_request_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_lock_irqsave(&port->lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Clear mask, so no surprise interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Clear status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rda_uart_write(port, 0, RDA_UART_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spin_unlock_irqrestore(&port->lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void rda_uart_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct platform_device *pdev = to_platform_device(port->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (port->flags & UPF_IOREMAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) devm_release_mem_region(port->dev, port->mapbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) devm_iounmap(port->dev, port->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) port->membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int rda_uart_verify_port(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (port->type != PORT_RDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (port->irq != ser->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct uart_ops rda_uart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .tx_empty = rda_uart_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .get_mctrl = rda_uart_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .set_mctrl = rda_uart_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .start_tx = rda_uart_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .stop_tx = rda_uart_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .stop_rx = rda_uart_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .startup = rda_uart_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .shutdown = rda_uart_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .set_termios = rda_uart_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .type = rda_uart_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .request_port = rda_uart_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .release_port = rda_uart_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .config_port = rda_uart_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .verify_port = rda_uart_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #ifdef CONFIG_SERIAL_RDA_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void rda_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!port->membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) while (!(rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rda_uart_write(port, ch, RDA_UART_RXTX_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void rda_uart_port_write(struct uart_port *port, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 old_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (port->sysrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else if (oops_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) locked = spin_trylock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_lock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) old_irq_mask = rda_uart_read(port, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) rda_uart_write(port, 0, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) uart_console_write(port, s, count, rda_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* wait until all contents have been sent out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) while (!(rda_uart_read(port, RDA_UART_STATUS) & RDA_UART_TX_FIFO_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rda_uart_write(port, old_irq_mask, RDA_UART_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) spin_unlock(&port->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void rda_uart_console_write(struct console *co, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct rda_uart_port *rda_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rda_port = rda_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!rda_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) rda_uart_port_write(&rda_port->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int rda_uart_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct rda_uart_port *rda_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int baud = 921600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (co->index < 0 || co->index >= RDA_UART_PORT_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) rda_port = rda_uart_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!rda_port || !rda_port->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return uart_set_options(&rda_port->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct console rda_uart_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .name = RDA_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .write = rda_uart_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .setup = rda_uart_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .data = &rda_uart_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int __init rda_uart_console_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) register_console(&rda_uart_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) console_initcall(rda_uart_console_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void rda_uart_early_console_write(struct console *co,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u_int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct earlycon_device *dev = co->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) rda_uart_port_write(&dev->port, s, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rda_uart_early_console_setup(struct earlycon_device *device, const char *opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (!device->port.membase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) device->con->write = rda_uart_early_console_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) OF_EARLYCON_DECLARE(rda, "rda,8810pl-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) rda_uart_early_console_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define RDA_UART_CONSOLE (&rda_uart_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define RDA_UART_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #endif /* CONFIG_SERIAL_RDA_CONSOLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static struct uart_driver rda_uart_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .driver_name = "rda-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .dev_name = RDA_UART_DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .nr = RDA_UART_PORT_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .cons = RDA_UART_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const struct of_device_id rda_uart_dt_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { .compatible = "rda,8810pl-uart" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MODULE_DEVICE_TABLE(of, rda_uart_dt_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int rda_uart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct resource *res_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct rda_uart_port *rda_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (pdev->id < 0 || pdev->id >= RDA_UART_PORT_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!res_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(&pdev->dev, "could not get mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (rda_uart_ports[pdev->id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rda_port = devm_kzalloc(&pdev->dev, sizeof(*rda_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!rda_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rda_port->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (IS_ERR(rda_port->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(&pdev->dev, "could not get clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return PTR_ERR(rda_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rda_port->port.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rda_port->port.regshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rda_port->port.line = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rda_port->port.type = PORT_RDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rda_port->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rda_port->port.mapbase = res_mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rda_port->port.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) rda_port->port.uartclk = clk_get_rate(rda_port->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (rda_port->port.uartclk == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_err(&pdev->dev, "clock rate is zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rda_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) UPF_LOW_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) rda_port->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rda_port->port.fifosize = RDA_UART_TX_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rda_port->port.ops = &rda_uart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) rda_uart_ports[pdev->id] = rda_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) platform_set_drvdata(pdev, rda_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = uart_add_one_port(&rda_uart_driver, &rda_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rda_uart_ports[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int rda_uart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct rda_uart_port *rda_port = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) uart_remove_one_port(&rda_uart_driver, &rda_port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) rda_uart_ports[pdev->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static struct platform_driver rda_uart_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .probe = rda_uart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .remove = rda_uart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .name = "rda-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .of_match_table = rda_uart_dt_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int __init rda_uart_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = uart_register_driver(&rda_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = platform_driver_register(&rda_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) uart_unregister_driver(&rda_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void __exit rda_uart_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) platform_driver_unregister(&rda_uart_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) uart_unregister_driver(&rda_uart_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) module_init(rda_uart_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) module_exit(rda_uart_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_DESCRIPTION("RDA8810PL serial device driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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