^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Based on drivers/serial/8250.c by Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Created: Feb 20, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright: (C) 2003 Monta Vista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Note 1: This driver is made separate from the already too overloaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 8250.c because it needs some kirks of its own and that'll make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * easier to add DMA support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Note 2: I'm too sick of device allocation policies for serial ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * If someone else wants to request an "official" allocation of major/minor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * for this driver please be my guest. And don't forget that new hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * to come from Intel might have more than 3 or 4 of those UARTs. Let's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * hope for a better port registration and dynamic device allocation scheme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * with the serial core maintainer satisfaction to appear soon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sysrq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/tty_flip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PXA_NAME_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct uart_pxa_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned char ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned char lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned char mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int lsr_break_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) char name[PXA_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) offset <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return readl(up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) offset <<= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(value, up->port.membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void serial_pxa_enable_ms(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) up->ier |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void serial_pxa_stop_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (up->ier & UART_IER_THRI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) up->ier &= ~UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void serial_pxa_stop_rx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) up->ier &= ~UART_IER_RLSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) up->port.read_status_mask &= ~UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void receive_chars(struct uart_pxa_port *up, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int ch, flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int max_count = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* work around Errata #20 according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Intel(R) PXA27x Processor Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Specification Update (May 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Step 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Disable the Reciever Time Out Interrupt via IER[RTOEI]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) up->ier &= ~UART_IER_RTOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ch = serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) flag = TTY_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) up->port.icount.rx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UART_LSR_FE | UART_LSR_OE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * For statistics only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (*status & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *status &= ~(UART_LSR_FE | UART_LSR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) up->port.icount.brk++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * We do the SysRQ and SAK checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * here because otherwise the break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * may get masked by ignore_status_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * or read_status_mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (uart_handle_break(&up->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else if (*status & UART_LSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) up->port.icount.parity++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else if (*status & UART_LSR_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) up->port.icount.frame++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (*status & UART_LSR_OE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) up->port.icount.overrun++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Mask off conditions which should be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *status &= up->port.read_status_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_SERIAL_PXA_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (up->port.line == up->port.cons->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Recover the break flag from console xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *status |= up->lsr_break_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) up->lsr_break_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (*status & UART_LSR_BI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) flag = TTY_BREAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else if (*status & UART_LSR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) flag = TTY_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else if (*status & UART_LSR_FE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) flag = TTY_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (uart_handle_sysrq_char(&up->port, ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto ignore_char;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ignore_char:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *status = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } while ((*status & UART_LSR_DR) && (max_count-- > 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tty_flip_buffer_push(&up->port.state->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* work around Errata #20 according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Intel(R) PXA27x Processor Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Specification Update (May 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Step 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) up->ier |= UART_IER_RTOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void transmit_chars(struct uart_pxa_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct circ_buf *xmit = &up->port.state->xmit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (up->port.x_char) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) serial_out(up, UART_TX, up->port.x_char);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) up->port.x_char = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) serial_pxa_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) count = up->port.fifosize / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) serial_out(up, UART_TX, xmit->buf[xmit->tail]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) up->port.icount.tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } while (--count > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) uart_write_wakeup(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (uart_circ_empty(xmit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) serial_pxa_stop_tx(&up->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void serial_pxa_start_tx(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!(up->ier & UART_IER_THRI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) up->ier |= UART_IER_THRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* should hold up->port.lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline void check_modem_status(struct uart_pxa_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) status = serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if ((status & UART_MSR_ANY_DELTA) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (status & UART_MSR_TERI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) up->port.icount.rng++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (status & UART_MSR_DDSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) up->port.icount.dsr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (status & UART_MSR_DDCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (status & UART_MSR_DCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) wake_up_interruptible(&up->port.state->port.delta_msr_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * This handles the interrupt from one port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct uart_pxa_port *up = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int iir, lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) iir = serial_in(up, UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (iir & UART_IIR_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) lsr = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (lsr & UART_LSR_DR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) receive_chars(up, &lsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) check_modem_status(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (lsr & UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) transmit_chars(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static unsigned int serial_pxa_tx_empty(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) status = serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (status & UART_MSR_DCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret |= TIOCM_CAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (status & UART_MSR_RI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret |= TIOCM_RNG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (status & UART_MSR_DSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret |= TIOCM_DSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (status & UART_MSR_CTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret |= TIOCM_CTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned char mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (mctrl & TIOCM_RTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mcr |= UART_MCR_RTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (mctrl & TIOCM_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mcr |= UART_MCR_DTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (mctrl & TIOCM_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mcr |= UART_MCR_OUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (mctrl & TIOCM_OUT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mcr |= UART_MCR_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (mctrl & TIOCM_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mcr |= UART_MCR_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mcr |= up->mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) serial_out(up, UART_MCR, mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (break_state == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) up->lcr |= UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) up->lcr &= ~UART_LCR_SBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) serial_out(up, UART_LCR, up->lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int serial_pxa_startup(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (port->line == 3) /* HWUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) up->mcr |= UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) up->mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) up->port.uartclk = clk_get_rate(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Allocate the IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Clear the FIFO buffers and disable them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * (they will be reenabled in set_termios())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) serial_out(up, UART_FCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Clear the interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) (void) serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (void) serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (void) serial_in(up, UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (void) serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Now, initialize the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) serial_out(up, UART_LCR, UART_LCR_WLEN8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) up->port.mctrl |= TIOCM_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) serial_pxa_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Finally, enable interrupts. Note: Modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * are set via set_termios(), which will be occurring imminently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * anyway, so we don't enable them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * And clear the interrupt registers again for luck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (void) serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) (void) serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (void) serial_in(up, UART_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (void) serial_in(up, UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void serial_pxa_shutdown(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) free_irq(up->port.irq, up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Disable interrupts from this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) up->ier = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) serial_out(up, UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) up->port.mctrl &= ~TIOCM_OUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) serial_pxa_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Disable break condition and FIFOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) UART_FCR_CLEAR_RCVR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) UART_FCR_CLEAR_XMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) serial_out(up, UART_FCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct ktermios *old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned char cval, fcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int baud, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) switch (termios->c_cflag & CSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case CS5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cval = UART_LCR_WLEN5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case CS6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cval = UART_LCR_WLEN6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case CS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) cval = UART_LCR_WLEN7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case CS8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cval = UART_LCR_WLEN8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (termios->c_cflag & CSTOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cval |= UART_LCR_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (termios->c_cflag & PARENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cval |= UART_LCR_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!(termios->c_cflag & PARODD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cval |= UART_LCR_EPAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Ask the core to calculate the divisor for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) quot = uart_get_divisor(port, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if ((up->port.uartclk / quot) < (2400 * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) else if ((up->port.uartclk / quot) < (230400 * 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Ok, we're now changing the port state. Do it with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) spin_lock_irqsave(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Ensure the port will be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * This is required especially for serial console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) up->ier |= UART_IER_UUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Update the per-port timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) uart_update_timeout(port, termios->c_cflag, baud);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (termios->c_iflag & INPCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) up->port.read_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Characters to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) up->port.ignore_status_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (termios->c_iflag & IGNBRK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) up->port.ignore_status_mask |= UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * If we're ignoring parity and break indicators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * ignore overruns too (for real raw support).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (termios->c_iflag & IGNPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) up->port.ignore_status_mask |= UART_LSR_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * ignore all characters if CREAD is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if ((termios->c_cflag & CREAD) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) up->port.ignore_status_mask |= UART_LSR_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * CTS flow control flag and modem status interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) up->ier &= ~UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (UART_ENABLE_MS(&up->port, termios->c_cflag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) up->ier |= UART_IER_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) serial_out(up, UART_IER, up->ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (termios->c_cflag & CRTSCTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) up->mcr |= UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) up->mcr &= ~UART_MCR_AFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * work around Errata #75 according to Intel(R) PXA27x Processor Family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Specification Update (Nov 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dll = serial_in(up, UART_DLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) WARN_ON(dll != (quot & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) serial_out(up, UART_LCR, cval); /* reset DLAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) up->lcr = cval; /* Save LCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) serial_pxa_set_mctrl(&up->port, up->port.mctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) serial_out(up, UART_FCR, fcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_unlock_irqrestore(&up->port.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) serial_pxa_pm(struct uart_port *port, unsigned int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int oldstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_prepare_enable(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_disable_unprepare(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void serial_pxa_release_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int serial_pxa_request_port(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void serial_pxa_config_port(struct uart_port *port, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) up->port.type = PORT_PXA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* we don't want the core code to modify any port params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) serial_pxa_type(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return up->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct uart_pxa_port *serial_pxa_ports[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct uart_driver serial_pxa_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #ifdef CONFIG_SERIAL_PXA_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * Wait for transmitter & holding register to empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void wait_for_xmitr(struct uart_pxa_port *up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unsigned int status, tmout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Wait up to 10ms for the character(s) to be sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) status = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (status & UART_LSR_BI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) up->lsr_break_flag = UART_LSR_BI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (--tmout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Wait up to 1s for flow control if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (up->port.flags & UPF_CONS_FLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) tmout = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) while (--tmout &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void serial_pxa_console_putchar(struct uart_port *port, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) serial_out(up, UART_TX, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Print a string to the serial port trying not to disturb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * any possible real use of the port...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * The console_lock must be held when we get here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct uart_pxa_port *up = serial_pxa_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int locked = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) clk_enable(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (up->port.sysrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) locked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else if (oops_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) locked = spin_trylock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spin_lock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ier = serial_in(up, UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) serial_out(up, UART_IER, UART_IER_UUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) serial_out(up, UART_IER, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_unlock(&up->port.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) clk_disable(up->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #ifdef CONFIG_CONSOLE_POLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * Console polling routines for writing and reading from the uart while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * in an interrupt or debug context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int serial_pxa_get_poll_char(struct uart_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned char lsr = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) while (!(lsr & UART_LSR_DR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) lsr = serial_in(up, UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return serial_in(up, UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void serial_pxa_put_poll_char(struct uart_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct uart_pxa_port *up = (struct uart_pxa_port *)port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * First save the IER then disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ier = serial_in(up, UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) serial_out(up, UART_IER, UART_IER_UUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Send the character out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) serial_out(up, UART_TX, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Finally, wait for transmitter to become empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * and restore the IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) wait_for_xmitr(up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) serial_out(up, UART_IER, ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #endif /* CONFIG_CONSOLE_POLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) serial_pxa_console_setup(struct console *co, char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct uart_pxa_port *up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int baud = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int parity = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int flow = 'n';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (co->index == -1 || co->index >= serial_pxa_reg.nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) co->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) up = serial_pxa_ports[co->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) uart_parse_options(options, &baud, &parity, &bits, &flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return uart_set_options(&up->port, co, baud, parity, bits, flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct console serial_pxa_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .write = serial_pxa_console_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .device = uart_console_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .setup = serial_pxa_console_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .data = &serial_pxa_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define PXA_CONSOLE &serial_pxa_console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define PXA_CONSOLE NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct uart_ops serial_pxa_pops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .tx_empty = serial_pxa_tx_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .set_mctrl = serial_pxa_set_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .get_mctrl = serial_pxa_get_mctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .stop_tx = serial_pxa_stop_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .start_tx = serial_pxa_start_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .stop_rx = serial_pxa_stop_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .enable_ms = serial_pxa_enable_ms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .break_ctl = serial_pxa_break_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .startup = serial_pxa_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .shutdown = serial_pxa_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .set_termios = serial_pxa_set_termios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .pm = serial_pxa_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .type = serial_pxa_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .release_port = serial_pxa_release_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .request_port = serial_pxa_request_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .config_port = serial_pxa_config_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .verify_port = serial_pxa_verify_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .poll_get_char = serial_pxa_get_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .poll_put_char = serial_pxa_put_poll_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static struct uart_driver serial_pxa_reg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .driver_name = "PXA serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .dev_name = "ttyS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .major = TTY_MAJOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .minor = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .nr = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .cons = PXA_CONSOLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int serial_pxa_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct uart_pxa_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) uart_suspend_port(&serial_pxa_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int serial_pxa_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct uart_pxa_port *sport = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) uart_resume_port(&serial_pxa_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct dev_pm_ops serial_pxa_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .suspend = serial_pxa_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .resume = serial_pxa_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct of_device_id serial_pxa_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .compatible = "mrvl,pxa-uart", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .compatible = "mrvl,mmp-uart", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int serial_pxa_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct uart_pxa_port *sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = of_alias_get_id(np, "serial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sport->port.line = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int serial_pxa_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct uart_pxa_port *sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct resource *mmres, *irqres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!mmres || !irqres)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!sport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sport->clk = clk_get(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (IS_ERR(sport->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = PTR_ERR(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = clk_prepare(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_put(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sport->port.type = PORT_PXA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) sport->port.iotype = UPIO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sport->port.mapbase = mmres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) sport->port.irq = irqres->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) sport->port.fifosize = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) sport->port.ops = &serial_pxa_pops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) sport->port.dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) sport->port.uartclk = clk_get_rate(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = serial_pxa_probe_dt(dev, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) sport->port.line = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) sport->port.membase = ioremap(mmres->start, resource_size(mmres));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!sport->port.membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) serial_pxa_ports[sport->port.line] = sport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) uart_add_one_port(&serial_pxa_reg, &sport->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) platform_set_drvdata(dev, sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) clk_unprepare(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk_put(sport->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) kfree(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct platform_driver serial_pxa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .probe = serial_pxa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "pxa2xx-uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .pm = &serial_pxa_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .of_match_table = serial_pxa_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* 8250 driver for PXA serial ports should be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int __init serial_pxa_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = uart_register_driver(&serial_pxa_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = platform_driver_register(&serial_pxa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uart_unregister_driver(&serial_pxa_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) device_initcall(serial_pxa_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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