^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __PMAC_ZILOG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __PMAC_ZILOG_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * At most 2 ESCCs with 2 ports each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define MAX_ZS_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * We wrap our port structure around the generic uart_port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NUM_ZSREGS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct uart_pmac_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct uart_pmac_port *mate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* macio_dev for the escc holding this port (maybe be null on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * early inited port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct macio_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* device node to this port, this points to one of 2 childs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * of "escc" node (ie. ch-a or ch-b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Port type as obtained from device tree (IRDA, modem, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int port_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 curregs[NUM_ZSREGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PMACZILOG_FLAG_IS_CONS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PMACZILOG_FLAG_IS_KGDB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PMACZILOG_FLAG_REGS_HELD 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PMACZILOG_FLAG_TX_STOPPED 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PMACZILOG_FLAG_IS_IRDA 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PMACZILOG_FLAG_HAS_DMA 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PMACZILOG_FLAG_IS_OPEN 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PMACZILOG_FLAG_BREAK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned char parity_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned char prev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) volatile u8 __iomem *control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) volatile u8 __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int tx_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int rx_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) volatile struct dbdma_regs __iomem *tx_dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) volatile struct dbdma_regs __iomem *rx_dma_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned char irq_name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ktermios termios_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define to_pmz(p) ((struct uart_pmac_port *)(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return uap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return uap->mate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Register accessors. Note that we don't need to enforce a recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * though if we try to use this driver on older machines, we might have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * to add it back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (reg != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writeb(reg, port->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return readb(port->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (reg != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writeb(reg, port->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writeb(value, port->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline u8 read_zsdata(struct uart_pmac_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return readb(port->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writeb(data, port->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline void zssync(struct uart_pmac_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (void)readb(port->control_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Conversion routines to/from brg time constants from/to bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* The Zilog register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FLAG 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Write Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R0 0 /* Register selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define R2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define R3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define R4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define R5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define R8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define R9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define R10 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define R11 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R12 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define R13 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define R14 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define R15 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define R7P 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NULLCODE 0 /* Null Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define POINT_HIGH 0x8 /* Select upper half of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SEND_ABORT 0x18 /* HDLC Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RES_Tx_P 0x28 /* Reset TxINT Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ERR_RES 0x30 /* Error Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RES_H_IUS 0x38 /* Reset highest IUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RES_EOM_L 0xC0 /* Reset EOM latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Write Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TxINT_ENAB 0x2 /* Tx Int Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PAR_SPEC 0x4 /* Parity is special condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RxINT_DISAB 0 /* Rx Int Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define INT_ERR_Rx 0x18 /* Int on error only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RxINT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Write Register #2 (Interrupt Vector) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Write Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RxENABLE 0x1 /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ENT_HM 0x10 /* Enter Hunt Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AUTO_ENAB 0x20 /* Auto Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define Rx5 0x0 /* Rx 5 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define Rx7 0x40 /* Rx 7 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define Rx6 0x80 /* Rx 6 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define Rx8 0xc0 /* Rx 8 Bits/Character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RxN_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Write Register 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PAR_ENAB 0x1 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PAR_EVEN 0x2 /* Parity Even/Odd* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SYNC_ENAB 0 /* Sync Modes Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SB1 0x4 /* 1 stop bit/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SB15 0x8 /* 1.5 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SB2 0xc /* 2 stop bits/char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SB_MASK 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MONSYNC 0 /* 8 Bit Sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BISYNC 0x10 /* 16 bit sync character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EXTSYNC 0x30 /* External Sync Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define X1CLK 0x0 /* x1 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define X16CLK 0x40 /* x16 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define X32CLK 0x80 /* x32 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define X64CLK 0xC0 /* x64 clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define XCLK_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Write Register 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RTS 0x2 /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TxENABLE 0x8 /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SND_BRK 0x10 /* Send Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define Tx5 0x0 /* Tx 5 bits (or less)/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define Tx7 0x20 /* Tx 7 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define Tx6 0x40 /* Tx 6 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define Tx8 0x60 /* Tx 8 bits/character */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TxN_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DTR 0x80 /* DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Write Register 7' (Some enhanced feature control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ENEXREAD 0x40 /* Enable read of some write registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Write Register 8 (transmit buffer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Write Register 9 (Master interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VIS 1 /* Vector Includes Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define NV 2 /* No Vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DLC 4 /* Disable Lower Chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MIE 8 /* Master Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define STATHI 0x10 /* Status high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define NORESET 0 /* No reset on write to R9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CHRB 0x40 /* Reset channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CHRA 0x80 /* Reset channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FHWRES 0xc0 /* Force hardware reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Write Register 10 (misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BIT6 1 /* 6 bit/8bit sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define LOOPMODE 2 /* SDLC Loop mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MARKIDLE 8 /* Mark/flag on idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define GAOP 0x10 /* Go active on poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NRZ 0 /* NRZ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define NRZI 0x20 /* NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define FM1 0x40 /* FM1 (transition = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define FM0 0x60 /* FM0 (transition = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CRCPS 0x80 /* CRC Preset I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Write Register 11 (Clock Mode control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TRxCXT 0 /* TRxC = Xtal output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TRxCTC 1 /* TRxC = Transmit clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TRxCBR 2 /* TRxC = BR Generator Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TRxCDP 3 /* TRxC = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TRxCOI 4 /* TRxC O/I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TCRTxCP 0 /* Transmit clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TCTRxCP 8 /* Transmit clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TCBR 0x10 /* Transmit clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TCDPLL 0x18 /* Transmit clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RCRTxCP 0 /* Receive clock = RTxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RCBR 0x40 /* Receive clock = BR Generator output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RCDPLL 0x60 /* Receive clock = DPLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Write Register 12 (lower byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Write Register 13 (upper byte of baud rate generator time constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Write Register 14 (Misc control bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BRENAB 1 /* Baud rate generator enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define BRSRC 2 /* Baud rate generator source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DTRREQ 4 /* DTR/Request function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AUTOECHO 8 /* Auto Echo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LOOPBAK 0x10 /* Local loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SEARCH 0x20 /* Enter search mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RMC 0x40 /* Reset missing clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DISDPLL 0x60 /* Disable DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SSBR 0x80 /* Set DPLL source = BR generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SFMM 0xc0 /* Set FM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SNRZI 0xe0 /* Set NRZI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Write Register 15 (external/status interrupt control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define EN85C30 1 /* Enable some 85c30-enhanced registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ZCIE 2 /* Zero count IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ENSTFIFO 4 /* Enable status FIFO (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DCDIE 8 /* DCD IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SYNCIE 0x10 /* Sync/hunt IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CTSIE 0x20 /* CTS IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TxUIE 0x40 /* Tx Underrun/EOM IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BRKIE 0x80 /* Break/Abort IE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Read Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define Rx_CH_AV 0x1 /* Rx Character Available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define ZCOUNT 0x2 /* Zero count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DCD 0x8 /* DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SYNC_HUNT 0x10 /* Sync/hunt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CTS 0x20 /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TxEOM 0x40 /* Tx underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define BRK_ABRT 0x80 /* Break/Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Read Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ALL_SNT 0x1 /* All sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Residue Data for 8 Rx bits/char programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RES3 0x8 /* 0/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RES4 0x4 /* 0/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RES5 0xc /* 0/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RES6 0x2 /* 0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RES7 0xa /* 0/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RES8 0x6 /* 0/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RES18 0xe /* 1/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RES28 0x0 /* 2/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Special Rx Condition Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PAR_ERR 0x10 /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define Rx_OVR 0x20 /* Rx Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CRC_ERR 0x40 /* CRC/Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define END_FR 0x80 /* End of Frame (SDLC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Read Register 2 (channel b only) - Interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CHB_Tx_EMPTY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CHB_EXT_STAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CHB_Rx_AVAIL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CHB_SPECIAL 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CHA_Tx_EMPTY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CHA_EXT_STAT 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CHA_Rx_AVAIL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CHA_SPECIAL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define STATUS_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Read Register 3 (interrupt pending register) ch a only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CHBTxIP 0x2 /* Channel B Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CHBRxIP 0x4 /* Channel B Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CHATxIP 0x10 /* Channel A Tx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define CHARxIP 0x20 /* Channel A Rx IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Read Register 8 (receive data register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Read Register 10 (misc status bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ONLOOP 2 /* On loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define LOOPSEND 0x10 /* Loop sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CLK2MIS 0x40 /* Two clocks missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CLK1MIS 0x80 /* One clock missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Read Register 12 (lower byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Read Register 13 (upper byte of baud rate generator constant) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Read Register 15 (value of WR 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Misc macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ZS_CLEARFIFO(port) do { volatile unsigned char garbage; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) garbage = read_zsdata(port); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) garbage = read_zsdata(port); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) garbage = read_zsdata(port); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif /* __PMAC_ZILOG_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags