^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PIC32 Integrated Serial Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Microchip Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DT_PIC32_UART_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DT_PIC32_UART_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PIC32_UART_DFLT_BRATE (9600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PIC32_UART_TX_FIFO_DEPTH (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIC32_UART_RX_FIFO_DEPTH (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PIC32_UART_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PIC32_UART_STA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PIC32_UART_TX 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIC32_UART_RX 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIC32_UART_BRG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct pic32_console_opt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int parity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* struct pic32_sport - pic32 serial port descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @port: uart port descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @idx: port index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @irq_fault: virtual fault interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @irqflags_fault: flags related to fault irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @irq_fault_name: irq fault name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @irq_rx: virtual rx interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @irqflags_rx: flags related to rx irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @irq_rx_name: irq rx name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @irq_tx: virtual tx interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @irqflags_tx: : flags related to tx irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @irq_tx_name: irq tx name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @cts_gpio: clear to send gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @dev: device descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pic32_sport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct uart_port port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pic32_console_opt opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int irq_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int irqflags_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const char *irq_fault_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int irq_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int irqflags_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const char *irq_rx_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int irq_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int irqflags_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char *irq_tx_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 enable_tx_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool hw_flow_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int cts_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define to_pic32_sport(c) container_of(c, struct pic32_sport, port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define pic32_get_port(sport) (&sport->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define pic32_get_opt(sport) (&sport->opt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define tx_irq_enabled(sport) (sport->enable_tx_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void pic32_uart_writel(struct pic32_sport *sport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct uart_port *port = pic32_get_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __raw_writel(val, port->membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct uart_port *port = pic32_get_port(sport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return __raw_readl(port->membase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* pic32 uart mode register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PIC32_UART_MODE_ON BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PIC32_UART_MODE_FRZ BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PIC32_UART_MODE_SIDL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PIC32_UART_MODE_IREN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PIC32_UART_MODE_RTSMD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PIC32_UART_MODE_RESV1 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PIC32_UART_MODE_UEN1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PIC32_UART_MODE_UEN0 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PIC32_UART_MODE_WAKE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PIC32_UART_MODE_LPBK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PIC32_UART_MODE_ABAUD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PIC32_UART_MODE_RXINV BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PIC32_UART_MODE_BRGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PIC32_UART_MODE_PDSEL1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PIC32_UART_MODE_PDSEL0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PIC32_UART_MODE_STSEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* pic32 uart status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PIC32_UART_STA_UTXISEL1 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PIC32_UART_STA_UTXISEL0 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PIC32_UART_STA_UTXINV BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PIC32_UART_STA_URXEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PIC32_UART_STA_UTXBRK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PIC32_UART_STA_UTXEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PIC32_UART_STA_UTXBF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PIC32_UART_STA_TRMT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PIC32_UART_STA_URXISEL1 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PIC32_UART_STA_URXISEL0 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PIC32_UART_STA_ADDEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PIC32_UART_STA_RIDLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PIC32_UART_STA_PERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PIC32_UART_STA_FERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PIC32_UART_STA_OERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PIC32_UART_STA_URXDA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif /* __DT_PIC32_UART_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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